Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
  • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
  • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
  • B26D7/00—Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
  • B26D7/08—Means for treating work or cutting member to facilitate cutting
  • B26D7/088—Means for treating work or cutting member to facilitate cutting by cleaning or lubricating
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
  • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
  • B26F3/00—Severing by means other than cutting; Apparatus therefor
  • B26F3/002—Precutting and tensioning or breaking
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
  • B65C—LABELLING OR TAGGING MACHINES, APPARATUS, OR PROCESSES
  • B65C9/00—Details of labelling machines or apparatus
  • B65C9/08—Label feeding
  • B65C9/18—Label feeding from strips, e.g. from rolls
  • B65C9/1896—Label feeding from strips, e.g. from rolls the labels being torn or burst from a strip
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
  • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
  • B65H35/00—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers
  • B65H35/10—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers from or with devices for breaking partially-cut or perforated webs, e.g. bursters
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates

Definitions

• the present invention relates to semiconductor processing and more particularly to a method of forming a planar surface in a semiconductor device.
• the width of these polysilicon lines is determined by a photolithography process.
• photographic techniques are used to transfer an image of the desired polysilicon pattern to the surface of a polysilicon layer within the semiconductor device. Then, after unneeded portions of the polysilicon layer are etched away, the image of the desired polysilicon pattern is manifested within the polysilicon material.
• Figures 1a-c illustrate a method of preparing a semiconductor substrate before deposition of the polysilicon layer from which transistors of the semiconductor device will be formed. For the foregoing reasons it is necessary that the surface of the semiconductor substrate be sufficiently planar before the polysilicon is deposited.
• trenches 11 and 13 are etched into semiconductor substrate 10. Trench regions 11 and 13 are referred to as isolation regions of the semiconductor device because these trenches serve to isolate electrically active components of the device from each other. For example, as illustrated both in cross section 20 and surface view 21 of semiconductor substrate 10, isolation region 11 is used to isolate region 12 from region 14 while isolation region 13 is used to isolate region 14 from region 15.
• Unetched regions 12, 14 and 15 are called active regions of the semiconductor device because electrically active components of the semiconductor device, such as transistors, are formed in these regions. Because isolation regions serve to isolate active regions from each other, transistors formed in active region 12 are allowed to operate independently of transistors formed in region 14. Likewise, transistors formed in region 14 are allowed to operate independently of transistors formed in region 15. Typically, isolation regions of a semiconductor device are of significantly varying widths. As illustrated, width 16 of isolation region 11 is much narrower than width 17 of isolation region 13. After trenches are etched into the semiconductor substrate, a dielectric material is deposited as illustrated in Figure 1 b. Dielectric layer 18 will coat the surface of semiconductor substrate 10, filling the trenches and covering the active regions.
• dielectric layer 18 As dielectric layer 18 is etched back to the surface of semiconductor substrate 10, the dip in the surface of dielectric layer 18 over isolation region 13 is propagated into the dip of dielectric layer 18 within isolation region 13 illustrated in Figure 1c.
• dielectric layer 18 is a lower density than semiconductor substrate 10, it is polished at a faster rate than semiconductor substrate 10, which also contributes to this dip.
• narrow trench isolation region 11 Narrow isolation regions such as this tend to exhibit more planarized topographies than wider isolation regions.
• the chemical mechanical polish process used to etch back the dielectric layer is typically optimized to planarize narrow isolation regions rather than wide isolation regions. Also, the higher density of the semiconductor substrate material in this region improves the end-pointing of the chemical mechanical polish.
• What is desired is a method for forming isolation regions in a semiconductor substrate wherein the surface of the substrate is substantially planarized. In this manner, problems associated with polysilicon line width variation and semiconductor substrate damage can be reduced or eliminated, resulting in more reliable and better performing semiconductor devices.
• a method of forming a substantially planar surface over a trench isolation region of a semiconductor substrate is described. Latent active regions are formed within the trench isolation region. A dielectric layer is then deposited over the surface of the semiconductor substrate. Then, the dielectric layer is polished back to form a planar surface.
• Figure 1a is an illustration of a cross sectional and surface view of a substrate after being etched.
• Figure 1b is an illustration of a cross sectional view of the substrate of Figure 1a after a layer has been deposited.
• Figure 1c is an illustration of a cross sectional view of the substrate of Figure 1 b after the layer has been etched back.
• Figure 2a is an illustration of a cross sectional and surface view of a substrate after being etched in accordance with the present invention.
• Figure 2b is an illustration of a cross sectional view of the substrate of Figure 2a after a layer has been deposited.
• Figure 2c is an illustration of a cross sectional view of the substrate of Figure 2b after the layer has been etched back.
• Figure 3a is an illustration of a cross sectional view of a substrate after being etched.
• Figure 3b is an illustration of a cross sectional view of the substrate of Figure 3a after a layer has been deposited.
• Figure 3c is an illustration of a cross sectional view of the substrate of Figure 3b after the layer has been etched back.
• a semiconductor substrate is a substrate comprising any material or materials used in the manufacture of a semiconductor device.
• a substrate is a structure on which or to which a processing step acts upon.
• isolation region 13 of figure 1a is modified to form isolation region 33 of Figure 2a.
• isolation region 33 of Figure 2a have been formed active regions 42.
• active regions 42 are formed within what was formerly the large isolation region 13.
• Active regions 42 are formed in the same process step as active regions 32, 34, and 35 by blocking the anisotropic etch of trenches 31 and 33. Therefore, technically, only the remaining etched regions of trench isolation region 33 surrounding active regions 42 are still the true isolation regions within what would otherwise have been the wider trench isolation region of the device.
• active regions 42 are only active insofar as they are capable of sustaining transistors as are active regions 32, 34, and 35. But in accordance with the present invention, unlike active regions 32, 34, and 35, no transistors or any other semiconductor device components are formed in active regions 42. For this reason, active regions 42 are referred to as latent active regions.
• trench isolation region 33 if properly located, does not significantly impact the isolation properties of the isolation region. Even though the effective area of isolation within trench isolation region 33 is diminished by the incorporation of latent active regions 42, trench isolation region 33 is still able to adequately isolate active region 34 from active region 35. As a result, the performance of isolation regions of semiconductor devices modified in accordance with the present invention is not significantly hindered. Therefore, since the size, shape, and method of forming the isolation region need not be modified to preserve its isolation properties, the present invention may be easily incorporated into virtually any semiconductor device manufacturing method utilizing trench isolation regions.
• the density of active regions within isolation region 33 is increased to more closely approximate the relative density of active regions elsewhere in the semiconductor device.
• the sizes, shapes, and placement of latent active regions 42 within isolation region 33 are specifically selected to achieve a particular density of active regions within the trench.
• the latent active regions are designed such that the proportion of active region to isolation region within the trench is approximately equal to the proportion of active region to isolation region of the most densely compacted active and isolation region elsewhere in the semiconductor device. Then, by optimizing the chemical mechanical polishing process to form a planarized surface over a semiconductor substrate area having this particular proportion of active region to isolation region, the entire surface the semiconductor substrate will be planarized.
• active regions 32 and 34 and isolation region 31 represent the most densely compacted active and isolation region on semiconductor substrate 30. If this were a microprocessor, this area of the semiconductor substrate may be a cell in the static random access memory (SRAM) portion of the semiconductor substrate where transistor density is at a maximum. As described above in conjunction with Figures 1a-c, this area is already adequately planarized by optimization of the chemical mechanical polish process. Therefore, by making isolation region 33 look more like the SRAM cell by introducing latent active regions 42 into the trench, the planarization of isolation region 33 will be similarly improved.
• SRAM static random access memory
• latent active regions 42 within isolation region 33 are chosen such that the functionality of the semiconductor device is not substantially altered by the presence of these active regions.
• an active region pattern comprising latent active regions 42 is defined wherein the sizes, shapes, and spacings of the latent active regions are selected in light of the considerations described above.
• an isolation region is identified into which the active region pattern comprising latent active regions 42 will be placed. This is accomplished by locating an isolation region having dimensions large enough to accommodate active regions formed therein. For example, width 36 of isolation region 31 is too narrow for active regions to be formed therein, but width 37 of isolation region 33 is large enough to accommodate the small, latent active regions 42.
• latent active regions 42, and the spacings 44 between them are selected so as to raise the density of active regions within isolation region 33 to approach the density of active regions in an area elsewhere in the semiconductor device.
• the size and shape of latent active regions 42, and the spacings 44 between them must also abide by the design rules of the process technology used to manufacture the semiconductor device. For example, minimum spacing and minimum dimension rules, which change according to the process technology employed, limit the spacings and dimensions of the latent active regions.
• latent active regions are selectively removed from the isolation region which may interfere with or otherwise alter the functionality of the device.
• latent active region 42 must be placed a safe distance 43 from adjacent active region 34.
• latent active region 42 must also be placed a safe distance 45 from active region 35. The distances 43 and 45 are determined by the practitioner such that latent active regions 42 do not violate minimum dimension design rules or interfere with the operation of any semiconductor device components such as, for example, transistors within active regions 34 and 35 respectively.
• any latent active regions within isolation region 33 which would underlie a polysilicon line are removed. Otherwise, a breakdown of the gate oxide separating a polysilicon line from a latent active region in isolation region 33 could cause the gates of nearby transistors to be shorted to the substrate, destroying operation of the semiconductor device.
• latent active regions within isolation region 33 which would underlie a polysilicon line should be removed to avoid creating a parasitic conductive channel by polysilicon voltage induced inversion within the isolation region, thereby destroying the isolation properties of the region.
• any latent active region 42 within isolation region 33 which would incorporate a well boundary of the well diffusion regions between active region 34 and 35 is removed. This is done to prevent problems such as shorting adjacent well regions to each other. For example, if the surface of a latent active region incorporating a well boundary is suicided, the suicide may electrically couple one well to the other at the surface of the latent active region. By shorting the wells together in this manner, operation of the semiconductor device is destroyed. In general, latent active regions 42 are not placed at any location within isolation region 33 that might detrimentally alter the functionality of the semiconductor device.
• latent active regions may be designed into what would otherwise be a large isolation region of the semiconductor device by any one of a number of other methods suitable to the design methodologies which the practitioner employs.
• a practitioner may wish to, for example, avoid placing the latent active regions within portions of the isolation region which underlie any polysilicon or other layer for some of the same concerns described above.
• the latent active regions within the isolation region may even be placed in a location within the isolation region which does alter the functionality of the semiconductor device. In such an embodiment, a practitioner may be willing to sacrifice some alteration of the functionality of the semiconductor device in exchange for gaining improved planarity.
• Dielectric layer 38 comprises silicon dioxide (oxide) material and is deposited by a method which provides adequate filling of regions 31 and 33, plus enough additional oxide to form a substantial surface above semiconductor substrate 30 which can be etched back. Note that the dip in dielectric layer 18 over isolation region 13 illustrated in Figure 1 b is not exhibited by the dielectric layer formed in accordance with the present invention as illustrated in Figure 2b. Active regions 42 within isolation region 33 have served to raise the surface of dielectric layer 38 within this region. Modifying the surface topography of dielectric 38 by modifying the underlying topography of semiconductor substrate 30 in this manner improves the planarizing effectiveness of the subsequent chemical mechanical polishing process.
• Figure 2c illustrates the semiconductor substrate of Figure 2b after dielectric layer 38 has been chemically mechanically polished back to the surface of semiconductor substrate 30. Note the significant improvement in the surface planarity of the substrate illustrated in Figure 2c versus an analogous cross section of the substrate illustrated in Figure 1c.
• the mechanisms by which the abrupt corner regions 19 were formed in isolation region 13 of Figure 1c have been counteracted by the presence of latent active regions 42 within isolation region 33 of Figure 2c.
• active regions 42 have raised the surface of dielectric layer 38 formed above isolation region 33, thereby eliminating any dips in the dielectric layer formed above this region.
• the presence of the higher density latent active regions 42 within isolation region 33 has prevented the chemical mechanical polish from over- etching the lower density oxide material of dielectric layer 38 within the isolation region.
• the subsequently formed polysilicon layer By forming substantially planar active and isolation regions from the semiconductor substrate, the subsequently formed polysilicon layer will also be planarized. Thus, the entire polysilicon layer surface will reside within a single focal plane of the photolithographic technology used to define the polysilicon lines, substantially reducing or eliminating polysilicon line width variation. As a result, the problems associated with polysilicon line width variation such as, for example, a loss in design efficiency, degraded transistor reliability, and slow transistor switching speeds, are significantly reduced or eliminated.
• a single, large latent active region is formed within the isolation region to improve the planarity at the surface of the isolation region.
• the shape of latent active regions designed into what would otherwise have been a large trench isolation region of the semiconductor device may be any regular or irregular polygon, rounded figure, or a combination of shapes.
• these latent active regions may form any regular or irregular pattern or sequence, or may even be randomly staggered.
• An important consideration is merely that a "high region" such as, for example, a latent active region in a trench, is formed in a portion of what would otherwise have been a larger "low region" of the substrate such as, for example, the trench isolation region itself.
• the dielectric layer used to fill the trench isolation regions comprises a substantially undoped oxide such as thermal oxide, borosiiicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon nitride, polysilicon, or any other material suitable for filling a trench isolation region.
• the dielectric layer comprises a multi-layer stack wherein the etched trenched regions of a silicon substrate are oxidized to form a thin thermal oxide layer over which BPSG is deposited.
• the dielectric layer may be etched back to the surface of the semiconductor substrate using an alternate etching technique or combination of techniques including, for example, purely mechanical polishing, wet etching, or dry etching.
• methods in accordance with the present invention may be implemented in a damascene process where high regions are designed and formed into what would otherwise have been a wide, low region of a dielectric substrate.
• a conductive material is then deposited over the surface of the dielectric substrate, substantially filling any gaps and coating the high and low regions of the substrate.
• the conductive material Upon etching back the conductive material to the surface of the dielectric substrate using a chemical mechanical polish, the conductive material will become isolated within the low regions of the substrate, forming interconnect lines of the semiconductor device.
• the presence of the high dielectric regions are used to prevent, for example, over- etching the surface of wide interconnect lines.
• Figures 3a-c illustrate an embodiment of the present invention in which a planar surface is formed from an interlayer dielectric (ILD) material.
• the ILD is used to physically and electrically isolate an entire layer of interconnects formed underneath the ILD from another layer of interconnects formed on the upper surface of the ILD.
• the ILD additionally serves to isolate one interconnect line from an adjacent interconnect line within the same layer of metal interconnects of the semiconductor device.
• Figure 3a illustrates a cross section of a portion of a semiconductor device in which metal interconnect lines 61 , necessary for proper operation of the semiconductor device, have been formed on top of substrate 60.
• Substrate 60 comprises the semiconductor materials used to form various components of the semiconductor device in lower layers.
• high regions 62 are designed into the wide low region between metal interconnect lines 61.
• High regions 62 are designed, patterned and formed from the same metal layer from which metal interconnect lines 61 are formed.
• High regions 62 are placed a sufficient distance from neighboring interconnect lines 61 so as not to alter the functionality of the semiconductor device. For example, high regions 62 must be located far enough away from interconnect lines 61 to not only satisfy minimum spacing design rules for the particular process technology employed but also to prevent detrimental cross-capacitive effects between adjacent metal lines.
• the effects high regions 62 have on the functionality of the semiconductor device are considered with respect to the placement of high regions 62 in the vicinity of interconnect lines in interconnect layers above and below the presently illustrated layer of the semiconductor device. Again, cross-capacitive effects are an important concern here as well.
• Figure 3b illustrates the substrate of Figure 3a after a dielectric layer 63 has been deposited over the surface of the substrate.
• the dip 65 in the surface of dielectric layer 63 is illustrated as it would be formed in the absence of high regions 62. In the presence of high regions 62, however, the surface of dielectric layer 63 will take the profile illustrated by dotted line 64. Note how modifying the topography of the substrate underlying dielectric layer 63 by adding high regions 62 has eliminated the dip in the dielectric layer above this region.
• Figure 3c illustrates the substrate of Figure 3b after a portion of dielectric layer 63 has been etched back using a chemical mechanical polish to form an ILD surface for the next layer of interconnects.
• dip 65 in Figure 3b has caused the non- planar topography 67 illustrated in Figure 3c.
• the chemical mechanical process used to form the final ILD surface will propagate dip 65 down into the final ILD surface forming dip 67.
• Dip 67 causes problems with the subsequently formed layer of interconnects, particularly in defining the line width of the interconnects using a photolithography process, as described above.
• the cross-sectional profile 64 of dielectric layer 63 is more effectively planarized.
• the result of a chemical mechanical polish of dielectric layer 63 in the presence of high regions 62 is illustrated by dotted line 66 in Figure 3c.
• the presence of high regions 62 has improved the planarity of the surface of the ILD layer so that a subsequently formed metal interconnect layer exhibits reduced line width variation thereby aiding in semiconductor device miniaturization efforts.
• similar results may be achieved by etching back dielectric layer 63 using a mechanical polish, wet etch, dry etch, or a combination of techniques.
• Planarity is achieved by modifying the topography of the underlying substrate.

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Cited By (17)

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• 1995
  • 1995-10-20 TW TW084111123A patent/TW299458B/zh active
  • 1995-11-13 CN CN95197102A patent/CN1171166A/zh active Pending
  • 1995-11-13 EP EP95940684A patent/EP0791227A4/en not_active Withdrawn
  • 1995-11-13 KR KR1019970703143A patent/KR970707582A/ko not_active Application Discontinuation
  • 1995-11-13 JP JP8516234A patent/JPH10512098A/ja active Pending
  • 1995-11-13 WO PCT/US1995/014681 patent/WO1996015552A1/en not_active Application Discontinuation
  • 1995-11-13 AU AU42351/96A patent/AU4235196A/en not_active Abandoned

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