EP0791227A4 - FORMATION OF A FLAT SURFACE ON A SUBSTRATE BY MODIFICATION OF ITS TOPOGRAPHY - Google Patents

FORMATION OF A FLAT SURFACE ON A SUBSTRATE BY MODIFICATION OF ITS TOPOGRAPHY

Info

Publication number
EP0791227A4
EP0791227A4 EP95940684A EP95940684A EP0791227A4 EP 0791227 A4 EP0791227 A4 EP 0791227A4 EP 95940684 A EP95940684 A EP 95940684A EP 95940684 A EP95940684 A EP 95940684A EP 0791227 A4 EP0791227 A4 EP 0791227A4
Authority
EP
European Patent Office
Prior art keywords
substrate
topography
modifying
forming
planar surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95940684A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0791227A1 (en
Inventor
Peter K Moon
Ananda G Sarangi
Timothy L Deeter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP0791227A1 publication Critical patent/EP0791227A1/en
Publication of EP0791227A4 publication Critical patent/EP0791227A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26D—CUTTING; DETAILS COMMON TO MACHINES FOR PERFORATING, PUNCHING, CUTTING-OUT, STAMPING-OUT OR SEVERING
    • B26D7/00—Details of apparatus for cutting, cutting-out, stamping-out, punching, perforating, or severing by means other than cutting
    • B26D7/08—Means for treating work or cutting member to facilitate cutting
    • B26D7/088—Means for treating work or cutting member to facilitate cutting by cleaning or lubricating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B26—HAND CUTTING TOOLS; CUTTING; SEVERING
    • B26F—PERFORATING; PUNCHING; CUTTING-OUT; STAMPING-OUT; SEVERING BY MEANS OTHER THAN CUTTING
    • B26F3/00—Severing by means other than cutting; Apparatus therefor
    • B26F3/002—Precutting and tensioning or breaking
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65C—LABELLING OR TAGGING MACHINES, APPARATUS, OR PROCESSES
    • B65C9/00—Details of labelling machines or apparatus
    • B65C9/08—Label feeding
    • B65C9/18—Label feeding from strips, e.g. from rolls
    • B65C9/1896—Label feeding from strips, e.g. from rolls the labels being torn or burst from a strip
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
    • B65H35/00—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers
    • B65H35/10—Delivering articles from cutting or line-perforating machines; Article or web delivery apparatus incorporating cutting or line-perforating devices, e.g. adhesive tape dispensers from or with devices for breaking partially-cut or perforated webs, e.g. bursters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Forests & Forestry (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
EP95940684A 1994-11-10 1995-11-13 FORMATION OF A FLAT SURFACE ON A SUBSTRATE BY MODIFICATION OF ITS TOPOGRAPHY Withdrawn EP0791227A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US337000 1989-04-12
US33700094A 1994-11-10 1994-11-10
PCT/US1995/014681 WO1996015552A1 (en) 1994-11-10 1995-11-13 Forming a planar surface over a substrate by modifying the topography of the substrate

Publications (2)

Publication Number Publication Date
EP0791227A1 EP0791227A1 (en) 1997-08-27
EP0791227A4 true EP0791227A4 (en) 1998-04-01

Family

ID=23318670

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95940684A Withdrawn EP0791227A4 (en) 1994-11-10 1995-11-13 FORMATION OF A FLAT SURFACE ON A SUBSTRATE BY MODIFICATION OF ITS TOPOGRAPHY

Country Status (7)

Country Link
EP (1) EP0791227A4 (zh)
JP (1) JPH10512098A (zh)
KR (1) KR970707582A (zh)
CN (1) CN1171166A (zh)
AU (1) AU4235196A (zh)
TW (1) TW299458B (zh)
WO (1) WO1996015552A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5665633A (en) 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
DE19703611A1 (de) * 1997-01-31 1998-08-06 Siemens Ag Anwendungsspezifisches integriertes Halbleiterprodukt mit Dummy-Elementen
JP3638778B2 (ja) 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP2006128709A (ja) * 1997-03-31 2006-05-18 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP5600280B2 (ja) * 1997-03-31 2014-10-01 ルネサスエレクトロニクス株式会社 半導体集積回路装置
EP0939432A1 (de) * 1998-02-17 1999-09-01 Siemens Aktiengesellschaft Verfahren zum Entwurf einer Maske zur Herstellung eines Dummygebiets in einem Isolationsgrabengebiet zwischen elektrisch aktiven Gebieten einer mikroelektronischen Vorrichtung
JP2000124305A (ja) 1998-10-15 2000-04-28 Mitsubishi Electric Corp 半導体装置
JP2000340529A (ja) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体装置
US6396158B1 (en) 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
JP4307664B2 (ja) 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
US6459156B1 (en) 1999-12-22 2002-10-01 Motorola, Inc. Semiconductor device, a process for a semiconductor device, and a process for making a masking database
JP4767390B2 (ja) * 2000-05-19 2011-09-07 エルピーダメモリ株式会社 Ｄｒａｍ
US6614062B2 (en) 2001-01-17 2003-09-02 Motorola, Inc. Semiconductor tiling structure and method of formation
US6611045B2 (en) 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
US6989229B2 (en) 2003-03-27 2006-01-24 Freescale Semiconductor, Inc. Non-resolving mask tiling method for flare reduction
JP4987254B2 (ja) 2005-06-22 2012-07-25 株式会社東芝 半導体装置の製造方法
FR2923914B1 (fr) 2007-11-21 2010-01-08 Commissariat Energie Atomique Dispositif pour mesures d'epaisseur et de resistivite carree de lignes d'interconnexions

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6392042A (ja) * 1986-10-06 1988-04-22 Nec Corp 半導体装置の製造方法
JPH0382053A (ja) * 1989-08-24 1991-04-08 Nec Corp 半導体装置
EP0545263A2 (en) * 1991-11-29 1993-06-09 Sony Corporation Method of forming trench isolation having polishing step and method of manufacturing semiconductor device
JPH05258017A (ja) * 1992-03-11 1993-10-08 Fujitsu Ltd 半導体集積回路装置及び半導体集積回路装置の配線レイアウト方法
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186342A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6015944A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd 半導体装置
JPS63240045A (ja) * 1987-03-27 1988-10-05 Matsushita Electric Ind Co Ltd 半導体装置
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
US5265378A (en) * 1992-07-10 1993-11-30 Lsi Logic Corporation Detecting the endpoint of chem-mech polishing and resulting semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6392042A (ja) * 1986-10-06 1988-04-22 Nec Corp 半導体装置の製造方法
JPH0382053A (ja) * 1989-08-24 1991-04-08 Nec Corp 半導体装置
EP0545263A2 (en) * 1991-11-29 1993-06-09 Sony Corporation Method of forming trench isolation having polishing step and method of manufacturing semiconductor device
JPH05258017A (ja) * 1992-03-11 1993-10-08 Fujitsu Ltd 半導体集積回路装置及び半導体集積回路装置の配線レイアウト方法
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 328 (E - 654) 6 September 1988 (1988-09-06) *
PATENT ABSTRACTS OF JAPAN vol. 015, no. 254 (E - 1083) 27 June 1991 (1991-06-27) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 024 (P - 1675) 14 January 1994 (1994-01-14) *
See also references of WO9615552A1 *

Also Published As

Publication number Publication date
AU4235196A (en) 1996-06-06
EP0791227A1 (en) 1997-08-27
JPH10512098A (ja) 1998-11-17
WO1996015552A1 (en) 1996-05-23
TW299458B (zh) 1997-03-01
CN1171166A (zh) 1998-01-21
KR970707582A (ko) 1997-12-01

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