WO1996012295A1 - A novel via hole profile and method of fabrication - Google Patents

A novel via hole profile and method of fabrication Download PDF

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Publication number
WO1996012295A1
WO1996012295A1 PCT/US1995/009529 US9509529W WO9612295A1 WO 1996012295 A1 WO1996012295 A1 WO 1996012295A1 US 9509529 W US9509529 W US 9509529W WO 9612295 A1 WO9612295 A1 WO 9612295A1
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WIPO (PCT)
Prior art keywords
interconnection
layer
conductive layer
via connection
opening
Prior art date
Application number
PCT/US1995/009529
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English (en)
French (fr)
Inventor
Alan M. Myers
Peter K. Charvat
Thomas A. Letson
Shi-Ning Yang
Peng Bai
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to GB9706661A priority Critical patent/GB2308234B/en
Priority to JP8513200A priority patent/JPH10507315A/ja
Priority to KR1019970702511A priority patent/KR100274138B1/ko
Priority to AU31521/95A priority patent/AU3152195A/en
Publication of WO1996012295A1 publication Critical patent/WO1996012295A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Definitions

  • the present invention relates to the field of semiconductor integrated circuit and more specifically to a novel interconnection structure for an integrated circuit and its method of fabrication.
  • Modern integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors, and resistors. These devices are initially isolated from one another but are later interconnected together to form functional circuits. The quality of the interconnection structure drastically affects the performance and reliability of the fabricated circuit. Interconnections are increasingly determining the limits of performance and density of modem ultra large scale integrated (ULSI) circuits.
  • ULSI ultra large scale integrated
  • Figure 1 a is a cross-sectional illustration of an interconnection structure which is presently used in the semiconductor industry.
  • active devices such as transistors and capacitors.
  • Interconnection lines 104 and 106 which are typically aluminum or aluminum alloys, are used to couple active devices into functional circuits.
  • Metal interconnections 104 and 106 and substrate 102 are electrically isolated from one another by interlevel dielectric's (ILDs) 108 and 110, respectively. Electrical connections are made between metal interconnections 104 and 106 through the use of metal, typically tungsten, vias or plugs 112.
  • ILDs interlevel dielectric's
  • Via delamination is a physical separation 114 between a via and the underlying metal interconnect as shown in Figure 1 b. Physical separation between a via connection and an underlying metal interconnection can cause open circuits to be formed resulting in complete failure of the device or circuit.
  • via delamination is most likely the result of several factors including: high stresses in the ILD, interconnection, and via materials, contaminated metal interconnection/plug interfaces, and weak interconnection/ILD and interconnection/plug interfaces.
  • the device is subjected to substantial thermal cycling. For example, various temperature conditions are encountered throughout the entire manufacturing process and packaging of the device. Additionally, during device operation, large current densities flow through vias and interconnections causing temperature increases in high resistance areas such as the interface between vias and the underlying interconnection.
  • the via connections are subjected to large amounts of stress as the device is temperature cycled. Additionally, various residues consisting of fluorides and oxides, formed during the via etch process, are generally left at the interface prior to via metallization. These fluorides and oxides are generally brittle materials and when subjected to large amounts of thermal stress, crack and cause via delamination.
  • a novel interconnection structure which prevents via delamination is described.
  • a multilayer interconnection comprising a titanium aluminide electromigration shunt layer, an aluminum alloy bulk conductor, and a titanium aluminide capping layer is formed on an insulating layer of a semiconductor substrate.
  • a second insulating layer is formed on and around the multilayer interconnection.
  • a via connection comprising tungsten has a first portion with a first width which extends through the insulating layer and through the capping layer of the interconnection line, and a second portion wider than the first portion, which is formed on the bulk conductor and underneath the capping layer to thereby lock the via connection into the interconnection.
  • Figure 1a is a cross-sectional illustration of a prior art interconnection structure.
  • Figure 1b is an illustration of a delaminated via in a prior art interconnection structure.
  • Figure 2 is an illustration of a cross-sectional view of a preferred embodiment of a novel interconnection structure of the present invention.
  • Figure 3a is an illustration of a cross-sectional view showing a semiconductor substrate having an insulating layer formed thereon, and a plurality of metal layers formed on the insulating layer.
  • Figure 3b is an illustration of a cross-sectional view showing the patterning of the metal layers on the substrate of Figure 3a into an interconnection line.
  • Figure 3c is an illustration of a cross-sectional view showing the formation of a via opening on the substrate of Figure 3b.
  • Figure 3d is an illustration of a cross-sectional view showing the formation of an anchor opening in the interconnection line on the substrate of Figure 3c.
  • Figure 3e is an illustration of a cross-sectional view showing the formation of a via connection in the substrate of Figure 3d.
  • Figure 3f is an illustration of a cross-sectional view showing the formation of a second interconnection on the substrate of Figure 3e.
  • the present invention describes a novel high-density, high- reliability, high-performance interconnection structure with a USI manufacturable process.
  • numerous specific details are set forth, such as specific materials, processes, and equipment in order to provide a thorough understanding of the present invention. It will be obvious however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instance, well-known semiconductor manufacturing materials, processes, and equipment have not been set forth in detail in order to not unnecessarily obscure the present invention.
  • the interconnection structure 200 of the present invention includes a first multilayer interconnect formed on an insulating layer 204. Insulating layer 204 is in turn formed on or above a semiconductor substrate 206. Semiconductor substrate 206 contains a plurality of active and passive devices such as transistors, capacitors, and resistors which are coupled together into functional circuits, such as microprocessor and memory devices, by the interconnection structure of the present invention.
  • Multilayer interconnect 202 preferably comprises a conductive capping layer 226 preferably a refractory metal compound, a bulk conductor 224, preferably an aluminum alloy, and an electromigration shunt layer 222 preferably a refractory metal compound. Additionally, a anti-reflective coating (ARC) 228, such as TiN, may be formed on interconnection 202, if desired.
  • a second interconnection 208 preferably a multilayer interconnection similar to interconnection 202, is separated and electrically isolated from first interconnection 202 by an insulator or interlayer dielectric (ILD) 210. Interconnection 202 is electrically coupled to interconnect 208 by via connection 212.
  • ILD interlayer dielectric
  • connection 212 is anchored into interconnection line 202.
  • Via connection 212 has a first narrow portion 214 which extends through ILD 210, ARC 228, and capping layer 226.
  • Via connection 212 also contains a second wider portion 216 formed in bulk conductor 224 which undercuts capping layer 226 of interconnection 202. Because the bond between capping layer 226 and bulk conductor 224 is made strong, via connection 212 is securely anchored into interconnection 202.
  • Via connection 212 is said to undercut interconnection 202 because via connection 212 has a top portion 214 in interconnection 202 which is thinner than a lower portion 216 of via connection 212 in interconnection 202.
  • connection 212 By anchoring via connection 212 into interconnection 202, there is no need to rely upon a strong mechanical bond between via connection 212 and underlying interconnection 202 to prevent via delamination. By anchoring via connection 212 into interconnection 202, via delamination is prevented in the present invention.
  • anchor portion 216 of via connection 212 is formed entirely within and surrounded by interconnection 202 and does not simply rest on the outer surface of interconnection 202. Additionally, according to the present invention, capping layer 226 is formed thick enough to provide sufficient mechanical strength to prevent via connection 212 from pulling away or delaminating from interconnection 202 during subsequent device processing or device operation. A capping layer of between 300 - 1 ,50 ⁇ A provides sufficient mechanical strength to prevent via delamination.
  • anchor 216 of via connection 212 undercuts capping layer 226 by an amount sufficient to lock via connection 212 securely in place. Minimal undercutting will result in poor mechanical anchoring, while too large of undercutting adversely effects via packing density. Undercutting capping layer 212 by between 500 - 1 ,50 ⁇ A provides sufficient anchoring of via connection 212 while still allowing high density placement of vias across a semiconductor device.
  • a valuable feature in the preferred embodiment of the present invention is the use of an aluminum alloy layer (aluminum-copper) as the bulk conductor 224 and the use of a refractory metal-aluminum layer as capping layer 226.
  • capping layer 226 can be chemically reacted with and bonded to bulk conductor 224. By reacting capping layer 226 and bulk conductor 224 together, the capping layer has significantly stronger mechanical strength, than if a non-reactive capping layer was used. Because capping layer 226 has a strong mechanical bond to bulk conductor 224, a strong interface between via connection 212 and interconnection 202 is formed.
  • refractory metal capping layer 226 and a refractory metal electromigration shunt layer 222 are very resistant to electromigration.
  • a continuous shunt layer is provided which prevents electromigration failures in the interconnection.
  • refractory metal conductors are higher in resistance than aluminum alloy layers, thus a tradeoff must be made between electromigration resistance and interconnection electrical resistance.
  • a refractory metal electromigration shunt layer 222 of between 300 - 100 ⁇ A provides a good balance between electrical performance and reliability.
  • anchor 216 extends to a depth beneath capping layer 226 which is sufficient to lock via connection 212 securely in place.
  • Anchor 216 preferably does not extend into electromigration shunt layer 222 so that the electromigration resistance of interconnection 202 is not impeded.
  • a via connection which extends from 1 ,000 - 3,50 ⁇ A into an approximately 4,OO ⁇ A bulk conductor 224 is sufficient.
  • the exact depth at which anchor 216 extends into bulk conductor 224 is immaterial as long as anchor 216 extends deep enough into bulk conductor 224 to provide sufficient mechanical strength to lock via connection 212 into place.
  • via connection 212 has a very large interfacial contact area with interconnection 202.
  • Via connection 212 has an interfacial contact with the vertical sides of capping layer 226, the underside of capping layer 226, as well as a large area contact with bulk conductor 224.
  • the large interfacial contact area between via connection 212 and interconnection 202 improves both performance and reliability of the interconnection structure 200 of the present invention.
  • the large interfacial contact area improves reliability by providing a large surface area for mechanical bonding between via connection 212 and interconnection 202. Additionally, the large interfacial contact area improves performance by decreasing contact resistance between via connection 212 and interconnection 202.
  • Figures 3a - 3f illustrates the preferred interconnection structure of the present invention.
  • a semiconductor substrate including to but not limited to, silicon and gallium arsenide is provided.
  • a plurality of devices such as transistors and capacitors, are formed in and on substrate 302 with well-known techniques.
  • an insulating layer 304 or an ILD, such as doped or undoped silicon dioxide is formed over substrate 302 with well-known techniques.
  • a multi-interconnection line is formed on insulator 304.
  • an approximately 20 ⁇ A thick layer of titanium (Ti) 306 is formed over insulator 304 with well- known techniques, such as sputtering. Although a titanium layer is preferred, other refractory metal layers can be used.
  • an approximately 5200A thick aluminum alloy layer 308 comprising approximately 1% copper is formed on titanium layer 306 by well-known techniques, such as sputtering. Although an aluminum alloy, layer is preferred because of its low resistivity and its well-known processes, it is to be appreciated that other low resistance materials may act as the bulk conductor in interconnection line.
  • an approximately 20 ⁇ A thick titanium layer 310 is formed over aluminum alloy layer 308. Although titanium is preferred, other refractory metal layers may be used, if desired.
  • An anti-reflective coating 312, such as titanium nitride (TiN), may be formed over titanium layer 310, if desired.
  • titanium layer 306, aluminum alloy layer 308, titanium layer 310, and titanium nitride layer 312 are patterned with well-known photolithography and etch processes to form an interconnection line 305.
  • TiN anti-reflective coating 312 helps to provide manufacturable photolithography process.
  • Any well-known etching technique, such as reactive ion etching (RIE) with a chemistry comprising BCI3 and CI2 can be used to pattern interconnection line 305.
  • RIE reactive ion etching
  • an interlayer dielectric (ILD) 314 such as doped silicon dioxide, is formed over and around multilayer interconnection 305.
  • ILD 314 is preferably planarized at this time with well-known techniques, such as chemical-mechanical polishing or etch- back, to form a planar top surface. It is to be appreciated that ILD 314 should be thick enough after planarization to provide adequate electrical isolation of interconnection 305 from a subsequent level of metallization. An approximately 10,OO ⁇ A Si ⁇ 2 layer provides suitable isolation.
  • titanium layer 310 is formed directly on aluminum alloy layer 308.
  • a reaction occurs to form titanium aluminide (TiAl3).
  • titanium aluminide TiAl3
  • the original thickness of titanium layers 306 and 310 are only approximately 20 ⁇ A, a titanium aluminide layer greater than 80 ⁇ A can result because the reactions consume aluminum from aluminum alloy layer 306.
  • capping layer 309 is securely bonded to underlying aluminum alloy layer 308, providing added mechanical strength which prevents capping layer 309 and a subsequently formed anchored via connection from pealing away from aluminum alloy layer 308.
  • An approximately 300 - 1500A titanium aluminide layer has been found to provide sufficient strength to prevent via delamination.
  • a titanium aluminide compound is preferred for capping layer 309, other refractory metal-aluminum compounds can be used.
  • titanium layer 306 and 310 need not necessarily be reacted at this time. However, enough reaction of titanium layer 310 and aluminum alloy layer 308 must occur in order to provide a titanium aluminide layer thick enough to provide sufficient mechanical strength to prevent via delamination. Any unreacted Ti can be fully reacted during subsequent standard and well-known process, such as ILD formation, annealings, curings, cleanings, sputterings, and high temperature hydrogen passivation, used to complete device fabrication.
  • a via hole is formed through ILD 314, titanium nitride layer 312, and titanium aluminide layer 309.
  • photoresist layer 316 is formed over planarized ILD 314 and patterned with well-known photolithography techniques, to define locations where a via hole 316 is to be formed.
  • the exposed portion of ILD 314, titanium nitride 312, and titanium aluminide layer 309 are etched.
  • Via hole 316 must be etched until aluminum alloy layer 308 is reached.
  • a reactive ion etch (RIE) with a chemistry comprising CF4 and CHF3 can be used to form via hole 316.
  • RIE reactive ion etch
  • the via etch depth across the substrate it is important to precisely control the via etch depth across the substrate. It is important to insure that the via etch stops in aluminum alloy layer 308 for all vias across the substrate or wafer. This can be accomplished with several different methods.
  • One method used in the preferred embodiment of the present invention is to chemically- mechanically polish ILD 314 to provide a very planar top surface. In this way, even with oxide deposition and polish rate variations, all vias across a substrate at a given layer are at substantially the same depth.
  • a second technique which can be employed is to keep titanium nitride and titanium capping layers 312 and 310, respectively, as thin as possible prior to via hole etch.
  • Thin capping layers reduce the need for excessively long via etches to reach aluminum alloy layer 308.
  • processing temperature it is advisable to keep processing temperature as low as possible after metal formation and before via etch, in order to prevent the formation of a thicker titanium aluminide layer. In this way via etch will not need to be excessively long to reach aluminum alloy layer 308. If this technique is used, however, sufficient reaction must occur prior to anchor hole formation so that there is a sufficient capping layer to lock a subsequently formed via into place.
  • an anchor hole 320 is formed in interconnection 305.
  • an isotropic wet etch is used which is highly selective to conductor 308 with respect to capping layer 309 (i.e., it etches conductor 308 at a rate faster than capping layer 309).
  • conductor 308 is laterally etched away beneath capping layer 309, forming a concave hole 320 which undercuts capping layer 309 of interconnection 305.
  • An anchor hole 320 which undercuts capping layer 309 i.e., extends laterally beneath capping layer 309) by an amount (a) of between 500 - 150 ⁇ A is preferred in the present invention.
  • anchor hole 320 When conductor 308 is an aluminum-copper alloy layer and capping layer 309 is a titanium aluminide layer, the following preferred process can be used to form anchor hole 320.
  • substrate 302 and formed metallization is dipped into a commercially available solvent known as PRS-3000 from J.T. Baker at approximately 70°C.
  • PRS-3000 comprises approximately 40 - 60 wt.% of 1-methyl-2-pyrrolidinone, 30 - 50 wt.% sulfolane, and 5 - 15 wt.% menoisopropanolamine.
  • substrate 302 is dunked into two different batches of PRS-3000 for at least 7.5 minutes each in order to sufficiently clean substrate 302 of photoresist and etch polymers.
  • substrate 302 is given a quick dip into de-ionized (Dl) water at room temperature for approximately 7.0 seconds. Substrate 302 is then removed from the de-ionized water and allowed to sit for approximately one minute in an empty Quick Dump Rinse (QDR) bath. Only when both PRS-3000 and water are simultaneously present on the substrate surface does the reaction occur which etches aluminum alloy layer 308. It is to be appreciated that the PRS-3000/water combination etches titanium aluminide layer 309 significantly slower than aluminum- copper alloy layer 308. Thus, the integrity of the titanium aluminide capping layer remains strong. This insures that a subsequently formed via connection is locked into and undercuts interconnection 305, rather than simply resting on the top of interconnection 305.
  • QDR Quick Dump Rinse
  • a valuable quality of the described etchant is that it is self-limiting. That is, after about one minute, etching essentially stops due to limited reactants. This makes the present invention very repeatable and, therefore, manufacturable. Additionally, it is to be appreciated that titanium aluminide layer 307 acts as an etch stop for the anchor hole etch insuring that anchor hole 320 does not extend all the way through interconnection 305.
  • the empty QDR bath fills with de- ionized water and a standard and well-known water rinse or QDR cycle is performed to clean substrate 302.
  • a standard spin-rinse-dry cycle SRD
  • other standard and well-known wet and dry cleaning techniques such as ashing, can be used to sufficiently clean anchor hole 320 and the wafer surface.
  • the anchor hole etch of the present invention removes residue left from the via etch and provides a "fresh" aluminum interface. This helps to provide a strong mechanical bond between a subsequently formed via connection and interconnection 305 and helps to provide lower electrical resistance because of cleanliness.
  • anchor hole forming process is preferred, other techniques may be utilized. For example, dry etching techniques, such as reactive ion etching (RIE) and plasma etching can be used. Additionally, other wet etchants can be used, such as dilute solutions of buffered hydrofluoric acid or ammonia fluoride. The only requirement is that the etch technique used to form anchor hole 320 be selective to conductor 308 with respect to capping layer 309. Thus, it is quite evident that it is important to choose materials for capping layer 309 and conductor 308 which can be selectively etched.
  • RIE reactive ion etching
  • via hole 318 and anchor hole 320 are filled with a conductive material 322, by well-known techniques, to form a via connection or plug.
  • a well-known sputter clean is conducted prior to metal deposition.
  • thin adhesion/barrier layers such as Ti and TiN (not shown) are blanket deposited over ILD 314 and into via hole 318 and anchor hole 320, with well-known techniques, such as sputtering.
  • CVD chemical vapor deposition
  • a CVD tungsten layer can be formed by first forming a nucleation layer by CVD with a chemistry comprising WF ⁇ and SiH4 and then forming a tungsten layer by CVD with a chemistry comprising WF ⁇ and H2.
  • CVD techniques are preferred, because CVD forms very conformal layers.
  • conductive layer 322 forms from the side walls in, allowing for deposition of metal beneath capping layer 309. It is to be appreciated that conductive material 322 is deposited until via hole 318 and anchor hole 320 are filled.
  • tungsten layer 322 and any adhesion or barrier layers on the top surface of ILD 314 are etched back to form via connection 324.
  • tungsten layer 322 and any adhesion/barrier metals are etched back through the use of well-known chemical- mechanical polishing techniques. It is to be appreciated, however, that other well-known etch back techniques, such as reactive ion etching (RIE), can be utilized if desired.
  • RIE reactive ion etching
  • a second interconnection line 326 is formed over and in electrical contact with via connection 324.
  • Second interconnection 326 makes electrical contact with first interconnection 305 through via connection 324.
  • Second interconnection 305 is preferably formed with the same structure and methods as first interconnection 305. In this way, a subsequent level of metallization can be anchored into interconnection 326 with the novel via connection technique of the present invention.
  • the process of forming the preferred interconnection structure of the present invention is now complete.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/US1995/009529 1994-10-17 1995-07-14 A novel via hole profile and method of fabrication WO1996012295A1 (en)

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GB9706661A GB2308234B (en) 1994-10-17 1995-07-14 A novel via hole profile and method fabrication
JP8513200A JPH10507315A (ja) 1994-10-17 1995-07-14 新規なビアホール形状およびその製造方法
KR1019970702511A KR100274138B1 (ko) 1994-10-17 1995-07-14 신규한바이어홀프로파일및그제조방법
AU31521/95A AU3152195A (en) 1994-10-17 1995-07-14 A novel via hole profile and method of fabrication

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GB2308234A (en) 1997-06-18
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CN1168739A (zh) 1997-12-24
US5619071A (en) 1997-04-08
JPH10507315A (ja) 1998-07-14
CN1106688C (zh) 2003-04-23
US5874358A (en) 1999-02-23
KR970707573A (ko) 1997-12-01
US5470790A (en) 1995-11-28
KR100274138B1 (ko) 2000-12-15
AU3152195A (en) 1996-05-06
TW289152B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-10-21

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