GB2308234B - A novel via hole profile and method fabrication - Google Patents
A novel via hole profile and method fabricationInfo
- Publication number
- GB2308234B GB2308234B GB9706661A GB9706661A GB2308234B GB 2308234 B GB2308234 B GB 2308234B GB 9706661 A GB9706661 A GB 9706661A GB 9706661 A GB9706661 A GB 9706661A GB 2308234 B GB2308234 B GB 2308234B
- Authority
- GB
- United Kingdom
- Prior art keywords
- via hole
- hole profile
- method fabrication
- novel via
- novel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/324,763 US5470790A (en) | 1994-10-17 | 1994-10-17 | Via hole profile and method of fabrication |
PCT/US1995/009529 WO1996012295A1 (en) | 1994-10-17 | 1995-07-14 | A novel via hole profile and method of fabrication |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9706661D0 GB9706661D0 (en) | 1997-05-21 |
GB2308234A GB2308234A (en) | 1997-06-18 |
GB2308234B true GB2308234B (en) | 1999-04-14 |
Family
ID=23264999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9706661A Expired - Fee Related GB2308234B (en) | 1994-10-17 | 1995-07-14 | A novel via hole profile and method fabrication |
Country Status (8)
Country | Link |
---|---|
US (3) | US5470790A (en) |
JP (1) | JPH10507315A (en) |
KR (1) | KR100274138B1 (en) |
CN (1) | CN1106688C (en) |
AU (1) | AU3152195A (en) |
GB (1) | GB2308234B (en) |
TW (1) | TW289152B (en) |
WO (1) | WO1996012295A1 (en) |
Families Citing this family (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2921773B2 (en) * | 1991-04-05 | 1999-07-19 | 三菱電機株式会社 | Wiring connection structure of semiconductor device and method of manufacturing the same |
KR0138308B1 (en) | 1994-12-14 | 1998-06-01 | 김광호 | Method of fabricating interlayer connection in semiconductor device |
KR100193100B1 (en) * | 1995-02-02 | 1999-06-15 | 모리시다 요이치 | Semiconductor device and manufacturing method |
JP2953340B2 (en) * | 1995-03-29 | 1999-09-27 | ヤマハ株式会社 | Wiring formation method |
US5897374A (en) * | 1995-05-22 | 1999-04-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical via/contact with undercut dielectric |
US5726498A (en) * | 1995-05-26 | 1998-03-10 | International Business Machines Corporation | Wire shape conferring reduced crosstalk and formation methods |
JP2899540B2 (en) * | 1995-06-12 | 1999-06-02 | 日東電工株式会社 | Film carrier and semiconductor device using the same |
TW298674B (en) * | 1995-07-07 | 1997-02-21 | At & T Corp | |
TW318261B (en) * | 1995-09-21 | 1997-10-21 | Handotai Energy Kenkyusho Kk | |
EP0852809A4 (en) * | 1995-09-29 | 1999-09-15 | Intel Corp | Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions |
US5747879A (en) * | 1995-09-29 | 1998-05-05 | Intel Corporation | Interface between titanium and aluminum-alloy in metal stack for integrated circuit |
US5851928A (en) * | 1995-11-27 | 1998-12-22 | Motorola, Inc. | Method of etching a semiconductor substrate |
US5851923A (en) * | 1996-01-18 | 1998-12-22 | Micron Technology, Inc. | Integrated circuit and method for forming and integrated circuit |
US6040613A (en) * | 1996-01-19 | 2000-03-21 | Micron Technology, Inc. | Antireflective coating and wiring line stack |
US5661083A (en) * | 1996-01-30 | 1997-08-26 | Integrated Device Technology, Inc. | Method for via formation with reduced contact resistance |
US5700718A (en) * | 1996-02-05 | 1997-12-23 | Micron Technology, Inc. | Method for increased metal interconnect reliability in situ formation of titanium aluminide |
JP4179483B2 (en) | 1996-02-13 | 2008-11-12 | 株式会社半導体エネルギー研究所 | Method for manufacturing display device |
US6821821B2 (en) * | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
US5912510A (en) * | 1996-05-29 | 1999-06-15 | Motorola, Inc. | Bonding structure for an electronic device |
US6222272B1 (en) | 1996-08-06 | 2001-04-24 | Nitto Denko Corporation | Film carrier and semiconductor device using same |
US6046100A (en) * | 1996-12-12 | 2000-04-04 | Applied Materials, Inc. | Method of fabricating a fabricating plug and near-zero overlap interconnect line |
US6028363A (en) * | 1997-06-04 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Vertical via/contact |
US5877092A (en) * | 1997-06-18 | 1999-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for edge profile and design rules control |
US6141870A (en) | 1997-08-04 | 2000-11-07 | Peter K. Trzyna | Method for making electrical device |
US5969425A (en) * | 1997-09-05 | 1999-10-19 | Advanced Micro Devices, Inc. | Borderless vias with CVD barrier layer |
US6522013B1 (en) * | 1997-12-18 | 2003-02-18 | Advanced Micro Devices, Inc. | Punch-through via with conformal barrier liner |
US5925932A (en) * | 1997-12-18 | 1999-07-20 | Advanced Micro Devices, Inc. | Borderless vias |
TW359884B (en) * | 1998-01-07 | 1999-06-01 | Nanya Technology Co Ltd | Multi-level interconnects with I-plug and production process therefor |
GB2347267B (en) * | 1998-02-20 | 2001-05-02 | Lg Lcd Inc | A liquid crystal display |
KR100276442B1 (en) | 1998-02-20 | 2000-12-15 | 구본준 | Liquid crystal display device and its fabrication method |
US6576547B2 (en) | 1998-03-05 | 2003-06-10 | Micron Technology, Inc. | Residue-free contact openings and methods for fabricating same |
US6080664A (en) * | 1998-05-29 | 2000-06-27 | Vanguard International Semiconductor Corporation | Method for fabricating a high aspect ratio stacked contact hole |
US6433428B1 (en) | 1998-05-29 | 2002-08-13 | Kabushiki Kaisha Toshiba | Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same |
US6084296A (en) * | 1998-07-09 | 2000-07-04 | Satcon Technology Corporation | Low cost high power hermetic package with electrical feed-through bushings |
KR100265772B1 (en) * | 1998-07-22 | 2000-10-02 | 윤종용 | Wiring structure of semicondcutor device and manufacturing method thereof |
KR100267106B1 (en) * | 1998-09-03 | 2000-10-02 | 윤종용 | Method for fabricating multi-layer metal interconnection of semiconductor device |
KR100295054B1 (en) * | 1998-09-16 | 2001-08-07 | 윤종용 | Semiconductor device having multi-wiring and manufacturing method thereof |
JP3655113B2 (en) * | 1998-12-28 | 2005-06-02 | シャープ株式会社 | Manufacturing method of semiconductor memory device |
US6153901A (en) * | 1999-01-26 | 2000-11-28 | Lucent Technologies Inc. | Integrated circuit capacitor including anchored plug |
US6169010B1 (en) * | 1999-01-26 | 2001-01-02 | Lucent Technologies Inc. | Method for making integrated circuit capacitor including anchored plug |
DE19903195B4 (en) * | 1999-01-27 | 2005-05-19 | Infineon Technologies Ag | Method for improving the quality of metal interconnects on semiconductor structures |
US6087726A (en) * | 1999-03-01 | 2000-07-11 | Lsi Logic Corporation | Metal interconnect stack for integrated circuit structure |
US6265305B1 (en) * | 1999-10-01 | 2001-07-24 | United Microelectronics Corp. | Method of preventing corrosion of a titanium layer in a semiconductor wafer |
JP2001145241A (en) * | 1999-11-15 | 2001-05-25 | Sumitomo Wiring Syst Ltd | Wiring board assembly |
JP3502800B2 (en) | 1999-12-15 | 2004-03-02 | 新光電気工業株式会社 | Method for manufacturing semiconductor device |
US6313026B1 (en) * | 2000-04-10 | 2001-11-06 | Micron Technology, Inc. | Microelectronic contacts and methods for producing same |
JP3547364B2 (en) * | 2000-04-21 | 2004-07-28 | シャープ株式会社 | Method for manufacturing semiconductor device |
US6392524B1 (en) | 2000-06-09 | 2002-05-21 | Xerox Corporation | Photolithographically-patterned out-of-plane coil structures and method of making |
US6396677B1 (en) * | 2000-05-17 | 2002-05-28 | Xerox Corporation | Photolithographically-patterned variable capacitor structures and method of making |
US6856225B1 (en) * | 2000-05-17 | 2005-02-15 | Xerox Corporation | Photolithographically-patterned out-of-plane coil structures and method of making |
WO2002017693A1 (en) * | 2000-08-18 | 2002-02-28 | Mitsubishi Denki Kabushiki Kaisha | Installation substrate, method of mounting installation substrate, and bulb socket using installation substrate |
KR100365642B1 (en) * | 2000-10-30 | 2002-12-26 | 삼성전자 주식회사 | Method for fabricating a semiconductor device with contact window |
JP4752108B2 (en) * | 2000-12-08 | 2011-08-17 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
US6613664B2 (en) * | 2000-12-28 | 2003-09-02 | Infineon Technologies Ag | Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices |
US6441435B1 (en) * | 2001-01-31 | 2002-08-27 | Advanced Micro Devices, Inc. | SOI device with wrap-around contact to underside of body, and method of making |
US6595787B2 (en) * | 2001-02-09 | 2003-07-22 | Xerox Corporation | Low cost integrated out-of-plane micro-device structures and method of making |
KR100385227B1 (en) * | 2001-02-12 | 2003-05-27 | 삼성전자주식회사 | Semiconductor device having copper multy later circuit line and method of making the same |
US20030219459A1 (en) * | 2002-01-18 | 2003-11-27 | Cytos Biotechnology Ag | Prion protein carrier-conjugates |
US20030194872A1 (en) * | 2002-04-16 | 2003-10-16 | Applied Materials, Inc. | Copper interconnect with sidewall copper-copper contact between metal and via |
JP3974470B2 (en) * | 2002-07-22 | 2007-09-12 | 株式会社東芝 | Semiconductor device |
KR20040017037A (en) * | 2002-08-20 | 2004-02-26 | 삼성전자주식회사 | Semiconductor contact structure and method of forming the same |
DE10257681B4 (en) | 2002-12-10 | 2008-11-13 | Infineon Technologies Ag | A method of fabricating an integrated circuit device including a metal nitride layer and integrated circuit device |
US6806579B2 (en) * | 2003-02-11 | 2004-10-19 | Infineon Technologies Ag | Robust via structure and method |
US6977437B2 (en) * | 2003-03-11 | 2005-12-20 | Texas Instruments Incorporated | Method for forming a void free via |
US20040192059A1 (en) * | 2003-03-28 | 2004-09-30 | Mosel Vitelic, Inc. | Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack |
US7045455B2 (en) * | 2003-10-23 | 2006-05-16 | Chartered Semiconductor Manufacturing Ltd. | Via electromigration improvement by changing the via bottom geometric profile |
KR20050056419A (en) * | 2003-12-10 | 2005-06-16 | 동부아남반도체 주식회사 | Method for forming a metal line in semiconductor device |
US7956672B2 (en) * | 2004-03-30 | 2011-06-07 | Ricoh Company, Ltd. | Reference voltage generating circuit |
US7217651B2 (en) * | 2004-07-28 | 2007-05-15 | Intel Corporation | Interconnects with interlocks |
KR100668833B1 (en) * | 2004-12-17 | 2007-01-16 | 주식회사 하이닉스반도체 | Emthod for fabricating capacitor in semiconductor device |
US7332428B2 (en) * | 2005-02-28 | 2008-02-19 | Infineon Technologies Ag | Metal interconnect structure and method |
US20060244151A1 (en) * | 2005-05-02 | 2006-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Oblique recess for interconnecting conductors in a semiconductor device |
DE102005024914A1 (en) * | 2005-05-31 | 2006-12-07 | Advanced Micro Devices, Inc., Sunnyvale | Method for forming electrically conductive lines in an integrated circuit |
WO2007020805A1 (en) * | 2005-08-12 | 2007-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US7511349B2 (en) * | 2005-08-19 | 2009-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact or via hole structure with enlarged bottom critical dimension |
US7517736B2 (en) * | 2006-02-15 | 2009-04-14 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
US7528066B2 (en) * | 2006-03-01 | 2009-05-05 | International Business Machines Corporation | Structure and method for metal integration |
JP4788474B2 (en) * | 2006-05-19 | 2011-10-05 | 三菱電機株式会社 | Semiconductor device |
DE102006035645B4 (en) * | 2006-07-31 | 2012-03-08 | Advanced Micro Devices, Inc. | Method for forming an electrically conductive line in an integrated circuit |
KR100790452B1 (en) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | Method for forming multi layer metal wiring of semiconductor device using damascene process |
DE102007004860B4 (en) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | A method of making a copper-based metallization layer having a conductive overcoat by an improved integration scheme |
US7790599B2 (en) * | 2007-04-13 | 2010-09-07 | International Business Machines Corporation | Metal cap for interconnect structures |
DE102007020263B4 (en) * | 2007-04-30 | 2013-12-12 | Infineon Technologies Ag | Verkrallungsstruktur |
US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
US7709966B2 (en) * | 2007-09-25 | 2010-05-04 | Sixis, Inc. | Large substrate structural vias |
CN102576764A (en) * | 2009-10-15 | 2012-07-11 | Lg伊诺特有限公司 | Solar photovoltaic device and a production method for the same |
US9793199B2 (en) * | 2009-12-18 | 2017-10-17 | Ati Technologies Ulc | Circuit board with via trace connection and method of making the same |
US8314026B2 (en) | 2011-02-17 | 2012-11-20 | Freescale Semiconductor, Inc. | Anchored conductive via and method for forming |
JP5360134B2 (en) * | 2011-06-01 | 2013-12-04 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP2013187339A (en) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
US8772949B2 (en) | 2012-11-07 | 2014-07-08 | International Business Machines Corporation | Enhanced capture pads for through semiconductor vias |
US9230934B2 (en) | 2013-03-15 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface treatment in electroless process for adhesion enhancement |
US9832887B2 (en) * | 2013-08-07 | 2017-11-28 | Invensas Corporation | Micro mechanical anchor for 3D architecture |
US9299656B2 (en) | 2014-06-02 | 2016-03-29 | Infineon Technologies Ag | Vias and methods of formation thereof |
KR102307633B1 (en) | 2014-12-10 | 2021-10-06 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
WO2017205781A1 (en) * | 2016-05-27 | 2017-11-30 | Board Of Trustees Of Michigan State University | Hybrid diamond-polymer thin film sensors and fabrication method |
US10163692B2 (en) * | 2017-03-08 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of interconnection structure of semiconductor device structure |
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US11183455B2 (en) * | 2020-04-15 | 2021-11-23 | International Business Machines Corporation | Interconnects with enlarged contact area |
US11551967B2 (en) * | 2020-05-19 | 2023-01-10 | Taiwan Semiconductor Manufacturing Company Limited | Via structure and methods for forming the same |
US20230187350A1 (en) * | 2021-12-13 | 2023-06-15 | International Business Machines Corporation | Dual-metal ultra thick metal (utm) structure |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4507852A (en) * | 1983-09-12 | 1985-04-02 | Rockwell International Corporation | Method for making a reliable ohmic contact between two layers of integrated circuit metallizations |
US4714686A (en) * | 1985-07-31 | 1987-12-22 | Advanced Micro Devices, Inc. | Method of forming contact plugs for planarized integrated circuits |
JPS63133647A (en) * | 1986-11-26 | 1988-06-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
US4879257A (en) * | 1987-11-18 | 1989-11-07 | Lsi Logic Corporation | Planarization process |
JPH02122546A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Manufacture of semiconductor device |
US5106461A (en) * | 1989-04-04 | 1992-04-21 | Massachusetts Institute Of Technology | High-density, multi-level interconnects, flex circuits, and tape for tab |
US5312775A (en) * | 1991-01-30 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device having multilayer interconnection structure |
US5408130A (en) * | 1992-08-31 | 1995-04-18 | Motorola, Inc. | Interconnection structure for conductive layers |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59228737A (en) * | 1983-06-10 | 1984-12-22 | Seiko Epson Corp | Semiconductor device |
JPH0529470A (en) * | 1991-07-24 | 1993-02-05 | Sony Corp | Forming method of wiring |
-
1994
- 1994-10-17 US US08/324,763 patent/US5470790A/en not_active Expired - Lifetime
-
1995
- 1995-05-06 TW TW084104522A patent/TW289152B/zh not_active IP Right Cessation
- 1995-07-14 AU AU31521/95A patent/AU3152195A/en not_active Abandoned
- 1995-07-14 WO PCT/US1995/009529 patent/WO1996012295A1/en active IP Right Grant
- 1995-07-14 KR KR1019970702511A patent/KR100274138B1/en not_active IP Right Cessation
- 1995-07-14 JP JP8513200A patent/JPH10507315A/en active Pending
- 1995-07-14 CN CN95196649A patent/CN1106688C/en not_active Expired - Fee Related
- 1995-07-14 GB GB9706661A patent/GB2308234B/en not_active Expired - Fee Related
- 1995-08-15 US US08/515,318 patent/US5619071A/en not_active Expired - Lifetime
-
1997
- 1997-02-25 US US08/805,961 patent/US5874358A/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4507852A (en) * | 1983-09-12 | 1985-04-02 | Rockwell International Corporation | Method for making a reliable ohmic contact between two layers of integrated circuit metallizations |
US4714686A (en) * | 1985-07-31 | 1987-12-22 | Advanced Micro Devices, Inc. | Method of forming contact plugs for planarized integrated circuits |
JPS63133647A (en) * | 1986-11-26 | 1988-06-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
US4879257A (en) * | 1987-11-18 | 1989-11-07 | Lsi Logic Corporation | Planarization process |
JPH02122546A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Manufacture of semiconductor device |
US5106461A (en) * | 1989-04-04 | 1992-04-21 | Massachusetts Institute Of Technology | High-density, multi-level interconnects, flex circuits, and tape for tab |
US5312775A (en) * | 1991-01-30 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device having multilayer interconnection structure |
US5408130A (en) * | 1992-08-31 | 1995-04-18 | Motorola, Inc. | Interconnection structure for conductive layers |
Non-Patent Citations (4)
Title |
---|
Gardner et al, IEDM 84, pp 114-117, 1984, "Layered and homogeneous films for interconnects" * |
Gardner et al, IEEE Transactions on Electron Devices, Vol ED-34, No 3, pp 632-643, Mar 87. * |
Hasegawa et al., Japan Society of Applied Physics, 52nd FallMeeting, extd abstracts, pg 718, Oct1991 * |
IBM Tech. Disc. Bull., Vol38, No6, June 95, "Method of anchoring contact or via plugs". * |
Also Published As
Publication number | Publication date |
---|---|
US5874358A (en) | 1999-02-23 |
TW289152B (en) | 1996-10-21 |
KR970707573A (en) | 1997-12-01 |
GB2308234A (en) | 1997-06-18 |
AU3152195A (en) | 1996-05-06 |
US5619071A (en) | 1997-04-08 |
KR100274138B1 (en) | 2000-12-15 |
US5470790A (en) | 1995-11-28 |
CN1106688C (en) | 2003-04-23 |
WO1996012295A1 (en) | 1996-04-25 |
JPH10507315A (en) | 1998-07-14 |
CN1168739A (en) | 1997-12-24 |
GB9706661D0 (en) | 1997-05-21 |
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