USD822629S1 - Semiconductor package - Google Patents

Description

FIG. 1 is a top perspective view of a semiconductor package showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a front view thereof;

FIG. 4 is a rear view thereof;

FIG. 5 is a right side view thereof;

FIG. 6 is a top view thereof;

FIG. 7 is a bottom view thereof;

FIG. 8 is an enlarged portion view labeled 8 taken in FIG. 1;

FIG. 9 is an enlarged portion view labeled 9 taken in FIG. 2; and,

FIG. 10 is another perspective view thereof shown in a used condition in which the semiconductor package is sealed and mounted onto a substrate which is shown in broken lines.

The broken lines in the drawings illustrate portions of the semiconductor package which form no part of the claimed design. The dot-dashed lines in the drawings are for the purpose of showing boundaries of the design and form no part of the claimed design.

Claims (1)

CLAIM
1. The ornamental design for a semiconductor package, as shown and described.

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