US7554534B2 - Noise elimination circuit of matrix display device and matrix display device using the same - Google Patents

Noise elimination circuit of matrix display device and matrix display device using the same Download PDF

Info

Publication number
US7554534B2
US7554534B2 US11/340,632 US34063206A US7554534B2 US 7554534 B2 US7554534 B2 US 7554534B2 US 34063206 A US34063206 A US 34063206A US 7554534 B2 US7554534 B2 US 7554534B2
Authority
US
United States
Prior art keywords
signal
counter
count
circuit unit
rising edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/340,632
Other languages
English (en)
Other versions
US20070018932A1 (en
Inventor
Jiro Takaki
Kazuhiro Ishiguchi
Akihiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Trivale Technologies LLC
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIGUCHI, KAZUHIRO, MINAMI, AKIHIRO, TAKAKI, JIRO
Publication of US20070018932A1 publication Critical patent/US20070018932A1/en
Application granted granted Critical
Publication of US7554534B2 publication Critical patent/US7554534B2/en
Assigned to TRIVALE TECHNOLOGIES, LLC reassignment TRIVALE TECHNOLOGIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI ELECTRIC CORPORATION
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation

Definitions

  • the present invention relates to a noise elimination circuit of a matrix display device and a matrix display device using the noise elimination circuit, and in particular, to a noise elimination circuit included in a timing controller of a liquid crystal display device.
  • a high voltage is applied to a casing body of a matrix display device, such as a liquid crystal display device
  • a static noise test for example, an abnormal display of the moment has been viewed.
  • the abnormal display mainly occurs because a noise is introduced into an input terminal of the liquid crystal display device and the noise is superposed on a signal within a digital circuit included in a timing controller of the liquid crystal display device, and as a result, the timing controller malfunctions to output various control signals at timings different from those in a normal state.
  • Output signals of the timing controller mounted in the liquid crystal display device include a horizontal direction start pulse, a vertical direction start pulse, and the like, which are affected by the superposition of the static noise introduced into the input terminal.
  • a horizontal direction start pulse When the timing of the horizontal direction start pulse deviates, a line noise is generated, and when the horizontal direction start pulse is not output, the abnormal display, such as omission of a line, occurs.
  • the abnormal display when the timing of the vertical direction start pulse deviates, the display rocking in the vertical direction occurs, and when the vertical direction start pulse is not output, the abnormal display, such as omission of a frame, occurs.
  • the omission of a frame is not a big problem in a still image, while the omission of a frame causes a screen jump so as to make unnatural movements in a moving picture.
  • LVDS low voltage differential signaling
  • a noise elimination circuit for preventing a digital circuit from malfunctioning when a noise is introduced thereinto has been proposed in which noise components of input signals are eliminated by preparing a plurality of input stages in consideration of a case where noises are included in the input signals and then comparing the input signals so as to determine the reliability of the signals (refer to JP-A-11-282401).
  • a noise detection circuit for detecting noises, such as continuously generated noises or a noise having a wide pulse width (refer to JP-A-2000-209076).
  • the noise elimination circuit disclosed in JP-A-11-282401 the sufficient performance cannot be obtained because, for example, noises cannot be filtered when the noises are introduced into all stages.
  • the noise elimination circuits disclosed in JP-A-11-214964 and JP-A-11-251884 in the case of a noise having a predefined pulse width or continuously generated noises, a noise of the input signal and a noise of the delayed input signal are superposed, and accordingly, the noise cannot be completely eliminated.
  • the noise elimination circuit disclosed in JP-A-2000-341098 since there is a limitation on the pulse width of a noise which can be eliminated, there is a possibility that an original signal will be removed when a noise having a wide pulse width is eliminated.
  • a level monitoring circuit for generating a level monitor signal for a predetermined period of time by detecting rising (or falling) edges of the input signal is provided so as to detect a noise during an operation period of the level monitoring circuit.
  • a noise (Low) signal during an active (High) period can be detected, a noise (High) signal during an inactive (Low) period cannot be detected, and also, an additional noise elimination circuit is needed to obtain an original input signal because a noise elimination circuit is not provided.
  • an edge of the input signal is detected by using an edge detector, a timer that counts a predetermined period of time subsequent to the edge and a mask unit that masks the input signal while the timer counts are provided, and the input signal is masked, thereby eliminating noises.
  • an edge detector a timer that counts a predetermined period of time subsequent to the edge and a mask unit that masks the input signal while the timer counts are provided, and the input signal is masked, thereby eliminating noises.
  • a noise (Low) signal during an active (High) period can be detected, a noise (High) signal during an inactive (Low) period cannot be detected.
  • the active (High) period refers to a case in which the signal is a signal determining whether other input signals (for example, a data signal) are effective or not and the input signal is effective.
  • the inactive (Low) period refers to a case in which the input signal is not effective.
  • a noise elimination circuit for eliminating a noise of a display control signal, of a matrix display device, includes: a rising edge detection circuit unit that detects a rising edge of a signal for eliminating a noise; a counter that performs a count operation during a predefined period of time; an initialization circuit unit that generates an initialization signal of the counter; a count enable circuit unit that generates a count allowance signal of the counter; and an initial state detection circuit unit that detects whether or not the counter is in an initial state.
  • the counter starts a count operation from an initial value in response to a rising edge detection of the rising edge detection circuit unit and the counter is initialized again after the count operation during the predefined period of time is completed, and thus an initial state detection signal of the initial state detection circuit unit 24 becomes a signal from which a noise is eliminated.
  • a control signal input to a liquid crystal driving circuit can be maintained in a normal operation state so as to prevent abnormal display from occurring by using the noise elimination circuit in a timing controller mounted in the flat panel display device.
  • FIG. 1 is a view illustrating the system configuration of a liquid crystal display device according to anyone of first to fourth embodiments of the invention
  • FIG. 2 is a view illustrating display control signals and timings thereof, which are input to the liquid crystal display device according to any one of the first and third embodiments;
  • FIG. 3 is a timing diagram of a timing controller according to any one of the first and third embodiments
  • FIG. 4 is a view illustrating the configuration of a noise elimination circuit according to the first embodiment of the invention.
  • FIG. 5 is a timing diagram of the noise elimination circuit according to the first embodiment of the invention.
  • FIG. 6 is a timing diagram of the noise elimination circuit according to the first embodiment of the invention.
  • FIG. 7 is a timing diagram of the noise elimination circuit adopting a downcounter according to the first embodiment of the invention.
  • FIG. 8 is a view illustrating the configuration of a noise elimination circuit according to the second and third embodiments of the invention.
  • FIG. 9 is a view illustrating the configuration of a resolution judgment circuit according to the fourth embodiment of the invention.
  • FIG. 10 is a timing diagram of the resolution judgment circuit according to the fourth embodiment of the invention.
  • FIG. 1 is a view illustrating the system configuration of a liquid crystal display device 1 including a timing controller 5 having a noise elimination circuit 6 according to a first embodiment.
  • a liquid crystal panel 10 has an XGA (Extra Graphic Array) resolution
  • pixels 12 and TFTs 11 for driving the pixels 12 are disposed in a matrix of 768 in a row by 1024 ⁇ 3 (corresponding to R, G, and B) which are not shown
  • a scanning line driving circuit 2 connected to a plurality of scanning lines and a signal line driving circuit 3 connected to a plurality of signal lines are disposed around a matrix display unit of the liquid crystal panel 10 .
  • a display control signal which is inputted to the timing controller 5 of the liquid crystal display device 1 from a display controller, and the timing thereof adopts a typical timing having a high compatibility as shown in FIG. 2 and will be described below in detail.
  • a data enable (hereinafter, referred to as ‘DENA’) signal and a display data (hereinafter, referred to as ‘DATA’) signal are read out at a timing synchronized with a falling (or rising) edge of a dot clock (hereinafter, referred to as ‘DCLK’) in a digital circuit of the timing controller 5 , and the DATA signal displayed on the liquid crystal panel 10 is determined to be effective for the digital circuit during an active period (High period) of the DENA signal. Further, the upper half of FIG. 2 shows the timing relationship between the DCLK and the DENA and DATA signals for two frames.
  • DENA data enable
  • DATA display data
  • a period while the DENA signal is in an active state during a relatively long period indicates a DATA signal effective period of a first line
  • 1024 DCLK period during which next DENA signal becomes active with a horizontal blanking period indicates a DATA effective period of a second line
  • a final DENA signal activation period (1024 DCLK period) immediately before a vertical blanking period between next frame and the final DENA signal activation period is a DATA signal effective period of a final 768th line.
  • the DENA signal rises and thus 1025 DCLK period elapses, the DENA signal becomes inactive (Low), resulting in a horizontal blanking period. Then, by repeating the above-described operation 768 times, data corresponding to one frame, that is, one screen is input to the timing controller 5 .
  • a timing control circuit 4 of the timing controller 5 shown in FIG. 1 generates a scanning line driving control signal 13 , such as a horizontal direction start pulse and a vertical direction start pulse, from the inputted DCLK and the DENA and DATA signals, and then outputs the scanning line driving control signal 13 to the scanning line driving circuit 2 .
  • the scanning line driving control signal 13 generates a signal line driving control signal 14 , such as a horizontal direction start pulse, a latch pulse, or display data, and then outputs the signal line driving control signal 14 to the signal line driving circuit 3 .
  • the control signals 13 and 14 are generated by using the timing control circuit 4 of the timing controller 5 at a predetermined timing on the basis of the timing type of an input signal of a gate driver IC used in the scanning line driving circuit 2 or a source driver IC used in the signal line driving circuit 3 .
  • the timing controller 5 includes the timing control circuit 4 , the noise elimination circuit 6 , and the delay circuit 7 .
  • the noise elimination circuit 6 is input with a DENA signal 8 supplied from the display controller and outputs a DENA 2 signal 16 after noise elimination.
  • the delay circuit 7 is input with a DATA signal 9 and outputs a delay DATA signal 15 delayed for a predetermined DCLK period.
  • the timing control circuit 4 of the timing controller 5 is input with the DCLK or the DENA 2 signal 16 after noise elimination and the delay DATA signal 15 , and the control signals 13 and 14 are generated on the basis of these signals to be output to the scanning line driving circuit 2 and the signal line driving circuit 3 . It is determined whether the delay DATA signal 15 inputted in synchronization with DCLK is effective or not by the DENA 2 signal 16 synchronized with the DCLK.
  • a vertical direction CLK and a vertical direction start pulse which are scanning line driving control signals 13 , are output from the timing controller 5 to the scanning line driving circuit 2
  • an output DATA, a horizontal direction start pulse, and a latch pulse which are signal line control signals 14 , are output from the timing controller 5 to the signal line driving circuit 3 .
  • the timing of a main display control signal of the timing controller 5 including the noise elimination circuit 6 is illustrated.
  • the horizontal direction start pulse included in the signal line control signal 14 is output at a timing before 1 DCLK period of first data after output DATA, which is output to a source driver IC, included in the signal 14 is horizontally blanked, and the vertical direction start pulse included in the scanning line control signal 13 is output at a first horizontal scanning timing after the vertical blanking.
  • the timing of the DENA signal is important in order to obtain the accurate positions of the first DATA signal timing after the horizontal blanking and the horizontal scanning timing after the vertical blanking, and accordingly, the noise elimination circuit 6 is required for wiring lines of the DENA signal.
  • the noise elimination circuit 6 since the DENA signal is delayed for a predetermined period of time as will be described later, it is necessary to delay the DATA signal for the same period of time as above. That is, by synchronizing the timing of the DENA signal with the timing of the DATA signal, it is possible to form the timing controller 5 without changing the subsequent timing control circuit 4 .
  • FIG. 4 illustrates the construction of the noise elimination circuit 6 according to the first embodiment.
  • the noise elimination circuit 6 includes: a delay circuit block 31 composed of D flip-flop circuits (hereinafter, referred to as ‘D-FF’) operating in synchronization with the same DCLK signal; a DENA rising edge detection unit 21 composed of a seven-input AND circuit unit 22 to which the input signal DENA and signals sequentially delayed to be input to the D-FF circuits for 1 DCLK; a counter 27 to which the DCLK is input so as to count the number of input pulses of the DCLK; a count enable circuit unit 26 to which a rising edge detection output signal PEG of the AND circuit unit 22 is input and which outputs a count allowance signal ENV to the counter 27 , the count allowance signal ENV controlling an operation or a stop of a counter function of the counter 27 ; an initialization circuit unit 25 to which the rising edge detection output signal PEG of the rising edge detection unit 21 is input and which generates an initialization signal INT of the counter 27 to be output to the
  • An output signal DENA 2 of the inverting buffer 28 becomes a signal 16 after the noise elimination.
  • the counter 27 adopts an up-count method. Therefore, since the output CNT becomes zero when the counter 27 is initialized, the initial state detection unit 24 includes a zero value detection circuit detecting whether the output CNT is zero. On the other hand, the horizontal pixel number detection unit 23 includes a specified value detection circuit determining whether the output CNT of the counter 27 has reached the specified value.
  • the DENA 2 is input to the count enable circuit unit 26 .
  • the specified value set in the horizontal pixel number detection unit 23 is 1024 because the resolution of the liquid crystal panel 10 is XGA.
  • the delay circuit block 31 and the AND circuit unit 22 to which six delayed output signals of the delay circuit block 31 and the DENA signal 8 are input detect whether the DENA signal 8 maintains an active (High) state during consecutive seven DCLK periods, and output the rising edge detection output PEG as High when the DENA signal 8 is continuously in the active state. That is, the signal PEG detects a rising edge of the DENA signal 8 , and the delay time until the rising edge is detected corresponds to six DCLK periods.
  • the delay time is dependent on the number of D-FFs of the delay circuit block 31 , and a case in which six D-FFs are provided is exemplified in the first embodiment.
  • the count allowance signal ENV becomes High and then the counter 27 starts a count-up operation of the DCLK.
  • a count stop signal EOC High pulse
  • the counter 27 counts a specified period of time, that is, a period from 0 to the specified value 1024 DCLK, which is set in the horizontal pixel number detection unit 23 .
  • the input DENA signal 8 is inactive (Low) because 1024 DCLK periods has already elapsed, and the signal PEG having passed through the AND circuit unit 22 becomes Low.
  • an output signal of an AND circuit 30 of the initialization circuit unit 25 that is, the initialization signal INT becomes High
  • the counter 27 is initialized after next 1 DCLK is input thereto, and accordingly, the count output CNT becomes an initialization value 0.
  • the initial state detection unit 24 detects the initial state and the output signal ITS becomes High.
  • the data enable output DENA 2 signal 16 which is an inversion signal of the signal ITS, becomes High except that the counter value CNT is zero.
  • the delay circuit block 31 and the seven-input AND circuit unit 22 erroneously detect the noise (High) signal as an input signal, and as a result, the counter 27 starts a count-up operation.
  • the counter 27 performs the count-up operation up to the specified value 1024.
  • an AND circuit 29 of the count enable circuit unit 26 generating the count allowance signal ENV operates to have the count allowance signal ENV become Low and to keep maintaining the counter value CNT until the DENA signal 8 becomes inactive (Low).
  • the initialization circuit unit 25 generating the initialization signal INT does not cause the counter 27 to be initialized because the rising edge detection output PEG is High.
  • an AND circuit 29 of the count enable circuit unit 26 is input with an inversion signal of the count stop signal EOC output from the horizontal pixel number detection unit 23 and OR output between the rising edge detection output signal PEG of the DENA rising edge detection unit 21 and the output DENA 2 signal of the inverting circuit 28 , and then an AND operation with respect to the inversion signal and the OR output is performed, thereby generating the count allowance signal ENV. Accordingly, as shown in FIG.
  • the counter 27 can be initialized at an inactive timing of next normal DENA signal 8 by holding the specified value 1024, and thus it is possible to prevent continuous malfunctions from occurring.
  • the specified value exemplified in the first embodiment is not necessarily 1024, but the value may be set according to the design condition in consideration of the resolution of a liquid crystal panel.
  • the specified value of the horizontal pixel number detection unit 23 is determined by the specifications of an expected value of the pulse width of an input DENA signal, which is specified in the resolution specifications of a liquid crystal panel. That is, the specified value corresponds to the pulse width of the DENA signal of an input signal in a liquid crystal display device.
  • the specified value is 1024
  • the specified value is SVGA (Super VGA)
  • the specified value is 800
  • the specified value is 640.
  • the specified value may be 512 for XGA and 400 for SVGA.
  • the configuration of the noise elimination circuit 6 has been described in which the counter 27 adopts an upcounter that starts a counting operation from an initial value 0 and then increments a count value.
  • the counter 27 adopts the upcounter, but it is possible to adopt a downcounter that presets the specified value on the counter 32 at the time of initialization so as to downcount DCLK input pulses in the same manner as a noise elimination circuit 40 in which a downcounter shown in FIG. 7 is adopted.
  • a horizontal pixel number detection unit 43 has a zero value detection circuit
  • an initial state detection unit 34 has a specified value detection circuit.
  • an output CNT of the counter 32 becomes zero from the specified value, which is an initial value, as a downcount operation progresses, then a count stop signal EOC output from the zero value detection circuit becomes High, then the count stop signal EOC is input to an initialization circuit unit 25 so as to make the initialization signal INT High, and then the initial value 1024 is preset in the counter 32 .
  • Construction and operations of circuit units other than described above are the same as those in FIG. 4 , and it is possible to obtain the same noise elimination function.
  • the number of D-FFs has been six stages in the delay circuit block 31 of the noise elimination circuit 6 , it is not limited thereto but may be set to another number because the filter coefficient is only determined by the stage number of D-FFs having the noise elimination function.
  • the noise elimination circuit 6 sensitively responds to a noise (High) signal generated during an inactive period (Low period) of an input signal, and as a result, there is a possibility that a rising point will be ahead of an original input signal position.
  • the noise elimination circuit 6 does not respond to the noise (High) signal generated during an inactive period (Low period) of an input signal and thus desired operations can be expected, but a possibility that the rising point will be behind the original input signal position is increased because the noise elimination circuit 6 becomes sensitive to a noise generated for a rising edge of the original input signal. Since the noise pulse width when the LVDS receiver malfunctions due to discharge of a static noise corresponds to several to tens of several DCLK periods, it is preferable that the number of D-FFs be set in the range of 2 to 30.
  • the specified value detection circuit adopted in the first embodiment is configured to be able to correspond to various resolutions of a liquid crystal panel by providing a control circuit 34 provided outside a noise elimination circuit 41 , the control circuit 34 being able to supplying a specified output LOD.
  • components other than the noise elimination circuit 41 such as a system configuration of a liquid crystal display device in the second embodiment, are the same as those adopted in the first embodiment, and thus the same components are denoted by the same reference numerals and detailed explanation thereof will be omitted.
  • a horizontal pixel number detection unit 43 has a function detecting whether a signal CNT matches a specified value and is configured such that the specified value output LOD can be set through an external control. Due to the control circuit 34 configured above, the specified value of the noise elimination circuit 41 can be changed corresponding to various resolution specifications of liquid crystal panels, and accordingly, it is possible to correspond to liquid crystal display devices having various resolutions by using one kind of timing controller adopting the noise elimination circuit 41 .
  • the specified value is set to the noise elimination circuit 41 included in a timing controller by using the external control circuit 34
  • the external control circuit 34 there is a method in which one or more set terminals are prepared in the control circuit 34 (not shown), and one of a plurality of set values provided beforehand in a logic circuit within the timing controller or the noise elimination circuit 41 is selected on the basis of High/Low of a corresponding terminal so as to make the one set value the specified value of the horizontal pixel number detection unit 43 .
  • a ROM (not shown) recorded with specified data may be provided within the timing controller or outside the timing controller, and the specified value output LOD read out from the ROM through the control circuit 34 may be set in the horizontal pixel number detection unit 43 of the noise elimination circuit 41 .
  • the noise elimination circuit 41 it is possible to change the specified value without changing the logic circuit of the timing controller.
  • control circuit 34 is provided within the timing controller 6 , the position is not limited thereto, but the control circuit 34 may be provided in any other places.
  • a detection output EOC of the horizontal pixel number detection unit 43 included in the noise elimination circuit 41 adopted in the second embodiment is input to the control circuit 34 as shown in FIG. 8 , and the control circuit 34 determines step by step whether a predefined resolution matches a resolution of a liquid crystal panel which is to be displayed on the basis of the length of a signal DENA input for displaying on the liquid crystal panel so as to set the specified value.
  • components other than the noise elimination circuit 41 such as a system configuration of a liquid crystal display device in the third embodiment, are the same as those adopted in the first and second embodiments, and thus the same components are denoted by the same reference numerals and detailed explanation thereof will be omitted.
  • the control circuit 34 assumes a little small value (that is, the specified value corresponding to, for example, VGA is 640) and sets the value in the horizontal pixel number detection unit 43 as the specified value LOD. Then, a DENA rising edge detection unit 21 makes a rising edge detection output PEG High, which allows a counter 27 to count, and thus an output CNT increases from zero.
  • a High pulse is output as the rising edge detection output EOC of the horizontal pixel number detection unit 43 at a time when the CNT output becomes 640. Then, the control circuit 34 reads out the High pulse and is input with the High/Low PEG signal. Since the High pulse of the output EOC means that the specified value LOD and the CNT output value of the counter 27 are equal to each other, that is, 640, the active period length of the DENA is more than 640 DCLK periods.
  • the PEG signal output to the control circuit 34 is Low, since it means that the input DENA signal 8 is already Low, the horizontal resolution output from the display controller is 640, and thus the specified value set operation of the control circuit 34 is completed.
  • the control circuit 34 Since a case, in which the PEG signal when the High pulse appears on the output EOC is High, means that the horizontal resolution exceeds 640, the control circuit 34 outputs 800 (corresponding to SVGA) as the specified value LOD, which becomes a set value of the horizontal pixel number detection unit 43 . Subsequently, the DENA signal becomes active, the PEG signal allows the count operation of the upcounter 27 , the High pulse is output as the detection output EOC of the horizontal pixel number detection unit 43 at the time when the CNT output becomes 800, and the control circuit 34 reads out he High pulse and is input with the High/Low PEG signal.
  • the PEG signal input to the control circuit 34 is Low, means that the input DENA signal 8 is already is Low, the horizontal resolution output from the display controller is 800, and thus the specified value set operation of the control circuit 34 is completed.
  • the control circuit 34 outputs 1024 (corresponding to XGA) as the specified value LOD, which becomes a set value of the horizontal pixel number detection unit 43 .
  • the set value has been selected by incrementing the predefined resolution step by step so as to reduce a period of time until the selection of the proper set value is completed.
  • a method may be adopted in which the set value is incremented from a predetermined minimum value one by one so as to read out the High/Low of the PEG signal, thereby determining whether or not the set value is proper.
  • the rising time of the rising edge detection output generated from the input DENA signal is delayed by six DCLK periods, and correspondingly, the count start of a counter is delayed. Therefore, a final set value LOD can be set by adding a value corresponding to the six DCLK periods to the set value which first makes the PEG signal Low as the set value is incremented.
  • FIG. 9 illustrates the configuration of a resolution judgment circuit 50 judging the resolution of a liquid crystal panel by using the DENA 2 signal from which the DENA signal and the noise are removed.
  • a first counter 101 is input with a falling edge detection output EDG 1 of an edge detection circuit unit 100 , DENA, and DCLK, the edge detection circuit unit 100 detecting a falling edge of a DENA signal.
  • the counter 101 starts a count operation on the DCLK when the DENA becomes active (High), and stops the count operation when a falling edge EDG 1 is input thereto and then outputs a first counter value CNT 1 to a counter value holding circuit unit 102 .
  • the first counter value CNT 1 is reset to be zero when the DENA input to the counter 101 becomes inactive (Low), which makes the first counter value CNT 1 zero.
  • the counter value holding circuit unit 102 holds the CNT 1 at that time and outputs a count holding value MTN held therein to a DENA pulse width determination circuit 104 .
  • An edge detection circuit 103 is composed of the same circuits as the edge detection circuit unit 100 and detects a falling edge of the DENA 2 so as to output a corresponding edge EDG 2 to the DENA pulse width determination circuit 104 .
  • the DENA pulse width determination circuit 104 is input with the EDG 2 signal and the MTN signal, and outputs a PDT signal to a second counter, that is, an updown counter 105 in synchronization with a rising edge of the EDG 2 signal, the PDT signal indicating whether the MTN value at the time when the EDG 2 pulse is input is larger or smaller than a predefined threshold value.
  • the updown counter 105 is a 4-bit counter to which the PDT signal and the EDG 2 signal are input and the count value is incremented whenever the rising edge of the EDG 2 signal is input thereto. The updown counter 105 increments the count value when the PDT signal is High and decrements the count value when the PDT signal is Low.
  • the count value CNT 2 that is, the second count value of the updown counter 105 is in the range of a minimum value 0 to a maximum value 15, and the carry-over from 0 to 15 and 15 to 0 is not performed.
  • the second count value CNT 2 is input to a resolution determination circuit 106 , and the resolution is determined by the resolution determination circuit 106 to be output as a determination result DST.
  • the corresponding determination result DST is used as a signal specifying the horizontal resolution of the liquid crystal panel 10 within a digital circuit included in the timing controller, for example, in the timing control circuit 4 , shown in FIG. 1 .
  • FIG. 10 it is assumed that a noise is superposed on the DENA signal during the active (High) period and thus a small pulse having Low level is included in the DENA signal.
  • the edge detection circuit unit 100 a falling edge due to the noise is detected, and an EDG 1 output is detected ahead of a regular blanking start time (in the present embodiment, two falling edges are assumed to be detected).
  • 500 and 200 are sequentially maintained subsequent to a regular value 1024, and 300 is maintained and output even during a blanking period for which 1024 is to be maintained.
  • the EDG 2 signal is generated, and since the MTN value 300 is smaller than a predetermined value, for example, an intermediate value 912 between horizontal resolutions of SVGA and XGA, a value of the pulse width determination output PDT of the DENA pulse width determination circuit unit 104 becomes Low in synchronization with a falling edge of the EDG 2 .
  • the updown counter 105 is a counter inputted in synchronization with the rising edge of the EDG 2 .
  • the updown counter 105 since the updown counter 105 is in High at the rising edge of the EDG 2 , the count value maintains the maximum vale 15.
  • the updown counter 105 reads out the PDT output Low in synchronization with a rising edge of the EDG 2 so as to decrease the count value from 15 to 14. That is, an increment or decrement processing is performed by the updown counter 105 always one horizontal period late.
  • the count value CNT 2 of the updown counter 105 is input to the resolution determination circuit 106 which determines whether the count value CNT 2 is larger or smaller than a predetermined value (for example, 7), being output as the determination result DST.
  • a predetermined value for example, 7
  • a 4-bit counter (count from 0 to 15) has been exemplified as the updown counter 105 in the fourth embodiment, for example, a 3-bit counter (count from 0 to 7) obtained by simplifying a circuit or an 8-bit counter (count from 0 to 255) to achieve even higher noise elimination effect may be selected.
  • the updown counter 105 counts in synchronization with the rising edge of the EDG 2 in the fourth embodiment, the updown counter 105 counts in synchronization with the falling edge of the EDG 2 if it is possible not to consider a variation timing of the PDT signal.
  • the falling edge of the DENA is counted by using the DENA 2 signal from which a noise is eliminated and it is determined whether the count value is larger or smaller than a predefined threshold value (912) so as to count it, and thus it is possible to obtain the resolution judgment circuit 50 in which there is no possibility of an erroneous judgment even when a noise is superposed.
  • an intermediate value of each list to be judged is preferably set to the predetermined threshold value.
  • the D-FF circuit has been exemplified as a delay element adopted in the delay circuit block 31 , however, other delay elements may be used.
  • a delay circuit using an inverter circuit, having a plurality of stages, exemplified in JP-A-11-214964 or JP-A-11-251884 may be adopted, or a delay circuit in which an inverter circuit and the D-FF circuit are combined may be adopted.
  • the data enable signal (DENA) is at High level while the data enable signal (DENA) is active
  • the level while the data enable signal (DENA) is active is not necessarily High, but the data enable signal (DENA) may be a Low active signal.
  • the above description can be applied in the first to fourth embodiments by slightly modifying the configuration of a logic circuit of the DENA rising edge detection unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electronic Switches (AREA)
  • Liquid Crystal (AREA)
US11/340,632 2005-07-25 2006-01-27 Noise elimination circuit of matrix display device and matrix display device using the same Active 2027-12-15 US7554534B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005214580A JP4894183B2 (ja) 2005-07-25 2005-07-25 ノイズ除去回路およびこれを用いたマトリックス表示装置、ならびに解像度弁別回路
JP2005-214580 2005-07-25

Publications (2)

Publication Number Publication Date
US20070018932A1 US20070018932A1 (en) 2007-01-25
US7554534B2 true US7554534B2 (en) 2009-06-30

Family

ID=37674244

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/340,632 Active 2027-12-15 US7554534B2 (en) 2005-07-25 2006-01-27 Noise elimination circuit of matrix display device and matrix display device using the same

Country Status (5)

Country Link
US (1) US7554534B2 (enExample)
JP (1) JP4894183B2 (enExample)
KR (1) KR100802459B1 (enExample)
CN (1) CN100583221C (enExample)
TW (1) TW200705356A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303750A1 (en) * 2007-06-01 2008-12-11 National Semiconductor Corporation Video display driver with data enable learning
US20100177067A1 (en) * 2009-01-14 2010-07-15 Chia-Hsin Tung Method and circuit for controlling timings of display devices using a single data enable signal
US20110148850A1 (en) * 2009-12-18 2011-06-23 Oki Semiconductor Co., Ltd. Synchronous processing system and semiconductor integrated circuit
US20150332624A1 (en) * 2014-05-13 2015-11-19 BOE Technology Group Cp., Ltd. Signal frequency setting device and method for time schedule controller and display device

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5161426B2 (ja) * 2006-01-31 2013-03-13 株式会社ジャパンディスプレイセントラル 表示制御装置
JP4305533B2 (ja) * 2007-03-12 2009-07-29 エプソンイメージングデバイス株式会社 表示装置
JP4903074B2 (ja) * 2007-03-27 2012-03-21 ラピスセミコンダクタ株式会社 同期信号生成回路
KR101377463B1 (ko) * 2007-05-10 2014-04-02 삼성디스플레이 주식회사 노이즈 제거회로와, 이를 구비한 게이트 구동회로 및 표시장치
KR101544916B1 (ko) * 2008-08-05 2015-08-18 삼성디스플레이 주식회사 정전기 방전 내성이 강화된 액정 표시 장치
JP5235819B2 (ja) * 2009-08-12 2013-07-10 キヤノン株式会社 画像処理装置、画像処理方法
CN102024435B (zh) * 2009-09-22 2013-03-06 群康科技(深圳)有限公司 电压调整模块、电压调整方法及液晶显示装置
CN102034444B (zh) * 2009-09-30 2013-01-23 北京京东方光电科技有限公司 液晶显示器源驱动方法及驱动装置
US8654259B2 (en) 2010-02-18 2014-02-18 Sharp Kabushiki Kaisha Image processing system and display device
US8687125B2 (en) 2010-05-18 2014-04-01 Sharp Kabushiki Kaisha Image processing system and display device for carrying out subtraction or addition of a pixel value of a target pixel in accordance with a value equivalent to a noise quantity
JP6425115B2 (ja) * 2014-07-03 2018-11-21 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 タイミングコントローラ及び表示装置
JP6349171B2 (ja) * 2014-07-07 2018-06-27 ローム株式会社 ノイズ除去回路、タイミングコントローラ、ディスプレイ装置、電子機器、ソースドライバの制御方法
US9379743B2 (en) * 2014-07-30 2016-06-28 Intel Corporation Method and apparatus for signal edge boosting
CN107612539B (zh) * 2017-09-30 2020-04-10 深圳市华星光电技术有限公司 一种电平转化器的时钟输入信号异常的处理方法
CN107947786A (zh) * 2017-11-16 2018-04-20 湖南工业大学 翻斗式雨量计计数脉冲产生方法
US11367390B2 (en) * 2018-12-24 2022-06-21 Novatek Microelectronics Corp. Display apparatus and method for noise reduction
JP6940535B2 (ja) * 2019-01-30 2021-09-29 ファナック株式会社 電子装置及びノイズ除去システム
US11423829B2 (en) * 2020-03-02 2022-08-23 Silicon Works Co., Ltd. Clock generating circuit for LED driving device and method for driving
TWI724840B (zh) * 2020-03-26 2021-04-11 友達光電股份有限公司 顯示面板

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5664045A (en) * 1995-04-27 1997-09-02 Samsung Electronics Co., Ltd. Video signal processor for compensating skew and eliminating noise
US5835542A (en) * 1996-07-19 1998-11-10 Utek Semiconductor Corporation Digital data separator for separating data signals from clock signals in an encoded data stream
JPH11214964A (ja) 1998-01-21 1999-08-06 Sony Corp ノイズ除去装置
JPH11251884A (ja) 1997-12-26 1999-09-17 Lg Semicon Co Ltd ノイズ除去装置
JPH11282401A (ja) 1998-03-30 1999-10-15 Toshiba Corp 平面表示装置
JP2000209076A (ja) 1999-01-18 2000-07-28 Mitsubishi Electric Corp ノイズ検出回路
JP2000341098A (ja) 1999-05-27 2000-12-08 Mitsubishi Electric Corp ノイズフィルタ回路
JP2002271427A (ja) 2001-03-09 2002-09-20 Ricoh Co Ltd ノイズ除去回路
US7259755B1 (en) * 1999-09-04 2007-08-21 Lg.Philips Lcd Co., Ltd. Method and apparatus for driving liquid crystal display panel in inversion

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01172998A (ja) * 1987-12-28 1989-07-07 Matsushita Electric Ind Co Ltd ディスプレイ制御回路
JP2733664B2 (ja) * 1988-04-25 1998-03-30 富士通株式会社 マトリクス表示装置
JP3516332B2 (ja) * 1998-02-20 2004-04-05 三洋電機株式会社 表示装置
KR100315011B1 (ko) * 1998-03-27 2002-02-28 주식회사 현대 디스플레이 테크놀로지 액정표시장치의모드검출회로
JP2001282198A (ja) * 2000-03-31 2001-10-12 Digital Electronics Corp プログラム式表示装置の誤動作防止方法
JP4487437B2 (ja) * 2001-03-29 2010-06-23 三菱電機株式会社 映像信号処理装置及び映像信号処理方法
JP4598355B2 (ja) * 2002-10-10 2010-12-15 ソニー株式会社 ディスクドライブ装置、プリピット検出方法
JP4508583B2 (ja) * 2003-09-05 2010-07-21 三洋電機株式会社 液晶表示制御装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5664045A (en) * 1995-04-27 1997-09-02 Samsung Electronics Co., Ltd. Video signal processor for compensating skew and eliminating noise
US5835542A (en) * 1996-07-19 1998-11-10 Utek Semiconductor Corporation Digital data separator for separating data signals from clock signals in an encoded data stream
JPH11251884A (ja) 1997-12-26 1999-09-17 Lg Semicon Co Ltd ノイズ除去装置
JPH11214964A (ja) 1998-01-21 1999-08-06 Sony Corp ノイズ除去装置
JPH11282401A (ja) 1998-03-30 1999-10-15 Toshiba Corp 平面表示装置
JP2000209076A (ja) 1999-01-18 2000-07-28 Mitsubishi Electric Corp ノイズ検出回路
JP2000341098A (ja) 1999-05-27 2000-12-08 Mitsubishi Electric Corp ノイズフィルタ回路
US7259755B1 (en) * 1999-09-04 2007-08-21 Lg.Philips Lcd Co., Ltd. Method and apparatus for driving liquid crystal display panel in inversion
JP2002271427A (ja) 2001-03-09 2002-09-20 Ricoh Co Ltd ノイズ除去回路

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080303750A1 (en) * 2007-06-01 2008-12-11 National Semiconductor Corporation Video display driver with data enable learning
US8072394B2 (en) * 2007-06-01 2011-12-06 National Semiconductor Corporation Video display driver with data enable learning
US20100177067A1 (en) * 2009-01-14 2010-07-15 Chia-Hsin Tung Method and circuit for controlling timings of display devices using a single data enable signal
US8237694B2 (en) * 2009-01-14 2012-08-07 Novatek Microelectronics Corp. Method and circuit for controlling timings of display devices using a single data enable signal
US20110148850A1 (en) * 2009-12-18 2011-06-23 Oki Semiconductor Co., Ltd. Synchronous processing system and semiconductor integrated circuit
US9058789B2 (en) * 2009-12-18 2015-06-16 Lapis Semiconductor Co., Ltd. Synchronous processing system and semiconductor integrated circuit
US9882569B2 (en) 2009-12-18 2018-01-30 Lapis Semiconductor Co., Ltd. Synchronous processing system and semiconductor integrated circuit
US20150332624A1 (en) * 2014-05-13 2015-11-19 BOE Technology Group Cp., Ltd. Signal frequency setting device and method for time schedule controller and display device

Also Published As

Publication number Publication date
CN100583221C (zh) 2010-01-20
KR20070013203A (ko) 2007-01-30
US20070018932A1 (en) 2007-01-25
KR100802459B1 (ko) 2008-02-14
JP4894183B2 (ja) 2012-03-14
JP2007033659A (ja) 2007-02-08
TW200705356A (en) 2007-02-01
CN1904994A (zh) 2007-01-31

Similar Documents

Publication Publication Date Title
US7554534B2 (en) Noise elimination circuit of matrix display device and matrix display device using the same
US8972811B2 (en) Panel driving circuit that generates panel test pattern and panel test method thereof
KR100290102B1 (ko) 표시모드 판별기능구비 표시장치 및 표시모드 판별방법
US10679546B2 (en) Timing controller, display apparatus having the same and signal processing method thereof
US7239355B2 (en) Method of frame synchronization when scaling video and video scaling apparatus thereof
KR101319088B1 (ko) 평판 패널용 화상 모드 제어기 및 그를 포함한 평판 표시장치
US9691316B2 (en) Display device capable of clock synchronization recovery
CN102201190B (zh) 同步信号生成装置及显示装置
JP3754531B2 (ja) 液晶表示装置
US8638283B2 (en) Timing controller, image display device, timing signal generating method, and image display control method
US20080278465A1 (en) Dot clock generating circuit, semiconductor device, and dot clock generating method
JP2003015579A (ja) 表示位置制御装置
US5473387A (en) Field decision circuit
JP7697324B2 (ja) 撮像装置
CN104517555A (zh) 运用于影像显示的时序控制器及其控制方法
CN113012617A (zh) 显示装置、显示驱动电路及显示驱动方法
CN114446258B (zh) 显示面板及显示装置
JP2007041437A (ja) 表示装置
KR100697385B1 (ko) 화면 위치 조정 회로
JPH0573022A (ja) デイスプレイ制御装置
JP2025135393A (ja) ソースドライバ及び表示装置
JPH05119747A (ja) 液晶表示装置
JPH05165451A (ja) 表示制御回路
JPH02302792A (ja) 表示制御装置
JP2002099240A (ja) 表示制御装置、表示装置、媒体及び情報集合体

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAKAKI, JIRO;ISHIGUCHI, KAZUHIRO;MINAMI, AKIHIRO;REEL/FRAME:017516/0772

Effective date: 20060119

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12

AS Assignment

Owner name: TRIVALE TECHNOLOGIES, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI ELECTRIC CORPORATION;REEL/FRAME:059024/0437

Effective date: 20211228