US6072353A - Logic circuit with overdriven off-state switching - Google Patents

Logic circuit with overdriven off-state switching Download PDF

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Publication number
US6072353A
US6072353A US08/636,559 US63655996A US6072353A US 6072353 A US6072353 A US 6072353A US 63655996 A US63655996 A US 63655996A US 6072353 A US6072353 A US 6072353A
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voltage
state
main switching
logic circuit
node
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Akira Matsuzawa
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Socionext Inc
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01735—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by bootstrapping, i.e. by positive feed-back

Definitions

  • the present invention generally relates, as is indicated, to a logic circuit. More particularly, the present invention relates to a logic circuit for high speed operation at low power supply voltage.
  • FIG. 31 is a diagram of a logic circuit of the prior art.
  • Reference labels 3101, 3120 and 3110 designate a logic input terminal, an output terminal and a power supply for supplying a voltage of Vdd, respectively.
  • Reference labels 3108 and 3109 designate a P-channel FET (field effect transistor) and an N-channel FET, respectively.
  • Reference labels 3106 and 3107 designate bias power supplies for supplying a voltage of Vs.
  • Reference labels 3102 and 3103 designate capacitors.
  • Reference labels 3104 and 3105 designate an N-channel FET and a P-channel FET, respectively.
  • the logic circuit shown in FIG. 31 suffers from the following inherent limitations. That is to say, a leak current flows when the FETs 3108 and 3109 are in an OFF state. Furthermore, it is not possible in the prior art to sufficiently drive (i.e., overdrive) the FETs 3108 and 3109, or to sufficiently out off the FETs 3108 and 3109 by biasing its gate with deep backward bias voltage. Therefore, the logic circuit according to the prior art results in a high dissipation power and cannot perform a high-speed operation at a low voltage.
  • a logic circuit includes: a main switching means for changing the conduction state between at least two terminals in accordance with a voltage supplied to a control terminal; and a voltage converting means for is converting a voltage at an input terminal and outputting the converted voltage to the control terminal.
  • the voltage converting means includes a voltage generating means and a sub switching means.
  • the sub switching means includes an SOI (semiconductor-on-insulator) structure.
  • the voltage generating means includes at least one of a capacitor; a battery and a high dielectric material.
  • the voltage converting means supplies a higher voltage than that of the input terminal to the control terminal in a first state, the first state being a state of the input terminal where the main switching means is conductive.
  • the voltage converting means supplies a lower voltage than that of the input terminal to the control terminal in a second state, the second state being a state of the input terminal where the main switching means is non-conductive.
  • the voltage converting means supplies a higher voltage than that of the input terminal to the control terminal in a first state; and the voltage converting means supplies a lower voltage than that of the input terminal to the control terminal in a second state; the first state being a state of the input terminal where the main switching means is conductive; and the second state being a state of the input terminal where the main switching means is non-conductive.
  • the voltage converting means further includes a capacitor of which a first terminal is connected to the input terminal; and wherein the sub switching means connects a second terminal of the capacitor to the control terminal of the main switching means in the first state; and connects the second terminal of the capacitor to the voltage generating means, and connects the control terminal of the main switching means to the ground in a state other than the first state.
  • the voltage converting means further includes a capacitor of which a first terminal is connected to the input terminal; and wherein the sub switching means connects a second terminal of the capacitor to the control terminal of the main switching means in the second state; and connects the first terminal of the capacitor to the control terminal of the main switching means, and connects the second terminal of the capacitor to the ground in a state other than the second state.
  • the voltage converting means further includes a first capacitor of which a first terminal is connected to the input terminal and a second capacitor of which a first terminal is connected to the input terminal; and wherein the sub switching means connects a second terminal of the first capacitor to the ground and connects a second terminal of the second capacitor to the control terminal of the main switching means in the first state; and connects the second terminal of the first capacitor to the control terminal of the main switching means and connects the second terminal of the second capacitor to the voltage generating means in the second state.
  • the main switching means includes an N-channel MOS FET.
  • the main switching means includes a P-channel MOS FET.
  • the main switching means includes a complementary MOS FETs.
  • a logic circuit includes: a first and a second main switching means for changing conduction state between at least two terminals in accordance with a voltage supplied to a control terminal; a first voltage converting means for converting a voltage at an input terminal and outputting the converted voltage to the control terminal of the first main switching means; and a second voltage converting means for converting a voltage at an input terminal and outputting the converted voltage to the control terminal of the second main switching means, wherein the first voltage converting means includes a first capacitor having a first terminal and a second terminal, a second capacitor having a first terminal and a second terminal, a first sub switching means, and a first voltage generating means; the first terminal of the first capacitor and the first terminal of the second capacitor being connected to the input terminal; the second voltage converting means includes a third capacitor having a first terminal and a second terminal, a fourth capacitor having a first terminal and a second terminal, a second sub switching means, and a second voltage generating means; the first terminal of the third capacitor
  • the invention described herein makes possible the advantage of providing a logic circuit which enables a high-speed operation at a low power supply voltage, and in which a leak current (i.e., a dissipation power) is small.
  • the logic circuit according to the present invention contributes to increasing operation speed and reducing dissipation power, especially for a battery-powered portable equipment.
  • FIG. 1 is a schematic diagram of a logic circuit 1 according to the present invention.
  • FIGS. 2A-2C are diagrams of a first example of the logic circuit according to the present invention.
  • FIG. 3 is a diagram of the first example of the logic circuit according to the present invention using an N-channel FET and P-channel FETs.
  • FIG. 4 is a diagram illustrating voltages of nodes 301-304 in FIG. 3 in states I and II.
  • FIG. 5A is a diagram of a logic circuit for substituting a P-channel FET in place of the N-channel FET used as the main switching device 220 in FIG. 2A.
  • FIG. 5B is a diagram of a logic circuit according to the present invention using N-channel FETs and a P-channel FET as the two switches.
  • FIGS. 6A-6C are diagrams of a second example of the logic circuit according to the present invention.
  • FIG. 7 is a diagram of the second example of the logic circuit according to the present invention using an N-channel FET and P-channel FETs.
  • FIG. 8 is a diagram illustrating voltages of nodes 701-704 in FIG. 7 in states I and II.
  • FIGS. 9A-9C are diagrams of a third example of the logic circuit according to the present invention.
  • FIG. 10 is a diagram of the third example of the logic circuit according to the present invention using an N-channel FET and P-channel FETs.
  • FIG. 11 is a diagram illustrating voltages of nodes 1001-1005 in FIG. 10 in states I and II.
  • FIG. 12 is a diagram of a circuit configuration for substituting in place of the main switching device 1020 shown in FIG. 10.
  • FIG. 13 is a diagram of a fourth example of the logic circuit according to the present invention.
  • FIG. 14 is a diagram of a logic circuit according to the present invention using FETs as the four switches in FIG. 13.
  • FIG. 15 is a diagram of the fifth example of the logic circuit according to the present invention.
  • FIG. 16 is a diagram of a logic circuit according to the present invention using FETs as the four switches in FIG. 15.
  • FIG. 17 is a diagram of a sixth example of the logic circuit according to the present invention.
  • FIG. 18 is a diagram of a seventh example of the logic circuit according to the present invention.
  • FIG. 19 is a diagram of a eighth example of the logic circuit according to the present invention.
  • FIG. 20 is a diagram illustrating a structure of an N-channel MOS FET and its equivalent circuit.
  • FIG. 21 is a diagram illustrating a structure of a P-channel MOS FET and its equivalent circuit.
  • FIG. 22A is a diagram illustrating a part of the first example of the logic circuit.
  • FIG. 22B is a diagram illustrating a equivalent circuit shown in FIG. 22A.
  • FIG. 23 is a diagram illustrating a structure of an N-channel transistor and a P-channel transistor both having an SOI structure.
  • FIG. 24A is a diagram illustrating a transfer gate type switch.
  • FIG. 24B Is a graph showing a conductance Gon between a drain and a source of the transfer gate as a function of a source voltage Vs.
  • FIG. 25 is a graph showing a conductance Gon between a drain and a source of the transfer gate as a function of a source voltage Vs when the source voltage is low.
  • FIG. 26 is a graph showing a polarization of the capacitor of which insulating material is high dielectric constant material as a function of a supplied voltage.
  • FIG. 27 is a circuit diagram of a logic circuit of the prior art to be compared.
  • FIGS. 28A and 2B are graphs showing voltages Va and Vc of the logic circuit of the prior art, and voltages Va and Vc of the logic circuit of the present invention, respectively at the rising edge of the output signal.
  • FIGS. 28C and 28D are graphs showing voltages Vb and Vc of the logic circuit of the prior art, and voltages Vb and Vc of the logic circuit of the present invention, respectively at the falling edge of the output signal.
  • FIG. 29 is a circuit diagram of the logic circuit of the present invention.
  • FIG. 30A is a graph showing voltages Va and Vb of the logic circuit of the present invention at the rising edge of the output signal.
  • FIG. 30B is a graph showing a gate voltage Vg of the main switching device and an output voltage Vout of the logic circuit of the prior art at the rising edge of the output signal.
  • FIG. 30C is a graph showing voltages Va and Vb of the logic circuit of the present invention at the falling edge of the output signal.
  • FIG. 30D is a graph showing a gate voltage Vg of the main switching device and an output voltage Vout of the logic circuit of the prior art at the falling edge of the output signal.
  • FIG. 31 is a diagram of a logic circuit of the prior art.
  • V followed by a reference label representing a node designates a voltage potential of the node with respect to the ground.
  • V1 represents a voltage potential of the "node 1" from the ground level.
  • V1 represents a voltage potential of the "node 1" from the ground level.
  • V1 represents a voltage potential of the node with respect to the ground level.
  • a logic low level (hereinafter, referred to as an “L (low) level”) is equal to 0 V (i.e., the ground potential)
  • a logic high level (hereinafter, referred to as an “H (high) level”) is equal to a voltage potential higher than that of the ground by a power supply voltage Vdd.
  • a node of a logic circuit (especially for an output node) should be either of an H level and an L level, should not be at an intermediate potential level between the H level and the L level. In an actual logic circuit, however, a voltage of a node reads an intermediate voltage level in an transient state.
  • FIG. 1 is a schematic diagram of a logic circuit 1 according to the present invention.
  • the logic circuit 1 includes a voltage converter 10 and a main switching device 20.
  • the voltage converter 10 drives the main switching device 20 in accordance with a voltage of node 11.
  • the main switching device 20 is an active device having nodes 21-23, and a conduction state between nodes 22 and 23 changes in accordance with a voltage of the nodes 21.
  • a state wherein a switching device conducts a current is referred to as an "ON" state
  • a state wherein a switching device does not conduct a current is referred to as an "OFF" state.
  • an FET field effect transistor
  • nodes 21, 22 and 23 correspond to a gate, a drain and a source, respectively.
  • Node 14 is supplied with a power supply voltage Vdd.
  • a resistor 13 pulls up node 12, which functions as an output terminal of the logic circuit 1, to the power supply voltage Vdd.
  • node 12 is at the L level.
  • node 12 is at the H level.
  • FIG. 1 although nods 22 is pulled up, and node 23 is connected to the ground, the configuration is not limited to this.
  • the main switching device 20 a plurality of switching device which are connected so as to constitute a transfer gate can be utilized.
  • the voltage converter 10 converts a voltage of node 11 and then outputs the converted voltage to node 21, thereby improving characteristics of the main switching device 20. These improvements include several aspects: increasing a switching speed (i.e., an improvement in transient characteristics), and reducing a ON-state resistance of a switching device (i.e., an improvement in static characteristics).
  • the voltage converter 10 used in the logic circuit 1 according to the present invention has three types: Types 1-3.
  • Type 1 when node 11 is at the L level (i.e., the ground level), node 21 is at the ground level, and when node 11 is at the H level (i.e., the Vdd level), node 21 is at a voltage level of (Vdd+Vov1).
  • Vdd and Vov1 designate positive voltage values. Therefore, in the logic circuit 1 of Type 1, when node 21 is at the H level, i.e., the main switching device 20 is ON state, the main switching device 20 is overdriven. In other words, when the main switching device 20 is ON state, node 21 which in a control terminal of the main switching device 20 1s supplied with a higher voltage than Vdd.
  • a turn-on time of the main switching device 20 enables reduction in a turn-on time of the main switching device 20, and reduction in a turn-on resistance (i.e., a resistance corresponding to a drain-source voltage VDS(sat) in ON state) of the main switching device 20.
  • a turn-on resistance i.e., a resistance corresponding to a drain-source voltage VDS(sat) in ON state
  • the main switching device 20 used in the logic circuit 1 of Type 1 an FET of which threshold voltage Vt is equal to 0.35 V or more is preferably used.
  • the threshold voltage Vt is a gate-source voltage Vgs when a drain current Id is zero, which is also referred to as a pinch-off voltage.
  • Type 2 when node 11 is at the L level (i.e., the ground level), node 21 is at a level of -Vov2, and when node 11 is at the H level (i.e., the Vdd level), node 21 is at a voltage level of Vdd.
  • Vov2 designates positive voltage values. Therefore, in the logic circuit 1 of Type 2, when node 21 is at the L level, i.e., the main switching device 20 is OFF state, the main switching device 20 is cut off sufficiently. In other words, when the main switching device 20 is OFF state, node 21 which is a control terminal of the main switching device 20 is supplied with a lower voltage than the ground level.
  • an FET of which threshold voltage Vt is equal to 0.35 V or less is preferably used.
  • Type 3 when node 11 is at the L level (i.e., the ground level), node 21 is at a level of -Vov2, and when node 11 is at the H level (i.e., the Vdd level), node 21 is at a voltage level of (Vdd+Vov1). Therefore, in the logic circuit 1 of Type 3, when node 21 is at the H level, i.e., the main switching device 20 is ON state, the main switching device 20 is overdriven. In other words, when the main switching device 20 is ON state, node 21 which is a control terminal of the main switching device 20 is supplied with a higher voltage than Vdd. This enables reduction in a turn-on time of the main switching device 20, and reduction in a turn-on resistance (i.e., a resistance corresponding to a drain-source voltage VDS(sat) in ON state) of the main switching device 20.
  • the main switching device 20 when node 21 is at the L level, i.e., the main switching device 20 is OFF state, the main switching device 20 is cut off sufficiently. In other words, when the main switching device 20 is OFF state, node 21 which is a control terminal of the main switching device 20 is supplied with a lower voltage than the ground level. This enables reduction in a turn-off time of the main switching device 20, and increasing a turn-off resistance (i.e., a resistance corresponding to a drain-source voltage VDS(sat) In ON state) of the main switching device 20.
  • a turn-off resistance i.e., a resistance corresponding to a drain-source voltage VDS(sat) In ON state
  • an FET of which threshold voltage Vt is equal to 0.35 V or less is preferably used.
  • FIGS. 2A-2C are diagrams of a first example of the logic circuit according to the present invention.
  • the logic circuit of the first example is classified into the above Type 1.
  • the logic circuit shown in FIG. 2A includes a voltage converter 210 and a main switching device 220.
  • Node 211 receives an input signal from an external device, thereby being set to either of the H level and the L level.
  • a state wherein a main switching device (designated by the reference label 220 in the first example) is OFF is referred to as "state I”
  • a state wherein a main switching device is ON is referred to as "state II”.
  • state II the voltage converter 210 outputs to node 221 a voltage of (Vdd+Vov1) higher than the voltage Vdd which is supplied to node 211.
  • the main switching device 220 As the main switching device 220, a MOS (metal-oxide-semiconductor) FET is used, and node 221, 222 and 223 are a gate, a drain and a source, respectively.
  • MOS metal-oxide-semiconductor
  • node 221, 222 and 223 are a gate, a drain and a source, respectively.
  • SOI semiconductor-on-insulator
  • MES metal-semiconductor
  • TFT thin film transistor
  • the voltage converter 210 includes switches S20 and S21, a voltage generator 214, and a capacitor 212. Switches S20 and S21 can be constituted using a plurality of FETs. Although a power supply voltage Vdd is used as the voltage generator 214 in the first example, a voltage value supplied by the voltage generator 214 is not limited to Vdd. Although an external power supply is used of the voltage generator 214 in the first example, the type of the voltage generator 214 is not limited to this. As the voltage generator in all examples in the specification, a capacitor, a battery and the like can be used. As a capacitor, such as the capacitor 212 and a capacitor as the voltage generator 214, a capacitor using material of a high dielectric constant is preferably used for the reason described in detail later.
  • FIG. 2A corresponds to state I.
  • FIG. 23 is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 2A in state I.
  • FIG. 2C is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 2A in state II.
  • node 211 is at the L level.
  • node 211 to which one terminal of the capacitor 212 is connected, is connected to the ground, while the other terminal of the capacitor 212 is connected to the voltage generator 214.
  • the capacitor 212 is charged by the voltage Vdd supplied by the voltage generator 214.
  • node 221 which is a gate of the main switching device 220 is connected to the ground, whereby electric charge in the gate of the main switching device 220 in discharged. An a result, the turn-off time of the main switching device 220 is shortened.
  • node 211 is at the H level.
  • node 211 to which one terminal of the capacitor 212 is connected, is pulled up to the power supply voltage Vdd, while the other terminal of the capacitor 212 is connected to node 221.
  • node 221 which is a gate of the main switching device 220 is supplied with a voltage of (Vdd+Vov1).
  • Vov1 is a positive voltage and is governed by the voltage supplied by the voltage generator 214 and a gate-source capacitance of the main switching device 220.
  • a relationship C212>>Cgs is preferably satisfied, where C212 and Cs are a capacitance of the capacitor 212 and a capacitance of the gate-source capacitance of the main switching device 220, respectively.
  • FIG. 3 is a diagram of the first example of the logic circuit according to the present invention using an N-channel FET and P-channel FETs.
  • a voltage converter 310 and a main switching device 320 correspond to the voltage converter 210 and the main switching device 220, respectively.
  • An inverter 330 inverts a voltage supplied to node 301 and then outputs to node 302. In other words, node 302 is at the L level when node 301 is at the H level, while nods 302 is at the H level when node 301 is at the L level.
  • a capacitor 312 and a voltage generator 314 correspond to the capacitor 212 and the voltage generator 214, respectively.
  • FETs 332 and 334 function as the switch S20, and an FET 336 functions as the switch S21.
  • the main switching device 320 corresponds to the main switching device 220, and nodes 304, 322 and 323 correspond to nodes 221, 222 and 223, respectively.
  • the logic circuit shown in FIG. 3 operates in the same manner as discussed above with respect to FIGS. 2A-2C with the exception that the main switching device 320 is OFF state when node 301 is at the H level, while the main switching device 320 is ON state when nods 301 is at the L level (i.e., a logic of node 301 is inverted).
  • node 302 corresponds to node 211.
  • using of an iverter per se is not an essential part of the present invention, rather the inverter is necessary to switch switching devices in the voltage converter at the predetermined phase. Therefore, further details are omitted.
  • FIG. 4 is a diagram illustrating voltages of nodes 301-304 in FIG. 3 in states I and II.
  • a voltage V304 of node 304 which is a gate of the main switching device 320, is (Vdd+Vov1) in state II. Due to the voltage V304, the main switching device 320 is sufficiently driven. As a result, this circuit topology enables reduction in the turn-on time and the turn-on resistance.
  • a drain current Id is given by the following equation as a function of a gate-source voltage Vgs of an N-channel MOS translator used as the main switching device 320:
  • Vt is a threshold voltage of the N-channel FET.
  • an operation voltage of an LSI large scale integrated circuit
  • Vdd is 1.0 V
  • the threshold voltage Vt is 0.35 V
  • the voltage generator 314 supplies the power supply voltage Vdd.
  • the present invention allows the drain current of the main switching device 320 to increase, thereby enabling a higher operation.
  • FIG. 5A is a diagram of a logic circuit for substituting a P-channel FET in place of the N-channel FET used as the main switching device 220 in FIG. 2A.
  • FIG. 5B is a diagram of a logic circuit according to the present invention using N-channel FETs and a P-channel FET as the two switches.
  • a voltage converter 510 and a main switching device 520 correspond to the voltage converter 210 and the main switching device 220, respectively.
  • Node 511, 521-523 correspond to node 211, 221-223, respectively.
  • Switches S50 and S51, a capacitor 512, and a voltage generator 514 correspond to the switches S20 and S21, the capacitor 212, and the voltage generator 214, respectively.
  • a power supply 516 supplies an output voltage to node 523 through the main switching device 520.
  • the voltage generator 514 supplies the same voltage value as a voltage of Vdd supplied by the power supply 516, however, the voltage level is not limited to Vdd
  • the switch S50 is placed in a position such that contact C1 is connected to contact C2, while in state II, the switch S50 is placed in a position such that contact C1 is connected to contact C3.
  • the switch S51 is placed in a position such that contact C1 is connected to contact C2, while in state II, the switch S51 is placed in a position such that contact C1 is not connected to contact C2.
  • one terminal of the capacitor 512, which is connected to node 511 is at the H level, while the other terminal of the capacitor 512, which is connected to contact C1 of the switch S50, is at the ground level. Therefore, in state I, the capacitor 512 is charged.
  • the gate of the main switching device 520 i.e., node 521) is set to be at the H level.
  • node 511 will go down to the L level, and the other terminal of the capacitor 512 will be connected to node 521.
  • node 521 is supplied with a voltage of -Vov1 (Vov1: a positive voltage).
  • FET 550 corresponds to the switch S51
  • FETs 551 and 552 correspond to the switch S50
  • a signal "D bar" supplied to the gate of the FET 550 is a signal obtained by inverting the signal D.
  • the logic circuit shown in FIG. 5B is a complementary circuit to the logic circuit shown in FIG. 3, and its operation in similar to that of the logic circuit of FIG. 3.
  • FIGS. 6A-6C are diagrams of a second example of the logic circuit according to the present invention.
  • the logic circuit of the second example is classified into the above Type 2.
  • the logic circuit shown in FIG. 6A includes a voltage converter 610 and a main switching device 620.
  • Node 611 receives an input signal from an external device, thereby being set to either of the H level and the L level.
  • the voltage converter 610 outputs to node 621 a voltage of -Vov2 lower than the ground level (i.e., 0 V) which is supplied to node 611.
  • a MOS (metal-oxide-semiconductor) FET is used, and node 621, 622 and 623 are a gate, a drain and a source, respectively.
  • the voltage converter 610 includes switches S60 and S61, and a capacitor 612. Switches S60 and S61 can be constituted using a plurality of FETs. Although contact C3 of the switch S60 is connected to the ground in the second example, a voltage value supplied to contact C3 of the switch S60 is not limited to this ground potential. As will be appreciated from the operation described below, however, contact C3 of the switch S60 is preferably connected to the ground.
  • FIG. 6A corresponds to state I.
  • FIG. 6B is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 6A in state I.
  • FIG. 6C is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 6A in state II.
  • node 611 is at the L level.
  • node 611 to which one terminal of the capacitor 612 is connected, is connected to the ground, while the other terminal of the capacitor 612 is connected to node 621.
  • node 621 which is the gate of the main switching device 620 is supplied with a voltage -Vov2.
  • Vov2 is a positive voltage and is governed by the voltage supplied to node 611 and a gate-source capacitance of the main switching device 620.
  • a relationship C612>>Cgs is preferably satisfied, where C612 and Cgs are a capacitance of the capacitor 612 and a capacitance of the gate-source capacitance of the main switching device 620, respectively.
  • node 611 to which one terminal of the capacitor 612 is connected, is at the H level, while the other terminal of the capacitor 612 is connected to the ground.
  • the capacitor 612 is charged by the voltage Vdd supplied by an external device connected to node 611.
  • FIG. 7 is a diagram of the second example of the logic circuit according to the present invention using an N-cannel FET and P-channel FETs.
  • a voltage converter 710 and a main switching device 720 correspond to the voltage converter 610 and the main switching device 620, respectively.
  • An inverter 730 inverts a voltage supplied to node 701 and then outputs to node 702. In other words, node 702 is at the L level when node 701 is at the H level, while node 702 is at the H level when node 701 ia at the L level.
  • a capacitor 712 corresponds to the capacitor 612.
  • FETs 732 and 734 function as the switch S60, and an FET 736 functions as the switch S61.
  • the main switching device 720 corresponds to the main switching device 620, and nodes 704, 722 and 723 correspond to nodes 621, 622 and 623, respectively.
  • the logic circuit shown in FIG. 7 operates in the same manner as discussed above with respect to FIGS. 6A-6C. Therefore, further details are omitted.
  • FIG. 8 is a diagram illustrating voltages of nodes 701-704 in FIG. 7 in states I and II.
  • a voltage V704 of node 704, which is a gate of the main switching device 720, is -Vov2 in state I. Due to the voltage V704, the main switching device 720 is sufficiently cut off. As a result, this circuit topology enables reduction in the turn-off time and increase in turn-off resistance.
  • FIGS. 9A-9C are diagrams of a third example of the logic circuit according to the present invention.
  • the logic circuit of the third example is classified into the above Type 3.
  • the logic circuit shown in FIG. 9A includes a voltage converter 910 and a main switching device 920.
  • Node 911 receives an input signal from an external device, thereby being set to either of the H level and the L level.
  • the voltage converter 910 outputs to node 921 a voltage of -Vov2 lower than the ground level (i.e., 0 V) which is supplied to node 911.
  • the voltage converter 910 outputs to node 921 a voltage of (Vdd+Vov1) higher then a voltage of Vdd which is supplied to node 911.
  • a MOS metal-oxide-semiconductor
  • nd nods 921, 922 and 923 are a gate, a drain and a source, respectively.
  • the voltage converter 910 includes switches S90 and S91, a voltage generator 914, and capacitors 912 and 913. Switches S90 and S91 can be constituted using a plurality of FETs. Although a power supply voltage Vdd is used as the voltage generator 914 in the third example, a voltage value supplied by the voltage generator 914 is not limited to Vdd. Although an external power supply is used as th voltage generator 914 in the third example, the type of the voltage generator 914 is not limited to this. As the voltage generator 914, for example, a capacitor using material of a high dielectric constant can be used.
  • FIG. 9A corresponds to state I.
  • FIG. 9B is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 9A in state I.
  • FIG. 9C is a diagram representing an equivalent circuit of the logic circuit shown in FIG. 9A in state II.
  • node 911 is at the L level.
  • node 911 to which one terminal of the capacitor 912 is connected, is connected to the ground, while the other terminal of the capacitor 912 is connected to the voltage generator 914.
  • the capacitor 912 is charged by the voltage Vdd supplied by the voltage generator 914.
  • node 921 which is a gate of the main switching device 920 is connected to the ground through the capacitor 913.
  • the capacitor 913 as will be described later, is charged in state II, thereby supplying a voltage of Vov2 between nodes 911 and 921. Therefore, a voltage of node 921 will be Vov2.
  • Vov2 is a positive voltage and is governed by the voltage supplied to node 911 (i.e., Vdd) and a gate-source capacitance of the main switching device 920.
  • a relationship C913>>Cgs is preferably satisfied, where C913 and Cgs are a capacitance of the capacitor 913 and a capacitance of the gate-source capacitance of the main switching device 920, respectively.
  • node 911 is at the H level.
  • node 911 to which one terminal of the capacitor 913 is connected, is pulled up to the power supply voltage Vdd, while the other terminal of the capacitor 913 is connected to the ground.
  • the capacitor 913 is charged by the power supply voltage Vdd.
  • node 921 which is the gate of the main switching device 920 is connected to node 911 through the capacitor 912.
  • the capacitor 912 as discussed above, is charged in state I, thereby supplying a voltage of Vov1 between node 911 and 921. Therefore, a voltage of node 921 is (Vdd+Vov1).
  • Vov1 is a positive voltage and is governed by the voltage supplied by the voltage generator 914 (i.e., Vdd) and a gate-source capacitance of the main switching device 920.
  • a relationship C912>>Cgs is preferably satisfied, where C912 and Cgs are a capacitance of the capacitor 912 and a capacitance of the gate-source capacitance of the main switching device 920, respectively.
  • FIG. 10 is a diagram of the third example of the logic circuit according to the present invention using an N-channel FET and P-channel FETs.
  • a voltage converter 1010 and a main switching device 1020 correspond to the voltage converter 910 and the main switching device 920, resistively.
  • An inverter 1030 inverts a voltage supplied to node 1001 and then outputs to node 1002.
  • node 1002 is at the L level when node 1001 is at the H level, while node 1002 is at the H level when node 1001 is at the L level.
  • Capacitors 1012 and 1013, and a voltage generator 1014 correspond to the capacitors 912 and 913, and the voltage generator 914, respectively.
  • FETs 1032 and 1034 function as the switch S90
  • an FET 1036 functions as the switch S91.
  • the main switching device 1020 corresponds to the main switching device 920, and nodes 1005, 1022 and 1023 correspond to nodes 921, 922 and 923, respectively.
  • the logic circuit shown in FIG. 10 operates in the same manner as discussed above with respect to FIGS. 9A-9C. Therefore, further details are omitted.
  • FIG. 11 is a diagram illustrating voltages of nodes 1001-1005 in FIG. 10 in states I and II.
  • a voltage V1005 of node 1005, which is a gate of the main switching device 1020, is -Vov2 in state I and (Vdd+Vov1) in state II. Due to the voltage V1005, the main switching device 1020 is sufficiently driven and sufficiently cut off. As a result, this circuit topology enables reduction in the turn-on time, the turn-off time and the turn-on resistance, and increase in the turn-off resistance.
  • FIG. 12 is a diagram of a circuit configuration for substituting in place of the main switching device 1020 shown in FIG. 10.
  • Node 1205 corresponds to node 1005 and receives the output from the voltage converter 1010.
  • Node 1225 is pulled up to the power supply voltage Vdd.
  • FETs 1220 and 1221 turn on alternately, thereby changing the voltage of node 1222.
  • the FET 1220 is OFF and the FET 1221 is ON when node 1205 is at the H level, whereby node 1222 will become the L level.
  • the FET 1220 is ON and the FET 1221 is OFF when node 1205 is at the L level, whereby node 1222 will become the H level.
  • the voltage converter in the logic circuit of the third example outputs the voltage of -Vov2 ( ⁇ 0) in state I, and outputs the voltage of (Vdd+Vov1) (>Vdd), thereby efficiently driving the main switching devices having the configuration of the series connection of the complementary FETs shown in FIG. 12.
  • the voltage generator 914 generates the power supply voltage Vdd, and that node 911 at the H level is equal to the power supply voltage Vdd. Accordingly, the capacitors 912 and 913 are charged by the voltage Vdd.
  • the charging voltage is not limited to Vdd.
  • a voltage which the voltage generator 914 generates is preferably high.
  • contact C3 of the switch S91 is connected to the ground, contact C3 can be set to a different voltage level. In order to deeply cut off the main switching device, contact C3 is preferably supplied with a lower voltage potential than the ground level.
  • FIG. 13 is a diagram of a fourth example of the logic circuit according to the present invention.
  • the fourth example includes the circuit topology as discussed above with respect to the first example and the second example.
  • an operation of a voltage converter 1310 and an FET 1331 will be described below.
  • a state wherein the FET 1331 is OFF state is referred to as state I
  • a state wherein the FET 1331 is ON state is referred to as state II.
  • state I a switch 1312 is placed in a position such that a capacitor 1311 is connected to a voltage generator 1313
  • a switch 1315 is placed in a position such that a gate of the FET 1331 is connected to a power supply 1380.
  • a switch 1312 is placed in a position such that a capacitor 1311 is connected to the FET 1331, and a switch 1315 is placed in a position such that the gate of the FET 1331 is not connected to a power supply 1380.
  • the gate of the FET 1331 is supplied with a voltage potential lower than the ground level (i.e., 0V). This voltage potential corresponds to the voltage of the -Vov2 as discussed in the second example.
  • a state wherein the FET 1332 is OFF state is referred to as state I
  • a state wherein the FET 1332 is ON state is referred to as state II.
  • state I a switch 1322 is placed in a position such that a capacitor 1321 is connected to a voltage generator 1323, and a switch 1325 is placed in a position such that a gate of the FET 1332 is connected to the ground.
  • state II a switch 1322 is placed in a position such that a capacitor 1321 is connected to the FET 1332, and a switch 1325 is placed in a position such that the gate of the FET 1332 is not connected to the ground.
  • Vdd the gate of the FET 1332 is supplied with a voltage potential higher than the power supply voltage Vdd. This voltage potential corresponds to the voltage of (Vdd+Vov1) as discussed In the first example.
  • the power supply 1380 supplying the power supply voltage Vdd, and the power generators 1313 and 1323 are used.
  • the power generators 1313 and 1323 generate a voltage of, for example, Vdd.
  • the power supply 1380 can be used.
  • a contact which is connected to a negative electrode of the voltage generator 1313 is connected to the ground; and a contact which is connected to a positive electrode of the voltage generator 1323, is connected to a positive electrode of the power supply 1380.
  • Such circuit topology requires only one kind of the power supply (i.e., power supply 1380). The some is true with respect to the other logic circuits according to the present invention as discussed in the other examples.
  • Node 1390 is at the L level when node 1301 is at the H level, while Node 1390 is at the H level when node 1301 is at the L level.
  • the logic circuit shown in FIG. 13 functions as an inverter.
  • FIG. 14 is a diagram of a logic circuit accords ing to the present invention using FETs as the four switches in FIG. 13.
  • FETs 1412 and 1414 correspond to the switch 1312
  • FETs 1422 and 1424 correspond to the switch 1322
  • FETs 1415 and 1425 correspond to the switches 1315 and 1325, respectively.
  • the logic circuit shown in FIG. 14 operates in the same manner as discussed referring to FIG. 13. Therefore, further details are omitted.
  • FIG. 15 is a diagram of the fifth example of the logic circuit according to the present invention.
  • the logic circuit shown in FIG. 15 has similar configurations to the logic circuit of FIG. 13 with the exception that the FETs 1331 and 1332 are replaced with FETs 1531 and 1532, and that node 1301 is replaced with nodes 1501 and 1502.
  • the switches 1312, 1315, 1322 and 1325 operate in the same manner as discussed above with respect to FIG. 13.
  • node 1501 receives D bar as an input signal.
  • FETs 1531 and 1532 turn on and turn off simultaneously, thereby changing conduction state between nodes 1591 and 1592. For example, when nodes 1501 and 1502 are at the L level and the H level, respectively, the FETs 1531 and 1532 are ON state. On the other hand, when nodes 1501 and 1502 are at the H level and the L level, respectively, the FETs 1531 and 1532 are OFF state.
  • the logic circuit according to the present invention is applied to a transfer gate.
  • FIG. 16 is a diagram of a logic circuit according to the present invention using FETs as the four switches in FIG. 15.
  • the logic circuit shown in FIG. 16 operates in the same manner as discussed referring to FIG. 15. Therefore, further details are omitted.
  • FIG. 17 is a diagram of a sixth example of the logic circuit according to the present invention.
  • the voltage converter 1010 in the third example described with respect to FIG. 10 driven FETs 1731 and 1732.
  • node 1701 When node 1701 is at the L level, voltages of nodes 1705 and 1706 are (Vdd+Vov1) and -Vov2, respectively, whereby nodes 1791 and 1792 are conduction state.
  • node 1701 is at the H level, voltages of nodes 1705 and 1706 are -Vov2 and (Vdd+Vov1), respectively, whereby nodes 1791 and 1792 are in a non-conduction state.
  • FIG. 18 is a diagram of a seventh example of the logic circuit according to the present invention.
  • the logic circuit in FIG. 18 receives D1 and D2 as inputs at nodes 1801 and 1802, performs a NAND operation and outputs the operation results to node 1834. In other words, only when both of nodes 1801 and 1802 are at the L level, node 1834 will become the H level.
  • FETs 1830 and 1831 are driven by the voltage converter shown in FIG. 5B.
  • FETs 1832 and 1833 are driven by the voltage converter shown in FIG. 3.
  • a capability for driving the main switching devices is enhanced, thereby enabling higher operations at a lower voltage.
  • FIG. 19 is a diagram of a eighth example of the logic circuit according to the present invention. The operation of the logic circuit of the eighth example is described below.
  • node 1901 is at the H level, an FET 1903 is ON state, an FET 1913 is OFF state. Therefore, an FET 1915 is ON state and an FET 1905 is OFF state, whereby node 1931 is at the L level.
  • a voltage generator 1904 generates a voltage of Vs
  • a voltage supply 1981 supplies a power supply voltage Vdd
  • node 1901 is supplied with a voltage of Vdd
  • a capacitor 1902 is charged by a voltage of (Vdd-Vs).
  • a gate of the FET 1916 is supplied with a summation of a voltage of node 1901 (i.e., H level) and a voltage due to electric charge in a capacitor 1912 (described later).
  • node 1901 When node 1901 is at the L level, an FET 1903 is OFF state, an FET 1913 is ON state. Therefore, an FET 1915 is OFF state and an FET 1905 is ON state, whereby node 1931 is at the H level.
  • a voltage generator 1914 generates a voltage of Vs
  • a voltage supply 1981 supplies a power supply voltage Vdd
  • node 1901 is at the ground level
  • a capacitor 1902 is charged by a voltage of -Vs.
  • a gate of the FET 1905 is supplied with a summation of a voltage of node 1901 (i.e., L level) and voltage due to electric charge in a capacitor 1902.
  • a gate of any ON-state FET of the FETs 1905 and 1915 is supplied with a higher voltage than Vdd, and a gate of any OFF-state FET of the FETs 1905 and 1915 is supplied with a lower voltage than the ground level.
  • the operation speed at a low operation voltage can be improved.
  • the eighth example utilizes a simple circuit configuration, resulting in reduction of a chip area in an integrated circuit.
  • FIG. 20 is a diagram illustrating a structure of an N-channel MOS FET and its equivalent circuit.
  • FIG. 21 is a diagram illustrating a structure of a P-channel MOS FET and its equivalent circuit.
  • a MOS FET as shown in FIGS. 20 and 21, has a junction capacitor CJ and diodes between the drain and the backgate, and between the source and the backgate.
  • FIG. 22A in a diagram illustrating a part of the first example of the logic circuit
  • FIG. 22B is a diagram illustrating a equivalent circuit shown in FIG. 22A. It is assumed that one terminal of terminals of a capacitor Cc, which is not dotted, is pulled up to Vdd after the capacitor Cc is supplied with a voltage of Vdd.
  • a gate voltage Vg will be represented below using a junction capacitance Cj and a gate capacitance Cg after electric charge is re-distributed.
  • FIG. 23 is a diagram illustrating a structure of an N-channel transistor and a P-channel transistor both having an SOI structure.
  • a drain current Id of an FET can be expressed using the following expression:
  • a delay time ⁇ d of the logic circuit is expressed as follows:
  • the voltage converter increases a voltage supplied to the gate, whereby ⁇ will become large, and the operation speed will be enhanced at an ordinary threshold voltage Vt (i.e., about 0.5 V). Moreover, when the main switching device is OFF state, the gate is at the ground level, thereby suppressing the leak current.
  • Vt i.e., about 0.5 V
  • the gate voltage is -Vov2.
  • the leak current Idleak is equal to ⁇ w*10.sup.(-Vov2-Vt/s).
  • -Vov2 is about -0.3 V, while Vt is equal to or less than 0.35 V, thereby sufficiently suppressing the leak current Idleak.
  • a transistor having a lower Vt can be used as the main switching device. Therefore, increased drive current due to the small Vt overdrives the device, whereby a remarkable advantage of the high operating speed according to the present invention.
  • FIG. 24A is a diagram illustrating a transfer gate type switch
  • FIG. 24B is a graph showing a conductance Gon between a drain and a source of the transfer gate as a function of a source voltage Vs.
  • Vtn and Vtp are threshold voltages of an N-channel FET and a P-channel FET, respectively.
  • Vdd the power supply voltage
  • FIG. 25 is a graph showing a conductance Gon between a drain and a source of the transfer gate as a function of a source voltage Vs when the source voltage is low.
  • the source voltage is about 1.0 V
  • both of the two complementary FETs do not turn-on in a certain region of the source voltage (see hatched region in FIG. 25).
  • the voltage converter of the logic circuit according to the present invention outputs a voltage higher than the power supply voltage Vdd to the gate of the main switching device, and provides deep backward bias to Vgs when the threshold voltage Vt of the main switching device is low. As a result, high speed operation at a low operation voltage is possible according to the present invention.
  • FIG. 26 is a graph showing a polarization of the capacitor of which insulating material is high dielectric constant material as a function of a supplied voltage.
  • the capacitor using the high dielectric constant material shows polarization characteristics of FIG. 26.
  • FIG. 27 is a circuit diagram of a logic circuit of the prior art to be compared.
  • FIGS. 28A and 28B are graphs showing voltages Va and Vc of the logic circuit of the prior art, and voltages Va and Vc of the logic circuit of the present invention, respectively at the rising edge of the output signal.
  • FIGS. 28C and 28D are graphs showing voltages Vb and Vc of the logic circuit of the prior art, and voltages Vb and Vc of the logic circuit of the present invention, respectively at the falling edge of the output signal.
  • the power supply voltage Vdd is 1.0 V. Referring to FIG.
  • the gate delay time is 1.2 ns.
  • Vb is equal to 0.1 V when the main switching device is OFF state, generating the leak current.
  • Vb is higher than Vdd by only 0.1 V when the main switching device is ON state. Therefore, the drive power is not sufficient.
  • the gate delay time is 1.0 ns.
  • Vb is equal to 0 V when the main switching device is OFF state. Therefore, the leak current does not flow. Vb is higher than Vdd by 0.3 V, resulting in high drive power.
  • the gate delay time is equal to 0.75 ns.
  • FIG. 29 is a circuit diagram of the logic circuit of the present invention.
  • an ordinary complementary MOS inverter is used to be compared.
  • a voltage of 0.5 V as the power supply voltage Vdd is used for the logic circuit of the present invention and the prior art.
  • FIG. 30A is a graph showing voltages Va and Vb of the logic circuit of the present invention at the rising edge of the output signal.
  • FIG. 30B is a graph showing a gate voltage Vg of the main switching device and an output voltage Vout of the logic circuit of the prior art at the rising edge of the output signal.
  • FIG. 30C is a graph showing voltages Va and Vb of the logic circuit of the present invention at the falling edge of the output signal.
  • FIG. 30D is a graph showing a gate voltage Vg of the main switching device and an output voltage Vout of the logic circuit of the prior art at the falling edge of the output signal.
  • Va is higher than Vdd by 0.5 V when the main switching device is OFF state, whereby the main switching device is deeply cut off. Va is lower than the ground level by 0.3 V, whereby the drive capability is enhanced.
  • the gate delay time is 1.63 ns.
  • the gate delay time of the prior art is 5.6 ns.
  • the gate delay time of the prevent invention is smaller than that of the prior art. Specifically, the gate delay time of the present invention is only 1.88 ns, while the gate delay time of the prior art is 6.4 ns.
  • the logic circuit according to the present invention enables enhancing the operation speed especially in the low operation voltage region.
  • a terminal which is not connected to the node receiving the input signal can be set to a voltage other than the power supply voltage of Vdd and the ground level.
  • the voltage generators 1313 and 1323 are provided in addition to the power supply 1380.
  • a voltage which is generated by the voltage generators 1313 and 1323 is not limited to Vdd.
  • the power supply 1380 can be used in place of the voltage generators 1313 and 1323.
  • the contact, which is connected to the negative electrode of the voltage generator 1313 can be connected to the ground, and the contact, which is connected to the positive electrode of the voltage generator 1323, can be connected to the positive electrode of the power supply 1380.
  • this modification of the above voltage potential is within the scope of the present invention.
  • a terminal other than the control terminal i.e., is drain or a source in case of an FET
  • a terminal other than the control terminal i.e., is drain or a source in case of an FET
  • node 222 of the main switching device 220 is in a floating state
  • node 222 can be pulled up to the power supply voltage Vdd in an actual circuit.
  • nodes 222 and 223 can be used as output terminals.
  • a drain voltage and a source voltage of an FET included in the voltage converter are forward direction voltages with respect to a substrate of the transistor.
  • the power supply voltage is equal to or lower than 1.0 V, however, the drain voltage and the source voltage do not cause a deep forward bias.
  • this forward bias can be avoided if the substrate of each transistor is controlled such that, for example, a substrate of a P-channel MOS FET (i.e., an N-well) is at a higher voltage potential then the power supply voltage, and a substrate of a N-channel MOS FET (i.e., a P-well) is at a lower voltage potential than the ground. Also, floating the substrate using the SOI technology will avoid the forward bias.
  • the voltage of the drain or the source will be at a higher voltage with respect to the transistor substrate, a voltage is supplied between the drain and the source when the transistor constituting the switching circuit is OFF state, thereby causing an off-leak current between the drain and the source.
  • transistors for switching are used, and a gate width thereof is small. Therefore, the present invention does not suffer from the problem due to the off-leak current.
  • the off-leak current can be avoided by setting the threshold voltage to a high value.

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232821B1 (en) * 2000-01-15 2001-05-15 Cirrus Logic, Inc. System for allowing below-ground and rail-to-rail input voltages
US6307420B1 (en) * 1997-01-10 2001-10-23 Xilinx, Inc. Circuit with ramp-up control for overcoming a threshold voltage loss in an NMOS transistor
US6433389B1 (en) * 2000-06-09 2002-08-13 Advanced Micro Devices, Inc. Silicon on insulator logic circuit utilizing diode switching elements
US6621321B2 (en) * 2001-06-20 2003-09-16 Analog Devices, Inc. Circuit for conditioning output waveform
US20040095159A1 (en) * 2002-11-20 2004-05-20 Hajime Kimura Semiconductor device and driving method thereof
US20040119529A1 (en) * 2002-12-19 2004-06-24 Parris Michael C. Powergate control using boosted and negative voltages
US20040155698A1 (en) * 2003-02-12 2004-08-12 Hajime Kimura Semiconductor device, electronic device having the same, and driving method of the same
US6794905B2 (en) * 2001-03-28 2004-09-21 Nippon Precision Circuits Inc. CMOS inverter
US20050099068A1 (en) * 2002-12-25 2005-05-12 Hajime Kimura Digital circuit having correcting circuit and electronic apparatus thereof
US20050275448A1 (en) * 2004-06-11 2005-12-15 Commissariat A L'energie Atomique Control method for an analogue switch
US20100026372A1 (en) * 2008-07-30 2010-02-04 Yen-An Chang Power switch for transmitting a power source of low voltage between regular mode and deep-power-down mode
US20140285241A1 (en) * 2013-03-22 2014-09-25 Denso Corporation Driver circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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GB2431785B (en) * 2005-10-27 2008-05-07 Toumaz Technology Ltd Current mode logic digital circuits
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US8143913B2 (en) * 2007-04-17 2012-03-27 Panasonic Corporation Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system
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WO2014038115A1 (ja) * 2012-09-06 2014-03-13 パナソニック株式会社 半導体集積回路
CN104677392B (zh) * 2015-02-12 2017-11-07 深圳怡化电脑股份有限公司 一种传感器信号处理电路
WO2019183174A1 (en) * 2018-03-20 2019-09-26 Circuit Seed, Llc CHARGE TRANSFER LOGIC (CTL) USING COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR DEVICES (CIFET) AND / OR COMPLEMENTARY SWITCHED CURRENT FIELD EFFECT TRANSISTOR DEVICES (CsiFET)

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059816A (en) * 1989-06-20 1991-10-22 Nec Corporation High speed booster circuit
US5065049A (en) * 1990-08-10 1991-11-12 Samsung Electronics Co., Ltd. MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage
JPH04357710A (ja) * 1991-06-03 1992-12-10 Nippon Telegr & Teleph Corp <Ntt> 論理回路
JPH0514166A (ja) * 1991-07-01 1993-01-22 Nippon Telegr & Teleph Corp <Ntt> Ｃｍｏｓ論理回路
JPH0522096A (ja) * 1991-07-11 1993-01-29 Matsushita Electric Ind Co Ltd 高圧スイツチング回路
JPH05160697A (ja) * 1991-12-06 1993-06-25 Sansei Denshi Japan Kk 情報転送制御回路及びこれを使用する情報伝達回路
US5268600A (en) * 1992-02-14 1993-12-07 Samsung Electronics Co., Ltd. Boosting clamping circuit and output buffer circuit using the same
JPH0637604A (ja) * 1992-07-17 1994-02-10 Nec Corp 三角波発生回路
JPH0653792A (ja) * 1992-07-30 1994-02-25 Matsushita Electric Ind Co Ltd 信号制御回路
US5296765A (en) * 1992-03-20 1994-03-22 Siliconix Incorporated Driver circuit for sinking current to two supply voltages
JPH06204756A (ja) * 1992-12-28 1994-07-22 Sony Corp バツフア回路
JPH07249979A (ja) * 1994-03-10 1995-09-26 Hitachi Ltd 半導体集積回路装置
JPH07283716A (ja) * 1994-04-13 1995-10-27 Fujitsu Ltd 出力回路及び半導体集積回路
US5594380A (en) * 1994-04-29 1997-01-14 Hyubdai Electronics Industries Co., Ltd. Bootstrap circuit and data output buffer having the bootstrap circuit
US5680071A (en) * 1995-01-27 1997-10-21 Matsushita Electronics Corporation Tristate voltage boosted integrated circuit
US5686854A (en) * 1996-03-14 1997-11-11 Magl Power Inc. Isolated driver circuit for high frequency solid-state switches
US5699018A (en) * 1995-12-08 1997-12-16 Mitsubishi Denki Kabushiki Kaisha Negative voltage generator
US5729165A (en) * 1996-04-04 1998-03-17 National Science Council 1.5v full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage deep-submicron CMOS VLSI
US5825217A (en) * 1996-05-29 1998-10-20 Amir Lehavot Low power accelerated switching for MOS circuits

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059816A (en) * 1989-06-20 1991-10-22 Nec Corporation High speed booster circuit
US5065049A (en) * 1990-08-10 1991-11-12 Samsung Electronics Co., Ltd. MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage
JPH04357710A (ja) * 1991-06-03 1992-12-10 Nippon Telegr & Teleph Corp <Ntt> 論理回路
JPH0514166A (ja) * 1991-07-01 1993-01-22 Nippon Telegr & Teleph Corp <Ntt> Ｃｍｏｓ論理回路
JPH0522096A (ja) * 1991-07-11 1993-01-29 Matsushita Electric Ind Co Ltd 高圧スイツチング回路
JPH05160697A (ja) * 1991-12-06 1993-06-25 Sansei Denshi Japan Kk 情報転送制御回路及びこれを使用する情報伝達回路
US5268600A (en) * 1992-02-14 1993-12-07 Samsung Electronics Co., Ltd. Boosting clamping circuit and output buffer circuit using the same
US5296765A (en) * 1992-03-20 1994-03-22 Siliconix Incorporated Driver circuit for sinking current to two supply voltages
JPH0637604A (ja) * 1992-07-17 1994-02-10 Nec Corp 三角波発生回路
JPH0653792A (ja) * 1992-07-30 1994-02-25 Matsushita Electric Ind Co Ltd 信号制御回路
JPH06204756A (ja) * 1992-12-28 1994-07-22 Sony Corp バツフア回路
JPH07249979A (ja) * 1994-03-10 1995-09-26 Hitachi Ltd 半導体集積回路装置
JPH07283716A (ja) * 1994-04-13 1995-10-27 Fujitsu Ltd 出力回路及び半導体集積回路
US5594380A (en) * 1994-04-29 1997-01-14 Hyubdai Electronics Industries Co., Ltd. Bootstrap circuit and data output buffer having the bootstrap circuit
US5680071A (en) * 1995-01-27 1997-10-21 Matsushita Electronics Corporation Tristate voltage boosted integrated circuit
US5699018A (en) * 1995-12-08 1997-12-16 Mitsubishi Denki Kabushiki Kaisha Negative voltage generator
US5686854A (en) * 1996-03-14 1997-11-11 Magl Power Inc. Isolated driver circuit for high frequency solid-state switches
US5729165A (en) * 1996-04-04 1998-03-17 National Science Council 1.5v full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage deep-submicron CMOS VLSI
US5825217A (en) * 1996-05-29 1998-10-20 Amir Lehavot Low power accelerated switching for MOS circuits

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307420B1 (en) * 1997-01-10 2001-10-23 Xilinx, Inc. Circuit with ramp-up control for overcoming a threshold voltage loss in an NMOS transistor
US6232821B1 (en) * 2000-01-15 2001-05-15 Cirrus Logic, Inc. System for allowing below-ground and rail-to-rail input voltages
US6433389B1 (en) * 2000-06-09 2002-08-13 Advanced Micro Devices, Inc. Silicon on insulator logic circuit utilizing diode switching elements
US6794905B2 (en) * 2001-03-28 2004-09-21 Nippon Precision Circuits Inc. CMOS inverter
US6621321B2 (en) * 2001-06-20 2003-09-16 Analog Devices, Inc. Circuit for conditioning output waveform
US20040095159A1 (en) * 2002-11-20 2004-05-20 Hajime Kimura Semiconductor device and driving method thereof
US8564329B2 (en) 2002-11-20 2013-10-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US7965106B2 (en) 2002-11-20 2011-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US7327168B2 (en) 2002-11-20 2008-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US7053692B2 (en) * 2002-12-19 2006-05-30 United Memories, Inc. Powergate control using boosted and negative voltages
US20040119529A1 (en) * 2002-12-19 2004-06-24 Parris Michael C. Powergate control using boosted and negative voltages
US8314514B2 (en) 2002-12-25 2012-11-20 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US8698356B2 (en) 2002-12-25 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US11139323B2 (en) 2002-12-25 2021-10-05 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US7411318B2 (en) 2002-12-25 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US20080291352A1 (en) * 2002-12-25 2008-11-27 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US10535684B2 (en) 2002-12-25 2020-01-14 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US9741749B2 (en) 2002-12-25 2017-08-22 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US9368526B2 (en) 2002-12-25 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Digital circuit having correcting circuit and electronic apparatus thereof
US20050099068A1 (en) * 2002-12-25 2005-05-12 Hajime Kimura Digital circuit having correcting circuit and electronic apparatus thereof
US8258847B2 (en) 2003-02-12 2012-09-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device having the same, and driving method of the same
EP1447911A1 (en) 2003-02-12 2004-08-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device having the same, and driving method of the same
US20040155698A1 (en) * 2003-02-12 2004-08-12 Hajime Kimura Semiconductor device, electronic device having the same, and driving method of the same
US8786349B2 (en) 2003-02-12 2014-07-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device having the same, and driving method of the same
US20090167404A1 (en) * 2003-02-12 2009-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device, Electronic Device Having the Same, and Driving Method of the Same
US7528643B2 (en) * 2003-02-12 2009-05-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device having the same, and driving method of the same
US7274222B2 (en) * 2004-06-11 2007-09-25 Commissariat A L'energie Atomique Control method for an analogue switch
US20050275448A1 (en) * 2004-06-11 2005-12-15 Commissariat A L'energie Atomique Control method for an analogue switch
US20100026372A1 (en) * 2008-07-30 2010-02-04 Yen-An Chang Power switch for transmitting a power source of low voltage between regular mode and deep-power-down mode
US20140285241A1 (en) * 2013-03-22 2014-09-25 Denso Corporation Driver circuit
US9019000B2 (en) * 2013-03-22 2015-04-28 Denso Corporation Driver circuit having a storage device for driving switching device

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KR960039645A (ko) 1996-11-25
US6211720B1 (en) 2001-04-03
TW295745B (ja) 1997-01-11
CN1109403C (zh) 2003-05-21
CN1139317A (zh) 1997-01-01

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