US20240332426A1 - Thin film semiconductor switching device - Google Patents

Thin film semiconductor switching device Download PDF

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US20240332426A1
US20240332426A1 US18/576,205 US202218576205A US2024332426A1 US 20240332426 A1 US20240332426 A1 US 20240332426A1 US 202218576205 A US202218576205 A US 202218576205A US 2024332426 A1 US2024332426 A1 US 2024332426A1
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source
thin film
film transistor
drain
transistor according
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Douglas W. Barlage
Lhing Gem SHOUTE
Kenneth C. Cadien
Alex Munnlick MA
Eric Wilson MILBURN
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Synthergy Inc
Zinite Corp
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Zinite Corp
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Assigned to ZINITE CORPORATION reassignment ZINITE CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SYNTHERGY INC.
Assigned to SYNTHERGY INC. reassignment SYNTHERGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BARLAGE, DOUGLAS W., CADIEN, KENNETH C., MA, ALEX MUNNLICK, MILBURN, ERIC WILSON, SHOUTE, LHING GEM
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    • H01L29/7869—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H01L29/66969—
    • H01L29/78603—
    • H01L29/78618—
    • H01L29/78642—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Definitions

  • the present invention relates to semiconductor devices. More specifically, the present invention relaters to thin film semiconductor switching devices, such as transistors.
  • Thin film semiconductor switching devices such as thin film transistors (TFTs) are widely employed in a variety of applications.
  • TFTs are perhaps the most common example of thin film semiconductor switching devices and are three-terminal field effect devices, comprising: a “source”; a “drain”; and a “gate”.
  • the gate is the control terminal used to enable or inhibit current flow from the source to the drain depending upon the voltage applied to the gate.
  • the electrical behavior of a TFT is dictated by the majority charge carrier of the active material, which is usually a semiconductor.
  • the majority charge carriers carry most of the electric charge, or electric current, through the semiconductor.
  • the majority charge carriers accumulate at the interface of a gate insulator and the semiconductor material to form a “channel” through which the charge carriers can move through the semiconductor material.
  • the TFT is said to be in an ‘ON’ state and electrical current flows from the source to the drain through the channel.
  • TFTs do not scale well to smaller dimensions, such as TFTs where the length of the semiconductor through which the channel can form is less than about 1000 nm, and especially those wherein the channel length is less than 200 nm.
  • a threshold voltage the gate voltage point at which the TFT is in an ‘ON’ state and the channel is formed to conduct current
  • This low (and in many cases, negative) threshold voltage can result in the poor output resistance and overall transistor performance of conventional TFTs manufactured at small dimensions and these TFTs often require a negative voltage to be applied to their gates to achieve an ‘OFF’ state and reduce leakage currents.
  • a thin film semiconductor device which can be manufactured with semiconductor/channel lengths less than 1000 nm and which have an inherent enhancement threshold voltage, resulting in devices which are normally in an ‘OFF’ state and are more readily controlled. Ideally, such devices would also be able to be fabricated as a Back End Of Line (“BEOL”) process in semiconductor fabrication.
  • BEOL Back End Of Line
  • a thin film transistor comprising: a substrate; an insulating layer formed on the substrate; a source formed on the insulating layer; a drain formed on the insulating layer and spaced from the source; an n-type semiconductor material formed on the insulating layer and extending between the source and the gate; a source-channel interfacial member electrically connecting at least the source to the semiconductor material; a gate dielectric layer formed over the semiconductor layer; and a gate formed over the dielectric layer such that, when a positive voltage is applied to the gate, current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the semiconductor material.
  • the n-type semiconductor material is a metal oxide. More preferably, the n-type semiconductor material is selected from the group comprising zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide and germanium oxide or combinations thereof.
  • the source-channel interfacial member is an oxide formed by catalytic growth of the source. Also preferably, the source-channel interfacial member is formed by atomic layer deposition. Also preferably, when source-channel interfacial member is an oxide formed by catalytic growth, the oxygen preferentially traverses to the source-channel interface, creating the source-channel interfacial member.
  • a vertical thin film transistor comprising: a substantially planar substrate; an insulating layer formed on the substrate; a source formed on the insulating layer; a second insulating layer formed on the source, the second insulating layer forming a vertical well having an inner surface; a source-channel interfacial member formed on the inner surface of the vertical well and the source; an n-type semiconductor material formed on the source-channel interfacial member, such that the source is electrically connected to the n-type semiconductor material by the source-channel interfacial member; a gate dielectric layer formed over the n-type semiconductor layer; a gate formed over the dielectric layer; and a drain formed on the insulating layer and in electrical contact with the n-type semiconductor material, wherein when a positive voltage is applied to the gate, current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the semiconductor material
  • a vertical thin film transistor comprising: a substantially planar substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upward from the drain; an n-type semiconductor material formed on inner surface of the well and the drain; a gate dielectric layer formed over the semiconductor layer; a gate formed over the dielectric layer; and a source and a source-channel interfacial member formed on the second insulating layer, the source-channel interfacial member electrically connecting the source to the n-type semiconductor material wherein, when a positive voltage is applied to the gate, current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the semiconductor material.
  • a vertical thin film transistor comprising: a substantially planar substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upward from the drain; an n-type semiconductor material formed on inner surface of the well and the drain; a gate dielectric layer formed over the semiconductor layer; a gate formed over the dielectric layer; and a source and a source-channel interfacial member formed on the second insulating layer, the source-channel interfacial member electrically connecting the source to the n-type semiconductor material wherein, when a positive voltage is applied to the gate, current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the semiconductor material.
  • FIGS. 1 a , 1 b , 1 c , 1 d and 1 e are cross-sectional views of prior art TFTs
  • FIG. 2 a is a cross-sectional view, taken along line A-A of FIG. 2 b , of a TFT in accordance with an embodiment of the present invention
  • FIG. 2 b is a top view of the TFT of FIG. 2 a;
  • FIG. 2 c is a cross-sectional view of a TFT in accordance with another embodiment of the present invention.
  • FIG. 2 d is a cross-sectional view of a TFT in accordance with another embodiment of the present invention.
  • FIG. 3 a is a schematic symbol of the TFT of FIG. 2 a;
  • FIG. 3 b is a cross-sectional view of a portion of the TFT of FIG. 2 a operating in a Forward Active state;
  • FIG. 3 c is a cross-sectional view of a portion of the TFT of FIG. 2 a operating in an OFF state;
  • FIG. 3 d is a cross-sectional view of a portion of the TFT of FIG. 2 a operating in a Zero Voltage state;
  • FIG. 4 a is a schematic symbol of the TFT of FIG. 2 c;
  • FIG. 4 b is a cross-sectional view of a portion of the TFT of FIG. 2 c operating in a Forward Active state;
  • FIG. 4 c is a cross-sectional view of a portion of the TFT of FIG. 2 c operating in an OFF state;
  • FIG. 4 d is a cross-sectional view of a portion of the TFT of FIG. 2 c operating in a Zero Voltage state
  • FIG. 5 a is a schematic symbol of the TFT of FIG. 2 d;
  • FIG. 5 b is a cross-sectional view of a portion of the TFT of FIG. 2 d operating in a Forward Active state;
  • FIG. 5 c is a cross-sectional view of a portion of the TFT of FIG. 2 d operating in an OFF state;
  • FIG. 5 d is a cross-sectional view of a portion of the TFT of FIG. 2 d operating in a Zero Voltage state;
  • FIG. 6 is flowchart representing the method of fabricating a TFT in accordance with an embodiment of the present invention.
  • FIGS. 7 a to 7 g are cross-sectional views of the stages of fabrication of a TFT in accordance with the method of FIG. 6 ;
  • FIGS. 7 h to 7 n are respective top views of the fabrication stages of the TFT of FIGS. 7 a to 7 g;
  • FIG. 8 a is a cross-sectional view of a TFT during fabrication, according to an embodiment of the present invention.
  • FIG. 8 b is a cross-sectional view of a TFT during fabrication, according to another embodiment of the present invention.
  • FIG. 8 c is a top view of the TFT of FIG. 8 a;
  • FIG. 8 d is a top view of the TFT of FIG. 8 b;
  • FIG. 9 a is a cross-sectional view of a vertical TFT according to another embodiment of the present invention.
  • FIG. 9 b is a cross-sectional view of another vertical TFT according to an embodiment of the present invention.
  • FIG. 9 c is a cross-sectional view of another vertical TFT according to an embodiment of the present invention.
  • FIG. 9 d is a cross-sectional view of a vertical TFT similar to that of FIG. 9 b but fabricated in a non-symmetric embodiment
  • FIGS. 10 a and 10 b are a flowchart of a method of fabricating a TFT according to another embodiment of the present invention.
  • FIGS. 11 a through 11 k are cross-sectional views showing stages of manufacturing a TFT according to the method of FIGS. 10 a and 10 b;
  • FIGS. 11 l through 11 v are corresponding top views of the TFT of FIGS. 11 a through 11 k , respectively;
  • FIGS. 12 a and 12 b are a flow chart of a method of fabricating a TFT according to another embodiment of the present invention.
  • FIGS. 13 a to 13 k are cross-sectional views of a TFT during fabrication, according to the method of FIGS. 12 a and 12 b ;
  • FIGS. 13 l to 13 v are top views of TFTs of FIGS. 13 a to 13 k , respectively.
  • forming is intended to comprise all semiconductor manufacturing techniques suitable and applicable therefor including, without limitation: deposition (chemical, atomic layer, physical vapor, etc.); sputtering; PECVD (Plasma Enhanced Chemical Vapor Deposition); implantation and annealing, oxidation; etc. as will be apparent to those of skill in the art.
  • FIG. 1 a shows a first example of a prior art TFT which is indicated generally at 100 a .
  • TFT 100 a consists of a substrate 120 with an insulation layer 118 formed thereon.
  • TFT 100 a further includes agate 102 , a source 106 and a drain 110 .
  • Gate 102 includes a gate electrode 104 and a gate contact 103
  • source 106 includes a source electrode 107 and a source contact 108
  • drain 110 includes a drain electrode 111 and a drain contact 112 .
  • source electrode 107 and source contact 106 can be the same or different materials.
  • the material of source contact 106 can be selected to provide a desired Work Function while the material of source electrode 107 can be selected to simplify connection of source electrode 107 to other devices, etc.
  • Gate electrode 104 and gate contact 103 , and drain electrode 111 and drain contact 112 can similarly be formed of the same respective materials or different materials, as desired.
  • TFT 100 a also includes a dielectric layer 114 and a semiconductor layer 116 . As is understood by those of skill in the art, TFT 100 a can optionally include a gate tuning layer 122 .
  • TFT 100 A relies upon the use of semiconductor layer 116 as an active material in which a channel can be formed.
  • semiconductor 116 When semiconductor 116 is in an active state, a channel is formed between source contact 108 and drain contact 112 allowing electrical current to flow therebetween.
  • a n-type semiconductor is shown.
  • FIG. 1 b which shows the relevant portions of interest of TFT 100 a in more detail, an accumulation layer 130 is illustrated.
  • Accumulation layer 130 is illustrated with a gradient, showing the varying concentration of electrons along the channel through semiconductor layer 116 , where the higher concentration of electrons (indicated by the darker color of accumulation layer 130 ) is closer to source contact 107 than drain contact 111 .
  • TFTs typically have two channels of current flow.
  • a first channel is formed through an ohmic connection between source contact 107 and drain contact 111
  • a second channel is formed by an accumulation layer at the interface between gate dielectric layer 114 and semiconductor layer 116 .
  • Conventional TFTs can also have output resistance problems if source contact 107 and drain contact 111 are too close to one another. For example, as mentioned above, if source contact 107 and drain contact 111 are less than about 1000 nm apart, and particularly if they are less than 200 nm apart, significant levels of leakage occurs. Accordingly, conventional TFTs are typically in an ‘ON’ state even under a zero-bias. In most cases, a negative gate voltage must be applied to conventional TFTs to create a depletion layer or region in order to limit the flow of current between source contact 107 and drain contact 111 to effectively turn the TFT “OFF”.
  • FIG. 1 e shows another type of a source gated TFT 100 e .
  • TFT 100 e is analogous to TFT 100 a with the exception that both source 106 ′ and drain 110 ′ of TFT 100 e are made of Schottky metals.
  • TFT 100 e utilizes a symmetry in source contact 106 ′ and drain contact 110 ′.
  • both TFT 100 d and 100 e face similar challenges as those described above with respect to TFT 100 a , particularly when fabricated in smaller dimensions.
  • FIG. 2 a shows a cross-sectional view of a TFT 200 a , taken along line 2 A- 2 A of FIG. 2 b , according to an embodiment of the present invention.
  • TFT 200 a includes a gate 202 , a source 206 and a drain 210 .
  • Gate 202 includes a gate electrode 204 and a gate contact 203
  • source 206 includes a source electrode 208 and a source contact 207
  • drain 210 includes a drain electrode 212 and a drain contact 211 .
  • the electrodes and contacts of each of these features can respectively be formed of the same materials, or the materials can be separately selected, as desired.
  • source contact 207 can be formed from a material selected for its desired Work function while source electrode 208 can selected from a material better suited to connection to other components of a circuit, such as metallization layers, etc.
  • TFT 200 a also includes a dielectric layer 214 and a semiconductor layer 216 .
  • TFT 200 a can optionally include a gate tuning layer 222 .
  • These layers, and TFT 200 a in general, are formed over an insulation layer 218 , which is formed over a substrate 220 .
  • substrate 220 will be a silicon wafer, as commonly used in the manufacture of semiconductors, however the present invention is not so limited and substrate 220 can, in fact, be a wide variety of materials including, without limitation: glass; ceramics; metals; flexible polymers or other plastics; etc.
  • semiconductor layer 216 is an n-type semiconductor layer.
  • N-type semiconductor layer 216 is a semiconductor material which is selected to preferably allow it to be formed at temperatures below 300 degrees centigrade. Examples of suitable materials for semiconductor layer 216 include, without limitation, zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, etc.
  • TFT 200 a further includes a source-channel interfacial member 250 that, in this embodiment, is a layer of p-type semiconductor material extending from source contact 207 to drain contact 211 under semiconductor layer 216 .
  • Source-channel interfacial member 250 electrically connects source contact 207 to semiconductor layer 216 and source contact 207 is otherwise electrically separated from semiconductor layer 216 . Further, in this example, source-channel interfacial member 250 electrically connects semiconductor layer 216 to drain contact 211 .
  • Gate contact 203 can comprise any elemental material or compound of materials with conducting properties. Examples of materials that can be used for gate contact 203 include titanium, titanium nitride, chrome, hafnium, tantalum nitride or any other single element or bi-metal element or compound. Gate electrode 204 can be formed of the same material as gate contact 203 or from another material which provides desired properties for connecting gate electrode 204 to other components.
  • Source 206 and drain 210 can comprise any elemental material or compound of materials with conducting properties.
  • source contact 207 and drain contact 211 can be a metal or a degenerate (highly doped) semiconductor.
  • suitable materials that can be used in source contact 207 and/or drain contact 211 include: nickel, tungsten, molybdenum, aluminum; gold; copper; cobalt; ruthenium; titanium nitride; tantalum nitride; silicon; and/or any III-V compound semiconductor with a high conductivity.
  • drain contact 211 consists of the same material as source contact 207 .
  • drain contact 211 consists of a material with a higher conductivity that is capable of providing a reduced barrier to electron transport than the material used in source contact 207 .
  • Source-channel interfacial member 250 is provided to create a repository of complimentary excess negative charge that functions to deplete the channel in at least the region of semiconductor layer 216 adjacent source contact 207 . In this manner, source-channel interfacial member 250 serves as an electron transport barrier, resulting in substantially no current flow through semiconductor layer 216 when TFT 200 a is in a ‘OFF’ state.
  • source-channel interfacial member 250 can be achieved in a variety of configurations, including a p-type semiconductor, an induced piezoelectric dipole, a controllable tunneling barrier, combinations thereof or other mechanisms to modulate injected current by an external applied field.
  • source-channel interfacial member 250 when implemented as a p-type semiconductor, can consist of elemental germanium or source-channel interfacial member 250 can be formed by using a p-type dopant in a relevant portion of semiconductor layer 216 .
  • source-channel interfacial member 250 can consist of an oxide or a sulfide, or another element corresponding to group VI(A) of the periodic table, or the chalcogens, such as oxygen, sulfur, selenium, tellurium or polonium.
  • Source-channel interfacial member 250 can also be formed by a catalytic growth of the material that forms source contact 207 . In such cases, the oxygen can preferentially traverse to the source-channel interface, creating the source-channel interfacial member. In other cases, source-channel interfacial member 250 can be formed by depositing a p-type dopant, such as a p-type metal oxide or another semiconductor, by way of a deposition technique, such as atomic layer deposition, sputtering physical vapor deposition or chemical vapor deposition.
  • a p-type dopant such as a p-type metal oxide or another semiconductor
  • source-channel interfacial member 250 has been formed as a continuous member extending from source contact 207 to drain contact 211 . While source-channel interfacial member 250 need only be located adjacent source contact 207 to electrically connect source contact 207 and semiconductor layer 216 , depending upon the manufacturing processes used to fabricate TFT 200 a , source-channel interfacial member 250 can be a formed as a layer extending between source contact 207 and drain contact 211 , or adjacent to just source contact 207 , or adjacent to each of source contact 207 and drain contact 211 .
  • semiconductor layer 216 is formed with compositional control such that semiconductor layer 216 is heavily n-type near source contact 207 and drain contact 211 to prevent carrier starvation during the ‘ON’ state of TFT 200 a .
  • semiconductor layer 216 is formed to be heavily n-type near source contact 207 , drain contact 211 and gate contact 203 which can allow tuning of the threshold voltage of TFT 200 a . Accordingly, the properties of TFT 200 a can be controlled based on the location and extent of n-type doping in semiconductor layer 216 .
  • dielectric layer 214 separates gate contact 203 from semiconductor layer 216 .
  • Dielectric layer 214 impedes the flow of electrons into gate contact 203 , allowing electrons to form a channel between source contact 207 and drain contact 211 with a large concentration of electrons.
  • Dielectric layer 214 can consist of materials such as, for example: hafnium oxide (HfO2); zirconium dioxide (ZrO 2 ); silicon dioxide (SiO 2 ); silicon nitride (Si 3 N 4 ); or any other suitable material as would occur to those of skill in the art.
  • TFT 200 a can also include an optional gate tuning layer 222 .
  • Gate tuning layer 222 can be an atomic layer of metal that is used to adjust the effective barrier height and/or Work function of the gate contact 203 , as desired, as will be apparent to those of skill in the art.
  • each of gate electrode 204 , source electrode 208 and drain electrode 212 are formed of highly conducting metals, such as copper or aluminum, that are used to electrically connect the corresponding electrode to the appropriate elements of the rest of the integrated circuit in which TFT 200 a is formed.
  • TFT 200 a also includes an insulation layer 218 formed over substrate 220 .
  • Substrate 220 serves as the foundation for the construction of components and devices, such as transistors and integrated circuits, and insulation layer 218 is a dielectric separating substrate 220 from source contact 207 and drain contact 211 .
  • insulation layer 218 include materials such as: silicon dioxide (SiO 2 ); silicon nitride (Si 3 N 4 ); aluminum oxide (Al 2 O 3 ); etc.
  • substrate 220 include silicon, glass, plastic materials and/or flexible polymers, printed circuit boards, etc. In some circumstances, such as the case illustrated in FIG.
  • source-channel interfacial member 250 extends between source contact 207 and drain contact 211 , and depending upon the material of substrate 220 , source-channel interfacial member 250 can also serve as insulation layer 218 , in which case it would formed before forming source contact 207 and drain contact 211 .
  • TFT 200 a is intended to perform, when compared to prior art TFTs, with improved operating characteristics, and in particular with a higher threshold voltage, especially when fabricated with channel length dimensions of 1000 nm or less.
  • source-channel interfacial member 250 serves to create a repository of complimentary excess negative charge that functions to deplete the channel in at least the region of semiconductor layer 216 adjacent source contact 207 .
  • the distance between gate contact 203 and source contact 207 , through gate dielectric layer 214 , semiconductor layer 216 and source-channel interfacial member 250 is selected such that the electric field induced by a voltage applied to gate contact 203 will lower the blocking potential of the repository of complimentary excess negative charge introduced by source-channel interfacial member 250 to place the TFT, such as TFT 200 a , into an ‘ON’ state. In the absence of such an applied gate voltage, the blocking potential results in the TFT being in an ‘OFF’ state.
  • TFT 200 a can be fabricated with its various elements formed in ranges of thicknesses.
  • the primary limiting factor is that gate contact 203 must be within sufficient electrical proximity to source contact 207 such that the threshold voltage applied to gate 202 serves to effectively reduce the barrier to electron flow into semiconductor layer 216 induced by source-channel interfacial member 250 . Failure to induce a sufficient electric field reduces the ability to turn TFT 200 a on. This is very similar to the well known criteria for MOSFETs and the like, typically referred to as Ada ( ⁇ ) factor.
  • semiconductor layer 216 was formed with a thickness of about 20 nm (dielectric constant of about 8) and source-channel interfacial member 250 with a thickness of about 2 nm (dielectric constant of about 10) and dielectric layer 214 with a thickness of about 10 nm (dielectric constant of about 24).
  • semiconductor layer 216 was formed with a thickness of about 5 nm ( 17 dielectric constant)
  • source-channel interfacial member 250 formed was with a thickness of about 0.5 nm (dielectric constant of about 10)
  • dielectric layer 214 was formed with a thickness of about 5 nm (dielectric constant about 24).
  • each of semiconductor layer 216 , dielectric layer 214 and source-channel interfacial member 250 will be, to some extent, dependent upon properties of the materials selected and the fabrication techniques employed. However, in view of the disclosure herein, these specific selections will now be well within the capabilities of those of ordinary skill in the art,
  • FIG. 2 c illustrates a cross-sectional view of a TFT 200 c according to another embodiment of the present invention.
  • source-channel interfacial member 250 is not a continuous layer extending between source contact 207 and drain contact 211 and is instead only formed at each of source contact 207 and drain contact 211 .
  • source-channel interfacial member 250 can be formed by a catalytic growth of a metal that forms the source contact 207 and drain contact 211 .
  • source-channel interfacial member 250 consists of an oxide or a sulfide, or another element corresponding to group VI(A) of the periodic table, or the chalcogens.
  • FIG. 2 d illustrates a cross-sectional view of another TFT 200 d according to another embodiment of the present invention.
  • source-channel interfacial member 250 is formed only at source contact 207 and can be formed by catalytic growth of a metal that makes up source contact 207 .
  • the material making up drain contact 211 can have been selected such that it is “noble”, meaning that it does not interact readily with oxidizing agents.
  • Source-channel interfacial member 250 can consist of an oxide or a sulfide, or another element corresponding to group VI(A) of the periodic table, or the chalcogens.
  • TFT 200 c The presence or absence of source-channel interfacial member 250 on drain contact 211 does alter the electrical properties of TFT 200 c .
  • TFT 200 c the absence of source-channel interfacial member 250 on drain contact 211 raises the threshold voltage of TFT 200 c between approximately 0.1V to 2V, compared to TFT 200 a and TFT 200 c .
  • source-channel interfacial member 250 is formed by catalytic growth of an oxide or sulfide
  • the resulting formation of source-channel interfacial member 250 on drain contact 211 in addition to the formation of source-channel interfacial member 250 on source contact 207 can be readily tolerated and no additional processing is required to remove source-channel interfacial member 250 from drain contact 211 , unless it is desired to reduce the threshold voltage.
  • FIGS. 3 a through 3 d represent a TFT 300 in accordance with an embodiment of the present invention and its performance in various states of operation.
  • the substrate and insulation layer have been omitted from the Figures for clarity.
  • source-channel interfacial member 250 adjacent source contact 207 a structure which is functionally similar to a bipolar junction transistor (BJT) is introduced.
  • BJT bipolar junction transistor
  • the TFTs of the embodiments disclosed herein effectively combine a field-effect transistor (FET) architecture with a structure analogous to the emitter of a BJT at the source contact.
  • FET field-effect transistor
  • FIG. 3 a A schematic representation of a TFT 300 which has source-channel interfacial member 350 at each of a source contact 307 and a drain contact 311 , is illustrated schematically in FIG. 3 a.
  • FIG. 3 b shows a cross section through an instance of TFT 300 when TFT 300 is in the Forward Active state (wherein V DS >0 V GS >V Threshold ).
  • FIG. 3 c shows the cross section of FIG. 3 b wherein TFT 300 is in the OFF state (wherein V DS >0 V GS ⁇ V Threshold ) and
  • FIG. 3 d shows a cross section through an instance of TFT 300 when TFT 300 a is in the 0V state (wherein V DS >0 V GS ⁇ V Threshold )
  • TFT 300 is analogous to TFT 200 a of FIG. 2 a , and source contact 307 , source electrode 306 , drain contact 311 , drain electrode 310 , gate electrode 302 , gate contact 303 , dielectric layer 314 , source-channel interfacial member 350 and n-type semiconductor layer 316 are analogous to the respective elements described above with respect to TFT 200 a of FIG. 2 a.
  • source-channel interfacial member 350 extends between source contact 307 and drain contact 311 , thereby forming a structure resembling a gate limited junction field effect transistor (JFET), or accumulation MOSFET, with a BJT equivalent at source contact 307 and drain contact 311 .
  • JFET gate limited junction field effect transistor
  • FIG. 3 b illustrates the operation of TFT 300 in the Forward Active (or ‘ON’) state.
  • the Forward Active state occurs when the drain voltage (V DS ) is greater than 0V, and the gate voltage (V GS ) is greater than the threshold voltage (V Threshold ).
  • V DS drain voltage
  • V GS gate voltage
  • V Threshold threshold voltage
  • an accumulation layer 330 of electrons forms underneath gate contact 303 below dielectric layer 314 . In this state of operation, accumulation layer 330 allows for electron flow from source contact 307 to drain contact 311 .
  • FIG. 3 c illustrates TFT 300 in the ‘OFF’ state mode.
  • TFT 300 enters the ‘OFF’ state of operation when the gate voltage (V GS ) is below the threshold voltage (V Threshold ).
  • V GS gate voltage
  • V Threshold threshold voltage
  • a depletion region 335 is formed in semiconductor layer 316 below gate contact 303 so as to greatly reduce, or substantially eliminate, the flow of electrons between source contact 307 and drain contact 311 .
  • FIG. 3 d illustrates TFT 300 in a ‘0V’ state wherein no voltages are applied to TFT 300 .
  • V GS gate voltage
  • depletion region 335 is more prominent and close to both source contact 307 and drain contact 311 , thereby greatly reducing, or substantially eliminating, the flow of electrons between source contact 307 and drain contact 311 .
  • FIGS. 4 a through 4 d represent a TFT 400 in accordance with an embodiment of the present invention and its performance in various states of operation.
  • TFT 400 is analogous to TFT 200 c of FIG. 2 c
  • source contact 407 , drain contact 411 , gate contact 403 , dielectric layer 414 , source-channel interfacial member 450 and n-type semiconductor layer 416 are analogous to the respective elements described above with respect to TFT 200 c of FIG. 2 c.
  • FIG. 4 a is a schematic model of TFT 400 .
  • source-channel interfacial member 450 is formed on each of source contact 407 and drain contact 411 , but does not extend between the two. This effectively forms a device similar to a JFET with structures similar to BJTs at source contact 407 and drain contact 411 , analogous to FIG. 3 a.
  • FIG. 4 b illustrates TFT 400 in the Forward Active state (wherein V DS >0 V GS >V Threshold ). Similar to TFT 300 in the Forward Active state, an accumulation layer 430 of electrons forms underneath gate contact 403 , below dielectric layer 414 . In this state of operation, accumulation layer 430 allows for electron flow from source contact 406 to drain contact 410 .
  • FIG. 4 c illustrates TFT 400 in the ‘OFF’ state (wherein V DS >0 V GS ⁇ V Threshold ) wherein a depletion region 435 inhibits electron flow between source contact 407 and drain contact 411 .
  • FIG. 4 d illustrates TFT 400 in a 0V state. Similar to TFT 300 , when the gate voltage (V GS ) of TFT 400 is at or about 0V, depletion region 435 is more prominent and close to both source contact 407 and drain contact 411 , thereby greatly reducing, or substantially eliminating, the flow of electrons between source contact 407 and drain contact 411 . This places TFT 400 into an enhanced OFF-state, reducing or substantially eliminating parasitic channels in TFT 400 .
  • V GS gate voltage
  • the differences in the gradients and configurations (e.g. thickness) of the accumulation layer and depletion region between TFT 300 and TFT 400 result from the differences in the extent of the presence of the source-channel interfacial member in the devices. With a higher concentration and distributed presence of the source-channel interfacial member, better depletion layer control of the n-type semiconductor channel is attained.
  • FIGS. 5 a through 5 e represent a TFT 500 in accordance with an embodiment of the present invention and its performance in various states of operation.
  • TFT 500 is analogous to TFT 200 d of FIG. 2 d
  • source electrode 507 , source contact 506 , drain electrode 511 , drain contact 510 , gate electrode 503 , gate contact 502 , dielectric layer 514 , source-channel interfacial member 550 and n-type semiconductor layer 516 are analogous to the source electrode 208 , source contact 207 , drain electrode 212 , drain contact 211 , gate electrode 204 , gate contact 203 , dielectric layer 214 , source-channel interfacial member 250 and semiconductor layer 216 of FIG. 2 d.
  • FIG. 5 a is a schematic model of TFT 500 .
  • source-channel interfacial member 550 is adjacent to source contact 506 only and this effectively forms a JFET with a BJT at the source contact 506 .
  • FIG. 5 b illustrates TFT 500 in the Forward Active state
  • FIG. 5 c illustrates TFT 500 in the ‘OFF’ state
  • FIG. 5 d illustrates TFT 500 in the 0V state.
  • Accumulation layer 530 and depletion region 535 , 540 characteristics of TFT 500 are analogous to TFT 300 of FIG. 3 a and TFT 400 of FIG. 4 a , with depletion region 540 being an asymmetric version of the depletion region 435 of FIG. 4 d in the 0V stage.
  • FIG. 6 is a flow chart illustrating a method 600 of manufacturing a TFT according to an embodiment of the present invention.
  • Method 600 of FIG. 6 is discussed with reference to FIGS. 7 a through 7 n for a TFT 700 and to FIGS. 8 a through 8 d , for TFT 800 a and TFT 800 b , which illustrate examples of the various steps involved in the method.
  • form or “forming” are intended to encompass any suitable manner for manufacturing the structures recited in this disclosure.
  • “form” and “forming” can include processes such as: atomic layer deposition; chemical vapor deposition; plasma enhanced chemical vapor deposition, sputtering; ion implantation; oxidation; electrochemical deposition; molecular beam epitaxy; etc. The selection of specific appropriate processes is well within the purview of those of skill in the art.
  • Method 600 begins at step 605 where source contact 707 and drain contact 711 contact are formed on top of an insulation layer 718 , which is, in turn formed on top of a substrate 720 , as shown in FIG. 7 a .
  • FIG. 7 a illustrates a cross-sectional view of TFT 700 , taken through line B-B of FIG. 7 h which shows a corresponding top view.
  • insulation layer 718 can be formed from materials such as: silicon dioxide (SiO 2 ); silicon nitride (Si 3 N 4 ); aluminum oxide (Al 2 O 3 ); etc.
  • Substrate 720 can be any suitable substrate suitable for serving as the foundation for the construction of components and devices, such as transistors and integrated circuits, image sensors and displays and examples of which include, without limitation, silicon, flexible polymers and other plastics, ceramic materials, optical glass, metals, etc.
  • source contact 707 and drain contact 711 are formed by deposition via lithography process.
  • the methods of forming source contact 707 and drain contact 711 are not particularly limited and they can be formed through a variety of other processes as will be apparent to those of skill in the art.
  • source-channel interfacial member 750 is formed.
  • source-channel interfacial member 750 is formed on top of source contact 707 and drain contact 711 and extends over the area of insulation layer 718 between them.
  • Source-channel interfacial member 750 can be a p-type semiconductor formed by any suitable technique including, without limitation, deposition techniques, such as atomic layer deposition, sputtering or chemical vapor deposition.
  • source-channel interfacial member 750 can also be formed in other ways and reference is made to FIG. 8 a which illustrates a cross-sectional view, taken through line D-D of FIG. 8 c , of a TFT 800 , similar to that of FIG. 7 b , according to another embodiment of the present invention.
  • source-channel interfacial member 850 has been formed by a controlled oxidation of the underlying metal structure of both source contact 807 and drain contact 811 . As shown, this results in source-channel interfacial member 850 forming on source contact 807 and source-channel interfacial member 850 forming on drain contact 811 .
  • FIG. 8 b shows a cross-sectional view, taken along line E-E of FIG. 8 d , of a TFT 800 b according to another embodiment of the present invention.
  • drain contact 811 is formed of a noble material (i.e.—one which will not oxidize) and source-channel interfacial member 850 is formed by the controlled oxidation of the underlying metal structure of just source contact 807 . As shown, this results in source-channel interfacial member 850 on source contact 807 only.
  • FIG. 7 c shows a cross section, taken along line F-F of FIG. 7 j , after semiconductor layer 716 is formed across TFT 700 , including on top of source-channel interfacial member 750 .
  • a dielectric layer 714 is formed. As shown in the cross section of FIG. 7 d , taken through line G-G of FIG. 7 k , dielectric layer 714 is formed over the entire device, including on top of semiconductor layer 716 . Dielectric layer 714 is preferably formed of a material with a high dielectric constant, although other materials, such as SiO 2 or Si 3 N 4 , can also be employed.
  • gate contact 703 is formed. As shown in FIG. 7 e , which is a cross section taken through line H-H of FIG. 7 l , gate contact 703 is formed on dielectric layer 714 . In some cases, an optional gate tuning layer 722 can also be formed between dielectric layer 714 and gate contact 703 . In such cases, gate tuning layer 722 is formed first and gate contact 703 is formed on top of gate tuning layer 722 as shown in FIG. 7 e.
  • FIG. 7 f a cross section of TFT 700 taken along line I-I of FIG. 7 m , shows that gate contact 703 can be used as a mask to remove portions of dielectric layer 714 and underlying semiconductor layer 716 and source-channel interfacial layer 750 .
  • a layer of vertical TFTs and any related interconnections or other components in accordance with the present invention, can be formed and then a layer of insulating material, such as silicon dioxide, can be formed over them and that insulating layer can serve as the substrate and insulating layer for another set of TFTs which are formed on it. It is contemplated that several layers of TFTs can be formed in this manner significantly increasing circuit densities compared to the prior art.
  • FIG. 9 a shows a TFT 900 a that includes a gate 902 , a source 906 and a drain 910 .
  • Gate 902 includes a gate contact 903 and a gate electrode 904
  • source 906 includes a source contact 907 and a source electrode 908
  • drain 910 includes a drain contact 911 and a drain electrode 912 .
  • TFT 900 a also includes a dielectric layer 914 around gate 902 of TFT 900 a and includes a first insulation layer 918 formed over a substrate 920 , and a second insulation layer 925 .
  • TFT 900 a further includes an n-type semiconductor layer 916 and a source-channel interfacial member 950 . If desired, TFT 900 a can also include a gate tuning layer 922 as illustrated.
  • source 906 including source contact 907 and source electrode 908 , are at the bottom (with respect to the orientation of the Figure) of TFT 900 a , having been formed on top of first insulation layer 918 .
  • Second insulation layer 925 is formed over a portion of source contact 907 leaving a portion of source contact 907 exposed in the middle of TFT 900 a .
  • Drain contact 911 with drain electrode 912 formed on drain contact 911 , is formed on either side of the exposed portion of source contact 907 .
  • Source contact 907 is insulated from drain contact 911 by second insulation layer 925 .
  • source-channel interfacial member 950 is formed on the above-mentioned exposed portion of source contact 907 , the inner surface of second insulation layer 925 and on drain contact 911 .
  • Gate contact 903 is surrounded by (optional) gate tuning layer 922 , which is in turn surrounded by dielectric layer 914 .
  • Semiconductor layer 916 is formed between the dielectric layer 914 and source-channel interfacial member 950 .
  • FIG. 9 b illustrates a TFT 900 b which is another embodiment of the present invention that is analogous to TFT 900 a , but wherein the extent and location of source-channel interfacial member 950 is altered.
  • source-channel interfacial member 950 is formed as a layer over the entire upper surface of source contact 907 .
  • source-channel interfacial member 950 is absent from the inner surface of second insulation layer 925 and drain contact 911 in TFT 900 b .
  • semiconductor layer 916 is formed between dielectric layer 914 , the inner surface of second insulation layer 925 and drain contact 911 .
  • FIG. 9 c shows a cross-sectional view of a TFT 900 c according to another embodiment of the present invention. Similar to TFTs 990 a and 900 b of FIGS. 9 a and 9 c , TFT 900 c is a vertical implementation of a TFT in accordance with an embodiment of the present invention.
  • TFT 900 c differs from the above-described TFTs 900 a and 900 b in that the bottom contact of TFT 900 c is drain contact 911 . Conversely, the top contact of TFT 900 c is source contact 907 . As shown in FIG. 9 c , source-channel interfacial member 950 is formed around source contact 907 . Source-channel interfacial member 950 is isolated from drain contact 911 due to the presence of second insulation layer 925 and is separated from dielectric layer 914 by semiconductor layer 916 .
  • FIGS. 9 a , 9 b and 9 c show “symmetric” implementations of vertical TFTs in accordance with aspects of the present invention, it will be readily apparent to those of skill in the art that such symmetry is not required.
  • FIG. 9 d shows a non-symmetric implementation of a TFT 900 d wherein the right hand side (with respect to the orientation of the Figure) of TFT 900 b has been omitted.
  • FIG. 9 d shows a non-symmetric implementation of a TFT 900 d wherein the right hand side (with respect to the orientation of the Figure) of TFT 900 b has been omitted.
  • TFT 900 a , TFT 900 b , TFT 900 c and TFT 900 d function in manners similar to the other embodiments of the present invention disclosed herein.
  • TFTs 900 a , 900 b , 900 c and 900 d can be formed as vertical cylinders, rectangular parallelepipeds, hexagonal prisms, etc. and this variety of possible shapes allows the “footprint” of TFTs 900 a , 900 b , 900 c and 900 d to be selected to optimize the density at which TFTs 900 a , 900 b , 900 c and 900 d can be formed in a device. This provides several advantages, especially in applications such as DRAM memory wherein increasing memory cell density is an important goal.
  • TFTs 900 a , 900 b , and 900 c can be “stacked” to increase circuit element densities.
  • an array of TFTs 900 a , 900 b , or 900 c can be formed upon a substrate and/o insulator covering a lower layer of circuit elements (including TFTs 900 a , 900 b and 900 c ) and, in turn covered by a substrate and/or insulator and another array of TFTs 900 a , 900 b , or 900 c formed atop that substrate and/or insulator—resulting in true 3D integrated circuits being formed.
  • FIGS. 10 a and 10 b are a flowchart of a method 1000 of manufacturing a vertical TFT 1200 , similar to TFT 900 a discussed above.
  • Method 1000 of FIGS. 10 a and 10 b is discussed with reference to FIGS. 11 a through 11 v which illustrate the various steps involved in the method.
  • Method 1000 begins at step 1005 where source electrode 908 and source contact 907 are formed on first insulation layer 918 which is, in turn, formed on substrate 920 , as shown in FIG. 11 a .
  • FIG. 11 a is a cross section of FIG. 11 l , taken along line K-K.
  • Source contact 907 can be formed of copper, tungsten or any other material usable in the fabrication of a vertical transistor as will occur to those of skill in the art.
  • the material of source contact 907 is selected based on Work function and surface oxidation properties of the material in order to provide the desired effect of the injection of electrons into the accumulation layer during operation of TFT 1200 , as will now be apparent to those of skill in the art. It is also contemplated that source electrode 908 and source contact 907 can be one and the same element if desired.
  • a second insulation layer 925 is formed over source contact 907 , as shown in FIG. 11 b , which is a cross section taken along line L-L of FIG. 11 m . As can be seen, second insulation layer 925 is formed over the entire upper surface of source contact 907 . Second insulation layer 925 can be formed using any suitable technique as will occur to those of skill in the art, including spin coating of polymers, chemical vapor deposition of dielectrics, etc.
  • drain contact 911 is formed as shown in FIG. 11 c , which is a cross section taken along line M-M of FIG. 11 n . As shown, drain contact 911 is formed over the entire upper surface of second insulation layer 925 .
  • the undesired material of drain contact 911 is removed.
  • the undesired material can be removed in any suitable manner as will occur to those of skill in the art, such as by patterning and etching.
  • FIG. 11 d which is a cross section taken along line N-N of FIG. 11 o , shows the result of step 1020 . It will be apparent to those of skill in the art that, if desired, the undesired material of drain contact 911 can be removed such that drain contact 911 is formed in a geometric shape, such as a hexagon, that can permit an enhanced packaging density of TFTs 1200 .
  • undesired portions of second insulation layer 925 are removed down to source contact 907 , as shown in FIG. 11 e , which is a cross section taken along line O-O of FIG. 11 p .
  • the undesired portions of second insulation layer 925 are removed via an etching process, which is selected so that it stops on the underlying source contact 907 , although any other suitable method of removing the undesired portions of second insulation layer 925 can also be employed, as will occur to those of skill in the art.
  • a source-channel interfacial member 950 is formed on the result of step 1025 .
  • source-channel interfacial member 950 is formed over the entire upper surface of TFT 1200 at this point, including over drain contact 911 and over the exposed portion of source contact 907 .
  • Source-channel interfacial member 950 can be formed in a variety of manners and, in one embodiment, is deposited using atomic layer deposition techniques.
  • an n-type semiconductor layer 916 is formed over source-channel interfacial member 950 , as shown in FIG. 11 g , which is a cross section taken along line Q-Q of FIG. 11 r .
  • Semiconductor layer 916 can be formed in a variety of manners and, in one embodiment, is deposited using atomic layer deposition techniques.
  • dielectric layer 914 is formed as shown in FIG. 11 h , which is a cross section taken along line R-R of FIG. 11 s .
  • Dielectric layer 914 is formed over semiconductor layer 916 .
  • the selection of the material for dielectric layer 914 is not particularly limited and dielectric layer 914 can be any suitable material with a high dielectric constant as will be apparent to those of skill in the art.
  • gate tuning layer 922 can be formed over dielectric layer 914 , and gate contact 903 is formed over gate tuning layer 922 .
  • Gate tuning layer 922 and gate contact 903 can be formed in a variety of manners, as will be apparent to those of skill in the art, including via an atomic layer deposition technique. If gate tuning layer 922 is not present, gate contact 903 is formed on dielectric layer 914 directly.
  • FIG. 11 i is a cross section taken along line S-S of FIG. 11 t.
  • step 1050 unwanted material from the various formed layers is removed to expose the underlying layers/features as shown in FIG. 11 j , which is a cross section taken along line T-T of FIG. 11 u .
  • drain contact 911 Source-channel interfacial member 950 , semiconductor layer 916 , dielectric layer 914 , gate tuning layer 922 and gate contact 903 are appropriately exposed.
  • the method of removing unwanted material from the various layers is not particularly limited and can be achieved in a variety of manners as will be apparent to those of skill in the art, including mechanical polishing, wet chemical etching, dry chemical etching, atomic layer etching, etc.
  • drain electrode 912 and gate electrode 904 are formed.
  • drain electrode 912 and gate electrode 904 can be deposited and patterned by using a masking approach.
  • the method used to form drain electrode 912 and gate electrode 904 is not particularly limited and a variety of suitable methods will be apparent to those of skill in the art.
  • FIGS. 12 a and 12 b show a flow chart of a method 1100 of manufacturing or fabricating another embodiment of a TFT 1300 , similar to TFT 900 b discussed above, in accordance with the present invention. Method 1100 is described with reference to FIGS. 13 a through 13 v.
  • Method 1100 begins with a substrate 920 on which an insulation layer 918 has been formed.
  • source electrode 908 and source contact 907 are formed on insulation layer 918 , as shown in FIG. 13 a , which is a cross section taken along line BL-BL of FIG. 13 l .
  • source electrode 908 and source contact 907 can be the same component, if formed of the same material.
  • Step 1105 is analogous to step 1005 of FIG. 10
  • FIGS. 13 a and 13 l are analogous to FIGS. 11 a and 11 l , respectively.
  • p-type semiconductor member 950 is formed on source contact 907 .
  • source-channel interfacial member 950 is formed as a layer over the entire upper surface of source contact 907 .
  • Source-channel interfacial member 950 can be formed in a variety of manners and in some embodiments it is deposited using an atomic layer deposition technique, but the method of forming source-channel interfacial member 950 is not particularly limited and can, for example, be formed by catalyzing a metal surface of source contact 907 to form a suitable metal oxide or any other appropriate method as will be apparent to those of skill in the art.
  • a second insulation layer 925 is formed on source-channel interfacial member 950 as shown in FIG. 13 c , which is a cross section taken along line BN-BN of FIG. 13 n .
  • second insulation layer 925 is deposited using spin coating of polymers, but the method of forming second insulation layer 925 is not particularly limited and second insulation layer 925 can, for example, be deposited using chemical vapor deposition (“CVD”) of dielectrics or any other suitable method as will be apparent to those of skill in the art.
  • CVD chemical vapor deposition
  • drain contact 911 is formed. As shown in FIG. 13 d , which is a cross section taken along line BO-BO of FIG. 130 , drain contact 911 is formed on the entire upper surface of second insulation layer 925 . Again, the method of forming drain contact 911 is not particularly limited and suitable methods will be apparent to those of skill in the art.
  • drain contact 911 is removed from drain contact 911 , as shown in FIG. 13 e , which is a cross section taken along line BP-BP of FIG. 13 p .
  • the method of removing unwanted material from drain contact 911 is not particularly limited. Further, if desired the unwanted material can be removed by etching, or the like, so that drain contact 911 can be formed in a pattern, such as the illustrated hexagon pattern or a stripe pattern (not shown), etc., in order to improve packing density of the resulting TFT.
  • step 1130 unwanted material is removed from second insulation layer 925 , as shown in FIG. 13 f , which is a cross section taken along line BQ-BQ of FIG. 13 q . As shown, second insulation layer 925 is removed down to source-channel interfacial member 950 .
  • Steps 1135 to 1155 of method 1100 are analogous to steps 1035 to 1055 of method 1000 , described above.
  • step 1135 as shown in FIG. 13 g , which is a cross section taken along line BR-BR of FIG. 13 r , an n-type semiconductor layer 916 is formed over source-channel interfacial member 950 .
  • N-type semiconductor layer 205 can be formed in a variety of manners, as will be apparent to those of skill in the art, including by an atomic layer deposition technique.
  • a dielectric layer 914 is formed over semiconductor layer 916 . This is shown in FIG. 13 h which is a cross section taken along line BS-BS of FIG. 13 s . Again, dielectric layer 914 can be formed in a variety of suitable manners, as will be apparent to those of skill in the art.
  • gate contact 903 is formed over dielectric layer 914 , as shown in FIG. 13 i , which is a cross section taken along line BT-BT of FIG. 13 t .
  • an optional gate tuning layer 922 can be formed on dielectric layer 914 before forming gate contact 903 .
  • Gate tuning layer 922 and gate contact 903 can be formed by any suitable process, as will occur to those of skill in the art, such as by atomic layer deposition techniques.
  • TFT 1300 is processed to remove unwanted material to expose underlying layers and features as shown in FIG. 13 j , which is a cross section taken along line BU-BU of FIG. 13 u .
  • the material which is removed to expose the layers and features of FIG. 13 j can be removed in any suitable manner, such as by mechanical polishing of TFT 1300 .
  • the underlying layers become exposed and form a hexagonal pattern.
  • drain electrode 912 and gate electrode 904 are formed. As shown in FIG. 13 k , which is a cross section taken along line BV-BV of FIG. 13 v , if desired drain electrode 912 and gate electrode 904 can be patterned, via a masking process, in a hexagonal, striped or other pattern.
  • the present invention comprises a variety of embodiments of novel semiconductor devices.
  • the present invention discloses TFTs with improved performance, even when fabricated at sub 200 nm channel dimensions.
  • Another contemplated advantage of semiconductor devices in accordance with embodiments of the present invention is their ability to be manufactured in Back End of Line (“BEOL”) semiconductor fabrication processes.
  • BEOL Back End of Line
  • FEOL Front End of Line
  • BEOL Back End of Line
  • IGZO Indium Gallium Zinc Oxide
  • TFTs in accordance with embodiments of the present invention can also be fabricated with techniques and processes which will not damage previously fabricated FEOL devices or structures but such TFTs have been shown to perform well, even at semiconductor/channel lengths of less than 200 nm, and to not be damaged by other BEOL processes.
  • TFTs in accordance with embodiments of the present invention employ six basic fabrication processes: Source Formation; Drain Formation; Gate Formation; Semiconductor Formation; Dielectric/Insulator Formation; and Source-Channel Interfacial Member Formation—each of which typically can be achieved in several possible ways. Selection of one or more appropriate alternatives for each of these fabrication processes, for use to fabricate BEOL TFTs or TFTs created in FEOL or alternative processes, is within the normal skills of those of skill in the art.
  • Source formation, Drain Formation and Gate formation will be achieved by sputtering and patterning; Semiconductor layer formation will be achieved by atomic layer deposition; Dielectric/Insulator formation will be achieved by atomic layer deposition; and Source-Channel Interfacial Member formation can be achieved by oxidation of the source contact (if the material is an oxidizable metal) or by sputtering a degeneratively doped monoatomic semiconductor layer, such as Germanium or Silicon.
  • Source-Channel Interfacial Member formation can be achieved by oxidation of the source contact (if the material is an oxidizable metal) or by sputtering a degeneratively doped monoatomic semiconductor layer, such as Germanium or Silicon.
  • the present invention provides novel thin film semiconductor switching devices which have good performance, even when manufactured with semiconductor/channel lengths of less than 1000 nm, and in particular with semiconductor/channel lengths of less than 200 nm. Manufacturing techniques and methods for the novel devices are also taught and these techniques and methods also allow the novel devices to be manufactured as BEOL devices.

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023285936A1 (en) 2021-07-13 2023-01-19 Zinite Corporation Thin film semiconductor switching device
EP4640026A1 (en) * 2022-12-23 2025-10-29 Zinite Corporation Thin film transistor
WO2024165987A1 (en) * 2023-02-09 2024-08-15 Zinite Corporation Passivation elements of a thin film transistor
CN121175800A (zh) * 2023-04-06 2025-12-19 任耐特公司 等温晶体管结构
CN121014276A (zh) 2023-04-18 2025-11-25 任耐特公司 氮化铪粘附层
TW202505981A (zh) * 2023-07-26 2025-02-01 日商半導體能源研究所股份有限公司 氧化物半導體層、氧化物半導體層的製造方法、半導體裝置及半導體裝置的製造方法
US20250204015A1 (en) * 2023-12-14 2025-06-19 Zinite Corporation Gate stack for field effect transistors
WO2025163584A1 (en) * 2024-02-01 2025-08-07 Zinite Corporation Thin-film transistors with gate-source capacitance tuning
WO2026022653A1 (en) * 2024-07-23 2026-01-29 Zinite Corporation Stackable and self-aligned tft structures
US20260032965A1 (en) * 2024-07-25 2026-01-29 Zinite Corporation Thin-film transistors and related methods of manufacture with metal nitride source/drain

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501094B1 (en) * 1997-06-11 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a bottom gate type thin film transistor
US20100301340A1 (en) * 2009-06-01 2010-12-02 Ishiang Shih Thin film transistors and arrays
US20130187164A1 (en) * 2012-01-20 2013-07-25 Sony Corporation Thin-film transistor, method of manufacturing the same, display unit, and electronic apparatus
US20130320339A1 (en) * 2011-02-28 2013-12-05 Panasonic Liquid Crystal Display Co., Ltd. Thin-film semiconductor device and method for manufacturing the same
US9685484B1 (en) * 2016-07-20 2017-06-20 Sandisk Technologies Llc Reversible resistivity memory with crystalline silicon bit line
US20200098930A1 (en) * 2018-09-25 2020-03-26 Van H. Le Contact electrodes for vertical thin-film transistors
US11264512B2 (en) * 2018-06-29 2022-03-01 Intel Corporation Thin film transistors having U-shaped features

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603192B2 (en) 1999-07-30 2003-08-05 Stmicroelectronics, Inc. Scratch resistance improvement by filling metal gaps
US20070194450A1 (en) * 2006-02-21 2007-08-23 Tyberg Christy S BEOL compatible FET structure
KR101513601B1 (ko) * 2008-03-07 2015-04-21 삼성전자주식회사 트랜지스터
KR101461127B1 (ko) * 2008-05-13 2014-11-14 삼성디스플레이 주식회사 반도체 장치 및 이의 제조 방법
KR100963027B1 (ko) 2008-06-30 2010-06-10 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
US9082857B2 (en) * 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
KR101525801B1 (ko) 2008-11-14 2015-06-08 삼성디스플레이 주식회사 어레이 기판 및 그 제조 방법
TWI372457B (en) * 2009-03-20 2012-09-11 Ind Tech Res Inst Esd structure for 3d ic tsv device
WO2011027656A1 (en) 2009-09-04 2011-03-10 Semiconductor Energy Laboratory Co., Ltd. Transistor and display device
KR102220606B1 (ko) 2009-11-06 2021-03-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
KR20110074355A (ko) * 2009-12-24 2011-06-30 삼성전자주식회사 트랜지스터
US8809861B2 (en) 2010-12-29 2014-08-19 Stmicroelectronics Pte Ltd. Thin film metal-dielectric-metal transistor
KR102072244B1 (ko) * 2011-11-30 2020-01-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
JP2013149827A (ja) * 2012-01-20 2013-08-01 Sony Corp 薄膜トランジスタおよびその製造方法、並びに表示装置および電子機器
JP5390654B2 (ja) * 2012-03-08 2014-01-15 株式会社東芝 半導体装置の製造方法
US20160315196A1 (en) * 2012-04-13 2016-10-27 The Governors Of The University Of Alberta Buried source schottky barrier thin film transistor and method of manufacture
JP5972065B2 (ja) 2012-06-20 2016-08-17 富士フイルム株式会社 薄膜トランジスタの製造方法
US9685559B2 (en) * 2012-12-21 2017-06-20 The Regents Of The University Of California Vertically stacked heterostructures including graphene
US8933564B2 (en) * 2012-12-21 2015-01-13 Intel Corporation Landing structure for through-silicon via
JP2014229713A (ja) * 2013-05-21 2014-12-08 独立行政法人産業技術総合研究所 半導体装置および半導体装置の製造方法
CA2932446A1 (en) * 2013-12-04 2015-06-11 The Governors Of The University Of Alberta Buried source schottky barrier thin film transistor and method of manufacture
JP2016146422A (ja) * 2015-02-09 2016-08-12 株式会社ジャパンディスプレイ 表示装置
WO2016128859A1 (en) * 2015-02-11 2016-08-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9761732B2 (en) * 2015-02-25 2017-09-12 Snaptrack Inc. Tunnel thin film transistor with hetero-junction structure
US10217819B2 (en) * 2015-05-20 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor device including metal-2 dimensional material-semiconductor contact
DE112015006960T5 (de) * 2015-09-25 2018-06-07 Intel Corporation Lang-kanal-mos-transistoren für kriechverlustarme anwendungen auf einem kurz-kanal-cmos-chip
WO2017061050A1 (ja) * 2015-10-09 2017-04-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
US9954101B2 (en) * 2016-06-15 2018-04-24 International Business Machines Corporation Precise junction placement in vertical semiconductor devices using etch stop layers
CN109643742B (zh) * 2016-08-26 2024-09-27 英特尔公司 集成电路器件结构和双侧制造技术
KR102603300B1 (ko) * 2016-12-30 2023-11-15 엘지디스플레이 주식회사 박막 트랜지스터, 그의 제조방법, 및 그를 포함하는 유기발광 표시장치
JP7086488B2 (ja) 2017-03-21 2022-06-20 日本化薬株式会社 有機半導体組成物、有機薄膜及び有機薄膜トランジスタ
CN111052395A (zh) * 2017-08-31 2020-04-21 美光科技公司 半导体装置、晶体管以及用于接触金属氧化物半导体装置的相关方法
US11227953B2 (en) 2017-11-29 2022-01-18 Japan Science And Technology Agency Tunneling field effect transistor
CN108109996B (zh) * 2017-12-15 2021-06-22 西安科锐盛创新科技有限公司 基于二极管的集成电路抗静电转接板及其制备方法
CN108091624B (zh) * 2017-12-15 2020-12-22 浙江清华柔性电子技术研究院 用于系统级封装的硅通孔转接板
GB2571351A (en) * 2018-02-27 2019-08-28 Univ Manchester Device and method
WO2020043089A1 (en) * 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Through-silicon via (tsv) fault-tolerant circuit, method for tsv fault-tolerance and integrated circuit (ic)
US20200083259A1 (en) 2018-09-11 2020-03-12 HKC Corporation Limited Array substrate, method for fabricating array substrate, and display
US11255902B2 (en) * 2018-09-21 2022-02-22 Micron Technology, Inc. Apparatuses for selective TSV block testing
US11335789B2 (en) * 2018-09-26 2022-05-17 Intel Corporation Channel structures for thin-film transistors
US11417770B2 (en) * 2018-09-26 2022-08-16 Intel Corporation Vertical thin-film transistors between metal layers
KR102718050B1 (ko) * 2018-10-25 2024-10-15 엘지디스플레이 주식회사 트랜지스터 및 전자장치
US20200167658A1 (en) 2018-11-24 2020-05-28 Jessica Du System of Portable Real Time Neurofeedback Training
GB201819570D0 (en) * 2018-11-30 2019-01-16 Univ Surrey Multiple-gate transistor
US10818324B2 (en) * 2018-12-18 2020-10-27 Micron Technology, Inc. Memory array decoding and interconnects
US11659722B2 (en) * 2018-12-19 2023-05-23 Intel Corporation Thin-film-transistor based complementary metal-oxide-semiconductor (CMOS) circuit
JP7655853B2 (ja) * 2019-02-11 2025-04-02 サンライズ メモリー コーポレイション 垂直型薄膜トランジスタ、及び、垂直型薄膜トランジスタの、３次元メモリアレイのためのビット線コネクタとしての応用メモリ回路方法
KR102711918B1 (ko) * 2019-12-27 2024-09-27 엘지디스플레이 주식회사 박막 트랜지스터, 그 제조방법 및 이를 포함하는 표시장치
DE102021104070A1 (de) 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterchip
WO2023285936A1 (en) 2021-07-13 2023-01-19 Zinite Corporation Thin film semiconductor switching device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501094B1 (en) * 1997-06-11 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a bottom gate type thin film transistor
US20100301340A1 (en) * 2009-06-01 2010-12-02 Ishiang Shih Thin film transistors and arrays
US20130320339A1 (en) * 2011-02-28 2013-12-05 Panasonic Liquid Crystal Display Co., Ltd. Thin-film semiconductor device and method for manufacturing the same
US20130187164A1 (en) * 2012-01-20 2013-07-25 Sony Corporation Thin-film transistor, method of manufacturing the same, display unit, and electronic apparatus
US9685484B1 (en) * 2016-07-20 2017-06-20 Sandisk Technologies Llc Reversible resistivity memory with crystalline silicon bit line
US11264512B2 (en) * 2018-06-29 2022-03-01 Intel Corporation Thin film transistors having U-shaped features
US20200098930A1 (en) * 2018-09-25 2020-03-26 Van H. Le Contact electrodes for vertical thin-film transistors

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