GB2571351A

GB2571351A - Device and method

Info

Publication number: GB2571351A
Application number: GB1803169.0A
Authority: GB
Inventors: Song Aimin; Zhang Jiawei; wilson Joshua
Original assignee: University of Manchester
Current assignee: University of Manchester
Priority date: 2018-02-27
Filing date: 2018-02-27
Publication date: 2019-08-28
Also published as: GB201803169D0

Abstract

A source-gated transistor (SGT) 100 is described. The SGT 100 comprises a Schottky source contact 150 on an oxide semiconductor channel 140, which may be indium gallium zinc oxide (IGZO). The SGT 100 has an intrinsic gain of at least 500. The Schottky source contact 150 is deposited on an oxide semiconductor channel 140 in an atmosphere comprising oxygen.

Description

The present invention relates to source-gated transistors. Particularly, the present invention relates to source-gated transistors comprising Schottky source contacts on oxide semiconductor channels and to methods of forming Schottky source contacts on oxide semiconductor channels for such sourcegated transistors.

Background to the invention

Generally, a source-gated transistor (SGT) comprises a stack including a gate insulator layer, a semiconductor channel overlaying the gate insulator layer, a source contact overlaying at least a part of the semiconductor channel, a drain contact and a gate contact. The source contact, the gate contact and the drain contact are mutually spaced. The source contact extends across a source region of the semiconductor channel defining a Schottky potential barrier between the source contact and the source region of the semiconductor channel. The gate contact controls transport of carriers from the source contact to the source region of the semiconductor channel across the barrier when the source region is depleted.

Oxide semiconductors, particularly indium-gallium-zinc-oxide (IGZO), are now reaching the maturity required for thin-film electronic applications. However, application of standard oxide semiconductor TFTs for example in displays, is limited by their relatively low intrinsic gains, short-channel effects and negative bias illumination temperature stresses (NBITS).

Hence, there is a need to improve oxide semiconductor TFTs.

Summary of the Invention

It is one aim of the present invention, amongst others, to provide a source-gated transistor comprising a Schottky source contact on an oxide semiconductor channel which at least partially obviates or mitigates at least some of the disadvantages of the prior art, whether identified herein or elsewhere. For instance, it is an aim of embodiments of the invention to provide a source-gated transistor comprising a Schottky source contact on an oxide semiconductor channel that has an improved intrinsic gain, an improved short channel effect and/or an improved negative bias illumination temperature stress. For instance, it is an aim of embodiments of the invention to provide a method of forming a Schottky source contact upon an oxide semiconductor channel that improves an intrinsic gain, a short channel effect and/or a negative bias illumination temperature stress.

According to a first aspect, there is provided a source-gated transistor, SGT, comprising a Schottky source contact on an oxide semiconductor channel, the SGT having an intrinsic gain of at least 500.

According to the second aspect, there is provided an inverter, a logic gate, an integrated circuit, an analogue circuit or a display comprising a source-gated transistor according to the first aspect.

According to a third aspect, there is provided a method of forming a Schottky source contact on an oxide semiconductor channel for a source-gated transistor, SGT, the method comprising:

depositing the source contact on the oxide semiconductor channel in an atmosphere comprising oxygen.

Detailed Description of the Invention

According to the present invention there is provided a source-gated transistor, as set forth in the appended claims. Also provided is a method of forming a Schottky source contact on an oxide semiconductor channel for a source-gated transistor. Other features of the invention will be apparent from the dependent claims, and the description that follows.

Throughout this specification, the term “comprising” or “comprises” means including the component(s) specified but not to the exclusion of the presence of other components. The term “consisting essentially of’ or “consists essentially of’ means including the components specified but excluding other components except for materials present as impurities, unavoidable materials present as a result of processes used to provide the components, and components added for a purpose other than achieving the technical effect of the invention, such as colourants, and the like.

The term “consisting of” or “consists of’ means including the components specified but excluding other components.

Whenever appropriate, depending upon the context, the use of the term “comprises” or “comprising” may also be taken to include the meaning “consists essentially of” or “consisting essentially of’, and also may also be taken to include the meaning “consists of’ or “consisting of’.

The optional features set out herein may be used either individually or in combination with each other where appropriate and particularly in the combinations as set out in the accompanying claims. The optional features for each aspect or exemplary embodiment of the invention, as set out herein are also applicable to all other aspects or exemplary embodiments of the invention, where appropriate. In other words, the skilled person reading this specification should consider the optional features for each aspect or exemplary embodiment of the invention as interchangeable and combinable between different aspects and exemplary embodiments.

SGT comprising a Schottky source contact on an oxide semiconductor channel

In this way, since the SGT has a relatively high intrinsic gain of at least 500, the SGT is suitable for use as an inverter, for example, and for application in large-area displays, in logic gates and in analogue circuits, for example. Furthermore, the SGT may have an improved short channel effect and/or an improved negative bias illumination temperature stress, as described below in more detail.

In a classical model of a SGT comprising a Schottky source contact on a semiconductor channel at zero bias, a conduction band energy E_c in the semiconductor is a maximum (i.e. the source barrier height Φ_Β) at the interface between the Schottky source contact and the semiconductor channel. The conduction band energy E_c decreases away from the interface in the semiconductor channel. Generally, SGTs require source barrier heights Φ_Β of ~ 0.3 eV - 0.5 eV in order to deplete the semiconductor channel while still achieving sufficiently high current for application.

The classical model assumes that the Schottky source contact and the semiconductor are homogeneous. The inventors have determined that this classical model may not apply to Schottky source contacts on oxide semiconductor channels, due to heterogeneities (also known as inhomogeneities) therein. The heterogeneities may be nanoscale and may arise, for example, from compositional inhomogeneities in the oxide semiconductor and/or the source contact, oxygen depletion in regions of the oxide semiconductor such as proximal the interface, (poly)crystalline and/or amorphous variations and/or crystallographic work function dependence of the source contact.

In contrast, for a SGT having a source contact on an oxide semiconductor channel, a conduction band energy E_c in the oxide semiconductor may instead increase away from the interface between the source contact and the oxide semiconductor channel. In this way, an effective source barrier height Φ_Β may be exhibited in the oxide semiconductor channel at a height greater than the source barrier height Φ_Β at the interface. In a direction perpendicular to the interface between the Schottky source contact and the semiconductor channel, the conduction band minimum E_c of the oxide semiconductor channel may increase when a source region of lower barrier height is surrounded by source regions of higher barrier height. Thus, a saddle point SP in the conduction band minimum E_c may be formed. The saddle point SP offers the most favourable current path and the effective source barrier height Φ_Βis defined by the most favourable current paths. As a result of a plurality of inhomogeneities, for example at the nanoscale, there may be a corresponding plurality of such saddle points SP providing and/or contributing to the effective source barrier height Φ_Β. Particularly, the inventors have determined that a problem with the saddle point SP is its strong voltage dependence, leading to a voltage dependent barrier height. As a drain voltage V_D increases, the saddle point SP becomes lower and more current can pass over the barrier, as described below in more detail. This increase in current with drain voltage V_D degrades the intrinsic gain. That is, the heterogeneities may, at least in part, dominate behaviour of the SGT by providing regions having higher, as well as lower, source barrier heights. Particularly, as discussed below in more detail, the lower barrier regions provided at least in part by these barrier heterogeneities may be deterministic in controlling the behaviour of the SGT.

The inventors have determined that, in order for the source contact to behave as a Schottky source contact on the oxide semiconductor channel as desired, the effective source barrier height Φ_Β should be reduced towards, and preferably below, the source barrier height Φ_Β at the interface. The inventors have determined that this may be achieved by, at least in part, controlling a thickness of the oxide semiconductor channel (i.e. the oxide semiconductor channel thickness H) and/or the heterogeneities, so as to control behaviour of the SGT and/or dominance of the heterogeneities on the behaviour.

Preferably, a goal is to remove the saddle point SP so that the effective barrier height Φ_Β, and therefore the current, is no longer strongly dependent upon the applied voltage. Reducing the oxide semiconductor channel thickness H may move the saddle point SP closer to the interface between the oxide semiconductor channel and the source contact until the saddle point SP eventually disappears entirely.

Particularly, the inventors have determined, as described below in more detail, that the effective source barrier height Φ_Β may be reduced by controlling the saddle point SP in the oxide semiconductor channel. Controlling the saddle point SP may be, for example, by reducing the height of the saddle point SP and hence the effective source barrier height Φ_Β, by reducing a distance of the saddle point SP from the interface or even by eliminating the saddle point SP entirely. That is, reducing the effective source barrier height Φ_Β may not only be by reducing the height of the saddle point SP but may also be by moving its position within the oxide semiconductor channel.

The inventors have determined, as described below in more detail, that if the oxide semiconductor channel thickness H is too large, the height of the saddle point SP and/or the distance of the saddle point from the interface may be too large and hence the effective source barrier height Φ| too high for the Schottky source contact to behave as desired i.e. without a bias dependence of the barrier height, caused by the saddle point SP. Conversely, the inventors have determined, as described below in more detail, that if the oxide semiconductor channel thickness H is too small, an electric field in use becomes so large that tunnelling and other barrier lowering mechanisms additionally affect a saturation current of an output curve of the SGT.

Treatment of the oxide semiconductor channel may be typically carried out to increase a conductivity thereof, prior to deposition of the source contact thereon, for example by annealing or by argon plasma treatment. However, surface regions, or even a through thickness, of the oxide semiconductor channel may become depleted with respect to oxygen during the treatment, for example during the annealing. The inventors have determined, as described below in more detail, that this depletion of the oxide semiconductor channel with respect to oxygen may result in heterogeneities that adversely affect the Schottky source contact behaviour. The inventors have determined, as described below in more detail, that depositing the source contact on the oxide semiconductor channel in the presence of oxygen may result in beneficial treatment of the oxygen-depleted surface regions of the oxide semiconductor and/or formation of a beneficial interface layer including the oxygen, as described below in more detail.

Through the constructive use of barrier height inhomogeneities and the resulting thickness dependence of the barrier height at the source contact, the inventors have overcome the conventional problems associated with oxide semiconductor, for example IGZO, SGT fabrication. Particularly, the inventors have successfully fabricated oxide semiconductor, for example IGZO, SGTs having extremely high intrinsic gains, an unprecedented robustness to reduced channel length and excellent stability under NBITS.

These SGTs are suitable for application in displays such as large-area displays, in logic gates and in analogue circuits, for example. Furthermore, the low-voltage saturation of these SGTs significantly reduces power consumption, making them useful for battery-powered wearable devices, for example.

Generally, a conventional source-gated transistor (SGT) employs a Schottky contact at the source (i.e. a Schottky source contact) to modulate the drain current I_D, making the drain current I_Dindependent of the semiconductor channel.

In order to operate as a conventional SGT, there are three basic design rules:

(a) the gate contact must overlap with the Schottky source contact;

(b) the semiconductor channel must be sufficiently conductive to not limit the drain current I_D; and (c) the semiconductor channel must be thin enough to be fully depleted by the reverse biased source.

The conventional SGT structure has been applied to various semiconductor channel layers including amorphous Si:H, poly-Si, ZnO , ZnO nanosheets and ZnO nanowires. Thus far, conventional SGTs fabricated using oxide semiconductors show quite poor properties, which may be due to poor Schottky source contact and/or low channel conductivities.

Generally, SGTs require source barrier heights of ~ 0.3 - 0.5 eV in order to deplete the semiconductor while still achieving sufficiently high current for application. For oxide semiconductors, achieving uniform Schottky contacts with such low barrier heights may be difficult. Furthermore, barrier height inhomogeneities are typically prevalent in thin-film Schottky diodes fabricated with oxide semiconductors and have been shown to significantly degrade reverse bias J - V characteristics of these diodes. Thus far, all discussions in the literature of the operating mechanism of SGTs have assumed a homogeneous barrier at the source contact. As the operating mechanism of SGTs relies so heavily upon the behaviour of the reverse biased Schottky barrier at the source, it is important to obtain a keen understanding of the effects of barrier height variations.

Herein, oxide semiconductor, particularly IGZO, SGTs exhibiting extremely high-gain, unprecedented stability to NBITS and short-channel effects are described. Firstly, the inventors produced conductive IGZO channels by thermally annealing in an inert atmosphere. However, a Schottky junction formed on IGZO, or any other disordered semiconductor, may have an inhomogeneous barrier height. Barrier inhomogeneities lead to the formation of saddle points in the conduction band minimum, such that the saddle point serves as an effective barrier height with a strong bias dependence. To maximise the intrinsic gain, the saddle points should be removed and/or their effects lessened. The inventors have achieved this through two mechanisms:

1. from SGT simulations, it has been established that the saddle points can be removed by reducing the thickness of the semiconductor;

2. by controlling barrier inhomogeneities using sputtering power and the presence of oxygen during source contact deposition.

Through these two mechanisms, intrinsic gains consistently above 1,000 are demonstrated. Finally, it was demonstrated that these SGTs are impervious to the short-channel effect down to 800 nm and are extremely stable under NBITS.

For oxide semiconductors, oxygen deficiencies are expected to cause inhomogeneities in Schottky source contacts. However, a method of fabrication described herein is applicable to all oxide semiconductors. Moreover, simulations of the SGTs having an inhomogeneous Schottky source contact offer a deeper understanding of SGT behaviour that will be of use in other disordered semiconductor systems, for example organics. The methods described herein are also compatible with complementary metal oxide circuits. Indeed, the use of Pt, for example, as a Schottky source contact enables use of single-step Schottky source contact deposition for both n-type and p-type transistors. While a current in SGTs may be relatively lower than standard TFTs, simulations suggest that the current produced by an oxide semiconductor, for example IGZO, SGT may be compatible with AMOLED displays, for example.

The inventors have determined a new design rule for these oxide semiconductor channel SGTs: in order for the source contact to behave as a Schottky source contact on the oxide semiconductor channel that is not strongly affected by the drain bias voltage (i.e. as desired), the effective source barrier height Φ_Β should be reduced towards, and preferably below, the source barrier height Φ_Β8ί the interface. The inventors have determined that this may be achieved by, at least in part, controlling a thickness of the oxide semiconductor channel (i.e. the oxide semiconductor channel thickness H) and/or the heterogeneities, so as to control behaviour of the SGT and/or dominance of the heterogeneities on the behaviour. In other words, for inhomogeneous barriers, the thickness of the oxide semiconductor channel (i.e. the oxide semiconductor channel thickness H) should be reduced such that the saddle point SP is removed or sufficiently close to the interface between the Schottky source contact and the oxide semiconductor channel, without being so thin as to induced a high enough electric field as to reduce the gain or deplete the oxide semiconductor channel of electrons so as to make the operating voltages impractically large. Using this new design rule, the inventors have successfully fabricated oxide semiconductor, for example IGZO, SGTs with ultra-high intrinsic gains. This result owes much to a detailed understanding of disorder at the interface between the Schottky source contact and the oxide semiconductor, which is useful understanding for other disordered materials. Furthermore, these SGTs also show excellent insensitivity to short-channel effects and NBTIS. Individually, these are excellent improvements upon the state of the art, but combined, they signify a major advance in SGT technology.

Intrinsic gain

As described in more detail below, the intrinsic gain A_v of a SGT may be considered to be a figure of merit thereof. The SGT has the intrinsic gain of at least 500. In one example, the intrinsic gain is preferably at least 1,000, more preferably at least 2,000, most preferably at least 3,000. In one example, the intrinsic gain is at most 50,000, preferably at most 20,000, more preferably at most 10,000.

NBITS

Negative Bias Illumination Temperature Stress (NBITS) may cause the threshold voltage of conventional SGTs to shift negatively during use. In one example, a change in an on voltage V_0N of the SGT after illumination for 30 minutes, preferably 45 minutes by a white LED, at approximately 2000 lx, at a spacing of 3 cm from the SGT, at a bias voltage of-20 V, at a gate voltage of 20 V and at 80 °C is at most 10%, preferably at most 5%, more preferably at most 1 %.

Short channel effect

Short channel effects may cause a problem for device scaling, due to the source contact being shielded from the drain contact. In one example, the SGT exhibits flat saturation up to a drain voltage V_D of 20 V at down to a channel length L_CH of 2 pm, preferably 1 pm, more preferably 0.8 pm.

Effective barrier height

In one example, an effective barrier height of the Schottky source contact is substantially independent of a drain voltage V_D of the SGT, in use. In this way, saddle points SP are reduced and/or removed. By substantially independent, it should be understood that other factors, such as image force lowering, may still provide a dependence of the drain voltage V_D but are not significant, in use.

In one example, a maximum potential of a conduction band minimum (i.e. a saddle point) of the oxide semiconductor channel at zero bias is within 10 nm, preferable within 5 nm, more preferably within 3 nm of an interface between the Schottky source contact and the oxide semiconductor channel. In this way, saddle points SP are reduced and/or removed.

In one example, the oxide semiconductor channel has a thickness H sufficiently small such that a maximum potential of a conduction band minimum (i.e. a saddle point) of the oxide semiconductor channel at zero bias is within 10 nm, preferable within 5 nm, more preferably within 3 nm of an interface between the Schottky source contact and the oxide semiconductor channel. This is particularly the case when the oxide semiconductor channel comprises and/or is formed from IGZO.

In one example, a conduction band of the oxide semiconductor channel at zero bias decreases, for example monotonically, away from an interface between the Schottky source contact and the oxide semiconductor channel. In this way, saddle points SP are reduced and/or removed.

Oxide semiconductor

It should be understood that the oxide semiconductor channel comprises and/or is formed from the oxide semiconductor and has a sufficiently high conductivity when the transistor is turned on. so that the source contact region of the transistor largely determines the transistor current.

In one example, the oxide semiconductor comprises and/or is an amorphous oxide semiconductor. In one example, the oxide semiconductor comprises and/or is a crystalline oxide semiconductor. In one example, the oxide semiconductor comprises and/or is an n-type oxide semiconductor. In one example, the oxide semiconductor comprises and/or is a p-type oxide semiconductor.

In one example, the oxide semiconductor comprises and/or is a ZnO-based oxide semiconductor, preferably an amorphous ZnO-based oxide semiconductor. In one example, the ZnO-based oxide semiconductor includes at least one selected from the group consisting of hafnium (Hf), yttrium (Y), tantalum (Ta), zirconium (Zr), titanium (Ti), copper (Cu), nickel (Ni), chromium (Cr), indium (In), gallium (Ga), aluminum (Al), tin (Sn), and magnesium (Mg).

In one example, the oxide semiconductor comprises and/or is ZnO, ZnGaO, ZnSnO, ln₂O₃, InSnO, InZnO, InGaO, InGaZnO, InHfZnO, InSiZnO, InZrZnO, InSnZnO, InGaSnO, SnO_2] AlZnO, AlZnSnO and/or ZrZnSnO. In one example, the oxide semiconductor comprises and/or is crystalline, for example polycrystalline, ZnO, crystalline, for example polycrystalline, ZnGaO, crystalline, for example polycrystalline, ZnSnO, crystalline, for example polycrystalline, ln₂O₃, crystalline, for example polycrystalline, InSnO, crystalline, for example polycrystalline, InZnO, crystalline, for example polycrystalline, InGaO, crystalline, for example polycrystalline, InGaZnO, crystalline, for example polycrystalline, InHfZnO, crystalline, for example polycrystalline, InSiZnO, crystalline, for example polycrystalline, InZrZnO, crystalline, for example polycrystalline, InSnZnO, crystalline, for example polycrystalline, InGaSnO, crystalline, for example polycrystalline, SnO₂, crystalline, for example polycrystalline, AlZnO, crystalline, for example polycrystalline, AlZnSnO, and/or crystalline, for example polycrystalline, ZrZnSnO. In one example, the oxide semiconductor comprises and/or is amorphous ZnO, amorphous ZnGaO, amorphous ZnSnO, amorphous ln₂O₃, amorphous InSnO, amorphous InZnO, amorphous InGaO, amorphous InGaZnO, amorphous InHfZnO, amorphous InSiZnO, amorphous InZrZnO, amorphous InSnZnO, amorphous InGaSnO, amorphous SnO₂, amorphous AlZnO, amorphous AlZnSnO, and/or amorphous ZrZnSnO.

In one preferred example, the oxide semiconductor is InGaZnO (IGZO). The oxide semiconductor may be a(ln₂O₃).b(Ga₂O₃).c(ZnO). More preferably, the oxide semiconductor is amorphous InGaZnO (IGZO). The oxide semiconductor may be amorphous a(ln₂O₃).b(Ga₂O₃).c(ZnO). In one example, a, b, and c are real numbers where a > 0, b > 0, and/or c > 0. In one example, a, b, and c are real numbers where a > 1, b > 1, and/or 0 < c < 1. In one example, a = 1, b = 1 and c = 2.

In one example, the oxide semiconductor channel is treated, for example by annealing and/or by plasma treatment, before deposition of the Schottky source contact thereon, as described below in more detail.

In one example, the oxide semiconductor comprises an oxygen-depleted region. In one example, the oxide semiconductor comprises an oxygen-depleted region proximal to and/or at an interface between the oxide semiconductor channel and the Schottky source contact. In one example, the oxygendepleted region is within 5 nm, preferably within 3 nm of the interface. In one example, the oxygendepleted region is formed during annealing prior to deposition of the Schottky source contact.

Preferably, the oxide semiconductor is IGZO, more preferably amorphous IGZO

Oxide semiconductor channel thickness H

If the oxide semiconductor channel thickness H is too large, the height of the saddle point SP and/or the distance of the saddle point from the interface may be too large and hence the effective source barrier height Φ| too high for the desired Schottky source contact behaviour i.e. voltage independence. Conversely, the inventors have determined, as described below in more detail, that if the oxide semiconductor channel thickness H is too small, an electric field in use becomes so large that tunnelling and other barrier lowering mechanisms additionally affect a saturation current of an output curve of the SGT.

In one example, the oxide semiconductor channel has a thickness H in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nm to 30 nm, for example 20 nm or 25 nm. It should be understood that the thickness H of the oxide semiconductor channel is measured in a direction orthogonal to a plane of the interface between the oxide semiconductor channel and the Schottky source contact.

Schottky source contact

In one example, the Schottky source contact comprises and/or is formed of a material, for example a metal, an alloy, a non-metal, having a work function of at least 4.5 eV, preferably at least 5 eV (Table 1). In one example, the Schottky source contact comprises and/or is formed of Pt, Pd, Ni, Au and/or ITO.

In one example, the Schottky source contact is deposited on the oxide semiconductor channel by evaporation and/or by sputtering in the presence of oxygen, for example in an atmosphere comprising oxygen.

In one example, the Schottky source contact has a thickness in a range from 10 nm to 250 nm, preferably in a range from 25 nm to 150 nm, more preferably in a range from 50 nm to 100 nm, for example 70 nm.

Element	Work function (eV)	Element	Work function (eV)	Element	Work function (eV)
Ag	4.26-4.74	Al	4.06-4.26	As	3.75
Au	5.10-5.47	B	-4.45	Ba	2.52-2.70
Be	4.98	Bi	4.31	C	~5
Ca	2.87	Cd	4.08	Ce	2.9
Co	5	Cr	4.5	Cs	1.95
Cu	4.53-5.10	Eu	2.5	Fe:	4.67-4.81
Ga	4.32	Gd	2.90	Hf	3.90
Hg	4.475	In	4.09	Ir	5.00-5.67
K	2.29	La	3.5	Li	2.9
Lu	-3.3	Mg	3.66	Mn	4.1
Mo	4.36-4.95	Na	2.36	Nb	3.95-4.87
Nd	3.2	Ni	5.04-5.35	Os	5.93
Pb	4.25	Pd	5.22-5.60	Pt	5.12-5.93
Rb	2.261	Re	4.72	Rh	4.98
Ru	4.71	Sb	4.55-4.70	Sc	3.5
Se	5.9	Si	4.60-4.85	Sm	2.7
Sn	4.42	Sr	-2.59	Ta	4.00-4.80
Tb	3.00	Te	4.95	Th	3.4
Ti	4.33	TI	-3.84	U	3.63-3.90
V	4.3	W	4.32-5.22	Y	3.1
Yb	2.60	Zn	3.63-4.9	Zr	4.05

Table 1: Work functions (eV) of various elements

Interface layer

In one example, the SGT comprises an interface layer arranged between the Schottky source contact and the oxide semiconductor channel. In one example, the interface layer comprises an oxide, for example AgO_x. In one example, the interface layer has a thickness in a range from 0.1 nm to 5 nm, preferably in a range from 0.5 nm to 2 nm.

Drain contact

In one example, the drain contact comprises and/or is formed of a material, for example a metal, an alloy, a non-metal, a conductive oxide In one example, the drain contact comprises and/or is formed 15 of a metal such as molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), chromium (Cr), gold (Au) or an alloy thereof and/or a conductive oxide such as an indium zinc oxide (IZO), indium tin oxide (ITO), or a mixture thereof.

Gate contact

In one example, the gate contact comprises and/or is formed of a material, for example a metal, an alloy, a non-metal, a conductive oxide In one example, the drain contact comprises and/or is formed of a metal such as molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), chromium (Cr), gold (Au) or an alloy thereof, a doped semiconductor such as doped silicon (Si), and/or a conductive oxide such as an indium zinc oxide (IZO), indium tin oxide (ITO), or a mixture thereof.

SGT stack

In one example, the SGT comprises a stack formed from a gate insulator layer, the oxide semiconductor channel overlaying the gate insulator layer, the Schottky source contact overlaying at least a first part of the oxide semiconductor channel, a gate contact overlaying at least a second part of the oxide semiconductor channel and a drain contact, wherein the source contact, the gate contact and the drain contact are mutually spaced.

Preferred example

In one example, the SGT comprises:

a stack formed from a gate insulator layer, wherein the gate insulator layer is SiO₂;

the oxide semiconductor channel overlaying the gate insulator layer, wherein the oxide semiconductor channel is annealed amorphous a(ln₂O₃).b(Ga₂O₃).c(ZnO), wherein a = 1, b = 1 and c = 2, wherein the oxide semiconductor comprises an oxygen-depleted region, formed during annealing prior to deposition of the source contact and wherein a thickness H of the oxide semiconductor channel is in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nmto 30 nm, for example 20 nm or 25 nm;

the Schottky source contact overlaying at least a first part of the oxide semiconductor channel, wherein the source contact is platinum formed by sputtering the platinum on the annealed oxide semiconductor in an atmosphere comprising oxygen;

a drain contact overlaying at least a second part of the oxide semiconductor channel, wherein the drain contact is platinum; and a gate contact underlaying at least a third part of the gate insulator layer, wherein the gate contact is doped silicon;

wherein the source contact, the gate contact and the drain contact are mutually spaced.

A preferred example provides a source-gated transistor, SGT, comprising a Schottky source contact on an oxide semiconductor channel, the SGT having an intrinsic gain of at least 500, preferably at least 1,000, more preferably at least 2,000, most preferably at least 3,000, wherein the oxide semiconductor channel is amorphous IGZO, specifically a(ln2O3).b(Ga2O3).c(ZnO), wherein a = 1, b = 1 and c = 2, and wherein a thickness H of the oxide semiconductor channel is in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nm to 30 nm, for example 16 nm to 28 nm such as 20 nm to 25 nm, for instance 20nm or 25nm;

and wherein the source contact is a Schottky source contact formed of a material, for example a metal, an alloy, a non-metal, having a work function of at least 4.5, preferably platinum. The SGT suitably has a maximum potential of a conduction band minimum of the oxide semiconductor channel at zero bias within 10 nm, preferably within 5 nm, more preferably within 3 nm of an interface between the Schottky source contact and the oxide semiconductor channel.

Method of forming a Schottky source contact on an oxide semiconductor channel

According to a third aspect, there is provided a method of forming a Schottky source contact on an oxide semiconductor channel for a source-gated transistor (SGT), the method comprising:

The Schottky source contact, the oxide semiconductor channel and the SGT may be according to the first aspect.

Depositing

In one example, depositing the source contact on the oxide semiconductor channel comprises evaporating the source contact on the oxide semiconductor channel.

In one example, depositing the source contact on the oxide semiconductor channel comprises sputtering the source contact on the oxide semiconductor channel at a sputtering power in a range from 0.4 W/cm² to 3 W/cm², preferably in a range from 0.6 W/cm² to 1.7 W/cm², for example 0.88 W/cm² or 1.32 W/cm². These sputtering powers correspond with a sputtering power in a range from 20 W to 150 W, preferably in a range from 30 W to 80 W, for example 40 W or 60W, respectively, for a 3 inch diameter sputtering target, as used herein.

In one example, depositing the source contact on the oxide semiconductor channel comprises sputtering the source contact on the oxide semiconductor channel to a thickness in a range from 10 nm to 250 nm, preferably in a range from 25 nm to 150 nm, more preferably in a range from 50 nm to 100 nm, for example 70 nm, at a sputtering power in a range from 0.4 W/cm² to 3 W/cm², preferably in a range from 0.6 W/cm² to 1.7 W/cm², for example 0.88 W/cm² or 1.32 W/cm².

Since higher sputtering powers may lead to faster source contact deposition rates, less oxygen may be incorporated at an interface formed between the oxide semiconductor channel and the source contact during sputtering. For example, for IGZO oxide semiconductors, more ln³⁺ may be reduced when higher sputtering powers are used, leading to a greater density of lower barrier regions (i.e. greater heterogeneity in barrier height) and a higher reverse current. The effect may be saturated at higher powers because a difference in oxygen content is reduced.

Atmosphere

In one example, the atmosphere comprising the oxygen is an inert gas, preferably argon, comprising the oxygen in a range from 0.1 % to 10 %, preferably in a range from 1 % to 5 %, for example 3% by partial pressure.

In one example, a pressure of the atmosphere is in a range from 1 x 10~⁵ mbar to 1 x 10~¹ mbar, preferably in a range from 1 χ 10’⁴ mbar to 1 χ 10’² mbar, for example 5 χ 10’³ mbar.

In one example, the atmosphere consists essentially of oxygen at a pressure in a range from 1 χ 10~⁸mbar to 1 χ 10’² mbar, preferably in a range from 1 χ 10’⁷ mbar to 1 χ 10’² mbar, more preferably in a range from 1 χ 10‘^s mbar to 1 χ 10‘³ mbar, for example 1 χ 10‘⁵ mbar or 1 χ 10‘⁴ mbar.

Annealing

In one example, the method comprises treating the oxide semiconductor channel prior to depositing the source contact thereon, to increase a conductivity of the oxide semiconductor channel, improve operation voltage and/or improve carrier mobility. Treating the oxide semiconductor channel may be by annealing (also known as thermal annealing) and/or by plasma treatment, for example argon plasma treatment.

In one example, the method comprises annealing the oxide semiconductor channel prior to depositing the source contact thereon.

In one example, the annealing is in an inert atmosphere, preferably nitrogen, at a temperature in a range from 200 °C to 400 °C, preferably in a range from 250 °C to 350 °C, for example 300 °C for at least 15 minutes, preferably for at least 30 minutes, more preferably for at least 60 minutes. While the annealing may increase a conductivity of the oxide semiconductor channel, improve operation voltage and/or improve carrier mobility, the annealing may also result in surface regions, and/or a through thickness, of the oxide semiconductor channel becoming depleted with respect to oxygen.

Oxide semiconductor channel

In one example, the oxide semiconductor channel is provided by sputtering, pulsed laser deposition, solution processing, combustion synthesis and/or spin coating. In one example, the oxide semiconductor channel is provided by sputtering.

Preferred example

In one example, the method comprises:

annealing the oxide semiconductor prior to depositing the source contact thereon; and depositing the source contact on the oxide semiconductor channel in an atmosphere comprising oxygen;

wherein the annealing is in an inert atmosphere, preferably nitrogen, at a temperature in a range from 200 °C to 400 °C, preferably in a range from 250 °C to 350 °C, for example 300 °C for at least 30 minutes, preferably about 60 minutes;

wherein the atmosphere comprising the oxygen is an inert gas, preferably argon, comprising the oxygen in a range from 0.1 % to 10 %, preferably in a range from 1 % to 5 %, for example 3% by partial pressure;

wherein the pressure of the atmosphere is in a range from 1 x 10~⁵ mbarto 1 x 10~¹ mbar, preferably in a range from 1 χ 10’⁴ mbarto 1 χ 10’² mbar, for example 5 χ 10’³ mbar;

wherein the oxide semiconductor channel is amorphous IGZO, preferably a(ln₂O₃).b(Ga₂O₃).c(ZnO), wherein a = 1, b = 1 and c = 2, and wherein a thickness H of the oxide semiconductor channel is in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nm to 30 nm, for example 16 nm to 28 nm such as 20 nm to 25 nm, for instance 20nm or 25nm;

and wherein the source contact is platinum.

Brief description of the drawings

For a better understanding of the invention, and to show how exemplary embodiments of the same may be brought into effect, reference will be made, by way of example only, to the accompanying diagrammatic Figures, in which:

Figure 1A schematically depicts a diode according to an exemplary embodiment;

Figure 1B schematically depicts a source-gated transistor according to an exemplary embodiment;

Figure 1C schematically depicts |/| - V curves for diodes according to exemplary embodiments;

Figure 1D schematically depicts I_D - V_G transfer curves for source-gated transistors according to exemplary embodiments;

Figure 2A schematically depicts I_D - V_G transfer curves for thin film transistors;

Figure 2B schematically depicts I_D - V_G transfer curves for source-gated transistors according to exemplary embodiments;

Figure 2C schematically depicts I_D - V_G transfer curves for source-gated transistors according to exemplary embodiments;

Figure 2D schematically depicts G ~ Fp output curves for a source-gated transistor according to an exemplary embodiment;

Figure 2E schematically depicts output curves for a source-gated transistor according to an exemplary embodiment;

Figure 2F schematically depicts output curves for a source-gated transistor according to an exemplary embodiment;

Figure 3A schematically depicts a model of a source-gated transistor according to an exemplary embodiment;

Figure 3B schematically depicts a model of a source-gated transistor according to an exemplary embodiment;

Figure 3C schematically depicts I_D - V_D output curves for a source-gated transistor according to an exemplary embodiment;

Figure 3D schematically depicts output curves for a source-gated transistor according to an exemplary embodiment;

Figure 3E schematically depicts current densities for the source-gated transistor of Figure 3D;

Figure 3F schematically depicts E_c - z depth profiles of conduction band minima for the sourcegated transistor of Figure 3D;

Figure 3G schematically depicts E_c - z depth profiles of conduction band minima for source-gated transistors according to exemplary embodiments;

Figure 4A schematically depicts intrinsic gains as functions of V_G for a source-gated transistor according to an exemplary embodiment;

Figure 4B schematically depicts intrinsic gains as functions of V_D for the source-gated transistor of Figure 4A;

Figure 4C schematically depicts intrinsic gains as functions of V_D for a source-gated transistor according to exemplary embodiments;

Figure 5A schematically depicts I_D - V_D output curves for a source-gated transistor according to an exemplary embodiment;

Figure 5B schematically depicts ~ Vd output curves for a source-gated transistor according to an exemplary embodiment;

Figure 5C schematically depicts I_D - V_D output curves for a source-gated transistor according to an exemplary embodiment;

Figure 5D schematically depicts Id ~ U) output curves for a source-gated transistor according to an exemplary embodiment;

Figure 6 schematically depicts I_D - V_G curves related to negative bias illumination stress for a sourcegated transistor according to an exemplary embodiment;

Figure 7A schematically depicts |/_D| - V_G transfer curves for models of source-gated transistors according to exemplary embodiments;

Figure 7B schematically depicts |/_D| - V_G transfer curves for models of source-gated transistors of

Figure 7A;

Figure 8 schematically depicts a method of forming a Schottky source contact on an oxidesemiconductor channel according to an exemplary embodiment; and

Figure 9 schematically depicts a method of forming a Schottky source contact on an oxidesemiconductorchannel according to an exemplary embodiment.

Detailed Description of the Drawings

Control of source barrier

Figure 1A schematically depicts a diode 10 according to an exemplary embodiment. Particularly, Figure 1A shows a cross-sectional view of a structure of the IGZO - Pt Schottky diode 10 on a Si/SiO₂substrate. The diode 10 comprises a stack formed from a gate contact 11, formed from Si, a dielectric layer 12, formed from SiO₂ thereupon, an ohmic contact layer 13, formed from Ti, overlaying the dielectric layer 12, an oxide semiconductor 14, formed from IGZO, overlaying the ohmic contact layer 13 and a Schottky source contact 15, formed from Pt, overlaying at least a part of the oxide semiconductor 14.

In more detail, the diodes 10 have an oxide semiconductor channel thickness H of 150 nm and the oxide semiconductor is IGZO. The diodes 10 have a Schottky source contact thickness h of 70 nm and the Schottky source contact is Pt (i.e. a metal). The diode 10 has a Ti ohmic contact having a thickness of 70 nm. All metal layers were deposited via radio-frequency sputtering, as described below.

Figure 1B schematically depicts a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 1B shows a cross-sectional view of a structure of the IGZO-Pt SGT 100 on a Si/SiO₂ substrate. The SGT 100 comprises a stack formed from a gate contact 110, formed from Si, a gate insulator layer 120 (also known as a dielectric layer), formed from SiO₂, thereupon, an oxide semiconductor channel 140, formed from IGZO, overlaying the gate insulator layer 120 of the substrate, a Schottky source contact 150, formed from Pt, overlaying a first part of the oxide semiconductor channel 140 and a drain contact 160, formed from Pt, overlaying a second part of the oxide semiconductor channel 140. The Schottky source contact 150 and the drain contact 160 are mutually spaced apart by a length L.The oxide semiconductor channel 140 has a thickness H i.e. an oxide semiconductor channel thickness H. The Schottky source contact 150 has a thickness h i.e. a Schottky source contact thickness h. In this example, the Si/SiO2 substrate forms the gate contact 110 (also known as a gate electrode) and the gate insulator layer 120. However, it is also possible to form the SGT 100 on an insulating substrate such as glass or plastic. In this case, the gate contact 110, for example a metal or a conductive oxide such as ITO, is deposited on the insulating substrate followed by deposition of the gate insulator layer thereon, from SiO₂ or HfO₂, for example.

In more detail, the SGTs 100 have an oxide semiconductor channel thickness H of 20 nm and the oxide semiconductor is IGZO. More generally, the SGTs 100 have an oxide semiconductor channel thickness H in a range from 5 nm to 100 nm. The SGTs 100 have a source length S of 600 pm and a channel length L of 60 pm. The SGTs 100 have a width W of 2 mm. The SGTs 100 have a Schottky source contact thickness h of 70 nm and the Schottky source contact is Pt (i.e. a metal). All metal layers were deposited via radio-frequency sputtering, as described below.

For SGT operation, the IGZO should be highly conductive so that the source region controls the current. This may be achieved through annealing the oxide semiconductor at 300 °C in an N₂atmosphere (i.e. thermal annealing). However, forming a Schottky contact on oxide semiconductors may be highly dependent on the oxygen content at the interface (i.e. the interface between the Schottky source contact and the oxide semiconductor channel). For Pt - IGZO interfaces, this may be attributable to a reduction of ln³⁺ to In⁰. Thus, annealing the oxide semiconductor in the N₂atmosphere can result in poor Schottky barriers, due to removal of O₂ from the oxide semiconductor channel.

Figure 1C schematically depicts |/| -V curves for diodes 10 according to exemplary embodiments. Particularly, Figure 1C shows |/| - V curves for Schottky diodes 10 at functions of power and O₂content during Pt deposition. The diodes 10 have an oxide semiconductor channel thickness H of 150 nm and the oxide semiconductor is IGZO. The diodes 10 have a Schottky source contact thickness h of 70 nm and the Schottky source contact is Pt (i.e. a metal). The diodes 10 have a Ti ohmic contact having a thickness h of 70 nm. The SGTs were formed, at least in part, by sputtering the Schottky source contact Pt in an absence of O₂ at a power of 60 W and in a 3% O₂/Ar atmosphere at respective powers of 40 W, 60 W and 100 W.

As shown in Figure 1C, annealing the oxide semiconductor in an absence of oxygen results in a IGZO-Pt contact that is effectively ohmic. To increase the oxygen content at the interface (i.e. the interface between the Schottky source contact and the oxide semiconductor channel), without adversely affecting conductivity of the IGZO channel (i.e. the oxide semiconductor channel), the Pt contacts are sputtered in a 3% O₂/Ar atmosphere after the thermal annealing. Figure 1C shows the |J |-V characteristics of the oxygen treated diodes. The reverse current of the diodes increases with the sputtering power of Pt. For example, when V = -1 V, the current in the 100 W diode is over two orders of magnitude larger than in the 40 W diode. Increasing the power above 100 W has limited affect on the current.

Figure 1D schematically depicts I_D - V_G transfer curves for source-gated transistors 100 according to exemplary embodiments. Particularly, Figure 1D shows I_D - V_G transfer curves for SGTs 100 as functions of power and O₂ content during Pt deposition. The SGTs 100 have an oxide semiconductor channel thickness H of 20 nm and the oxide semiconductor is IGZO. The SGTs 100 have a source length S of 600 qm and a channel length L of 60 qm. The SGTs 100 have a width W of 2 mm. The

SGTs 100 have a Schottky source contact thickness h of 70 nm and the Schottky source contact is Pt (i.e. a metal). The SGTs 100 were formed, at least in part, by sputtering the Schottky source contact Pt in an absence of O₂ at a power of 60 W and in a 3% O₂/Ar atmosphere at respective powers of 40 W, 60 Wand 100 W.

As shown in Figure 1D, similar results for the diodes 10 are observed in the SGT transfer curves for the SGTs 100. The on-currents of the SGTs 100, which is determined by the reverse biased Schottky source contact, is 6 V higher for the SGT in which the respective Pt source contact was sputtered at a power of 40 W in a 3% O₂/Ar atmosphere compared with the SGT in which the respective Pt source contact was sputtered at a power of 60 W in a 3% O₂/Ar atmosphere. That is, sputtering at the power of 60 W in the 3% O₂/Ar atmosphere is preferred compared with sputtering at the power of 60 W in the 3% O₂/Ar atmosphere since the current is higher and the on-voltage is closer to zero. At sputtering powers greater than 60 W, there is limited improvement in current and on-voltage.

Such a strong dependence of the reverse current may be associated with a presence of barrier height inhomogeneities. Since higher sputtering powers lead to faster Pt deposition rates, less oxygen may be incorporated at the Pt-IGZO interface during sputtering. Hence, more ln³⁺ may be reduced when higher sputtering powers are used, leading to a greater density of lower barrier regions and a higher reverse current. The effect is saturated at higher powers because the difference in oxygen content is reduced.

Thickness dependence of SGT behaviour

Fully-depleted inhomogeneous diodes may have a thickness dependent effective barrier height. By tuning (for example optimising) the oxide semiconductor channel thickness H of the SGTs 100, the effective barrier height for SGT operation may be optimised.

TFTs and SGTs 100 with oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm and 50 nm were fabricated using IGZO as the oxide semiconductor. The TFTs had Ti source-drain contacts deposited in Ar. The SGTs 100 had Pt Schottky source contacts 150 deposited by sputtering in an atmosphere of 3% O₂/Ar at a power of 60 W.

Figure 2A schematically depicts I_D - V_G transfer curves for thin film transistors. Particularly, Figure 2A shows I_D - V_G transfer curves for the TFTs having oxide semiconductor channel thicknesses H of 20 nm, 30 nm and 50 nm for V_D = 1V.

Figure 2A shows that the TFTs showed no discernible dependence on the oxide semiconductor channel thickness H. All the TFTs had a mobility of approximately 7 cm² V‘¹s‘¹ and V_T of approximately 2 V.

Figure 2B schematically depicts I_D - V_G transfer curves for source-gated transistors 100 according to exemplary embodiments. Particularly, Figure 2B shows I_D - V_G transfer curves for the SGTs 100 having oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm and 50 nm for V_D = 1V.

Figure 2C schematically depicts I_D - V_G transfer curves for source-gated transistors 100 according to exemplary embodiments. Particularly, Figure 2C shows I_D - V_G transfer curves for the SGTs 100 having oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm and 50 nm for V_D = 10 V.

In contrast to the TFTs as shown in Figure 2A, Figure 2B and Figure 2C show that the SGTs 100 exhibit two strong dependences on the oxide semiconductor channel thickness H.

Firstly, when Vp = 10V (Figure 2C) the on-voltage V_0N increases from -18 V when the oxide semiconductor channel thickness H is 50 nm to 0 V when the oxide semiconductor channel thickness H is 20 nm. The large increase may be attributed to an ease with which the oxide semiconductor channel 140 is depleted by the Schottky source contact 150 in the SGTs 100 having smaller oxide semiconductor channel thicknesses H, thus requiring a greater V_G accumulate charge.

Secondly, and counterintuitively, the SGTs 100 having smaller oxide semiconductor channel thicknesses H have greater respective on-currents, particularly at lower drain voltage, which is not adequately explained by the current SGT literature.

Figure 2D schematically depicts Id ~ Vd output curves for a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 2D shows I_D - V_D output curves for the SGT 100 having an oxide semiconductor channel thickness H of 50 nm and the oxide semiconductor is IGZO for different V_G from 10 V to 40 V in 2 V steps.

Figure 2E schematically depicts Id ~ Vd output curves for a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 2E shows Id ~ Vd output curves for the SGT 100 having an oxide semiconductor channel thickness H of 30 nm and the oxide semiconductor is IGZO for different V_G from 10 V to 40 V in 2 V steps.

Figure 2F schematically depicts Id ~ Vd output curves for a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 2F shows Id ~ Vd output curves for the SGT 100 having an oxide semiconductor channel thickness H of 20 nm and the oxide semiconductor is IGZO for different V_G from 10 V to 40 V in 2 V steps.

From the I_D - V_D output curves for the SGTs 100 of Figures 2D, 2E and 2F, the saturation voltage decreases as the oxide semiconductor channel thickness H decreases. This is consistent with a twodielectric model due to Shannon and Gerstner in which:

^Dsatl

c_G(y_G-v_T) _t „ - _Cs + c_G ^+K

where V_Dsatl is the voltage required to fully deplete the oxide semiconductor channel 140 under the Schottky source contact 150 edge (also known as the source saturation voltage), V_T is the threshold voltage of the oxide semiconductor channel, C_s and C_G are the capacitances per unit area of the oxide semiconductor channel 140 and the gate insulator 120, respectively, and K is a constant. Typically, V_Dsatl is much lower than the drain saturation V_Dsat2 for conventional TFTs, in which:

Two unexpected trends are also shown.

Firstly, flatter saturation for SGTs 100 having smaller oxide semiconductor channel thicknesses H, for example 30 nm and 50 nm.

Secondly, more linear I_D - V_D output curves prior to saturation for SGTs 100 having smaller oxide semiconductor channel thicknesses H, for example 30 nm and 50 nm. The V_D dependence of saturation current is particularly important for achieving high intrinsic gain, as described below in more detail.

Effects of barrier inhomogeneities

A behaviour of SGTs may be described using a distributed network of diodes and resistors in a depletion region or envelope of the Schottky source contact 150.

Figure 3A schematically depicts a model of a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 3A shows a cross-sectional view of a distributed diode model of the SGT 100.

As described above with respect to Figure 1B, the SGT 100 comprises the stack formed from gate contact 110, formed from Si, and the gate insulator layer 120, formed from SiO₂, thereupon, the oxide semiconductor channel 140, formed from IGZO, overlaying the gate insulator layer 120 of the substrate, the Schottky source contact 150 overlaying a first part of the oxide semiconductor channel 140 and the drain contact 160, overlaying a second part of the oxide semiconductor channel 140. The SGT 100 comprises a gate contact 170 arranged on a reverse side of the Si layer 110 of the substrate. The Schottky source contact 150 and the drain contact 160 are mutually spaced apart by a length L.The oxide semiconductor channel 140 has a thickness H i.e. an oxide semiconductor channel thickness H. The Schottky source contact 150 has a thickness h i.e. a Schottky source contact thickness h.

The oxide semiconductor channel 140 may be modelled as a distributed network of a plurality of diodes D_s (4 diodes arranged in parallel and in series with the 5^th diode in this example) and a plurality of resistors R_sc (4 in this example) and R_CH (3 in this example) arranged there between in a depletion region or envelope of the Schottky source contact 150, in which the resistor R_sc is a resistance due, at least in part, to the oxide semiconductor and the resistor R_CH is a resistance due, at least in part, to the channel. In use, a drain current I_D is controlled by a reverse biased source barrier. In Mode 1, a current R is controlled by modulation of the barrier height at the edge of the Schottky source contact 150 closest to the drain contact 160. In Mode 2, a current I₂ is controlled by a restrictive action of a JFET-like depletion region which forms under the edge of the Schottky source contact 150. The drain current I_D = !, + /₂. That is, the reversed bias diode controls the drain current.

Since the oxide semiconductor channel 140 is highly conductive, vertical transport is likely to be dominated by a reverse bias diode at the Schottky source contact 150 rather than a vertical resistance. An exponential current increase in a reverse bias diode may be attributable to several causes, including tunnelling, image force lowering and/or barrier inhomogeneities. However, if tunnelling or image force lowering were the origin of the exponential current increase, then as the oxide semiconductor channel thicknesses H is reduced, the electric field is increased and hence the exponential dependence of I_D on V_D would only be exacerbated by reducing the oxide semiconductor channel thicknesses H. As the experimental results from Figures 2B to 2E show, reducing the oxide semiconductor channel thicknesses H can remove the exponential behaviour and hence tunnelling and/or image force lowering may be discounted and/or negligible and/or not dominate. A dependence of the reverse current on the oxide semiconductor channel thicknesses H in the Pt - IGZO Schottky diodes 10 may be due to barrier height inhomogeneities. However, the presence of inhomogeneities in Schottky source contacts in SGTs has until now not been investigated .

Figure 3B schematically depicts a structure of a model of a source-gated transistor according to an exemplary embodiment. Particularly, Figure 3B shows a cross-sectional view of a model of the SGT containing an inhomogeneity 180 (also known as a barrier inhomogeneity or a lower barrier region) in the source barrier height in the Schottky source contact 150.

As described above with respect to Figure 1B and Figure 3A, the SGT 100 comprises the stack formed from the gate contact 110, formed from Si, and the gate insulator layer 120, formed from SiO₂, thereupon, the oxide semiconductor channel 140, formed from IGZO, overlaying the gate insulator layer 120 of the substrate, the Schottky source contact 150 overlaying at least a part of the oxide semiconductor channel 140 and the drain contact 160, overlaying at least a part of the oxide semiconductor channel 140. The SGT 100 comprises the gate contact 170 arranged on a reverse side of the Si layer 110 of the substrate. The Schottky source contact 150 and the drain contact 160 are mutually spaced apart by a length L.The oxide semiconductor channel 140 has a thickness H i.e. an oxide semiconductor channel thickness H. The Schottky source contact 150 has a thickness h i.e. a Schottky source contact thickness h and a length S i.e. a Schottky source contact length S. The barrier inhomogeneity 180 has a width L_o of 10 nm providing a lower barrier region (LBR) is at a distance P from a drain contact end of the Schottky source contact 150.

In more detail, the SGTs 100 were simulated using Silvaco Atlas (RTM) available from Silvaco, Inc. (USA). A barrier inhomogeneity 180 was inserted into the Schottky source contact 150, as shown in Figure 3B. Only inhomogeneities having a barrier height lower than a mean barrier height Φ/ of 0.5 eV were considered, as higher barriers are not expected to contribute significantly to the drain current I_D. To help understand the different contributions of the randomly distributed inhomogeneities that occur in fabricated Schottky source contacts 150, positions and magnitudes of the inhomogeneity 180 were varied. The Schottky source contact length S was fixed at 5 pm. The Schottky source contact 150 and the drain contact 160 are mutually spaced apart by a fixed length L (also known as a channel length) of 2 pm. The barrier inhomogeneity 180 has a width L_o of 10 nm. The channel width was fixed at 1 pm.

Figure 3C schematically depicts I_D - V_D output curves for a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 3C shows I_D - V_D output curves for the SGT 100 having a homogeneous source barrier for different V_G from 0 V to 10 V in 1 V steps.

In more detail, Figure 3C shows simulated output curves I_D - V_D of the SGT 100 having a homogeneous Schottky source contact 150, an oxide semiconductor channel thickness H of 100 nm and wherein the oxide semiconductor is IGZO. Note that such a homogeneous Schottky source contact 150 may not be fabricated in practice and is for comparative purposes. The output curve is typical of a standard SGT, with a low saturation current I_Dsat of 0.7 nA, a low saturation voltage V_Dsatlof 2.6 V and a high output impedance r₀ of 200 GD, when V_G is 10 V.

Figure 3D schematically depicts Id ~ Vd output curves for a source-gated transistor 100 according to an exemplary embodiment. Particularly, Figure 3D shows I_D - V_D output curves for the SGT 100 for different gate contact voltages V_G from 0 V to 10 V in 1 V steps. The SGT 100 has an oxide semiconductor channel thickness H of 100 nm and the oxide semiconductor is IGZO. The barrier inhomogeneity has a width L_o of 10 nm and a magnitude Δ = 0.3 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end of the Schottky source contact 150.

In comparison with Figure 3C, Figure 3D shows Id ~ Vd output curves for the otherwise same SGT as Figure 3C but having an inhomogeneous Schottky source contact 150. In this example, the lower barrier region (LBR) is introduced at the distance P of 100 nm from a drain contact end of the Schottky source contact 150. The barrier in this region is lowered by Δ = 0.3 eV. The presence ofthe LBR leads to a large deterioration in output impedance and a current increase larger than one order of magnitude. The non-linear region seen in experiments is also replicated, suggesting that inhomogeneities may be the source of the sub-optimal characteristics seen in Figure 2D and Figure 2E. Similar behaviour may also be seen with different values of Δ, distance/⁵ and width L_o. I_D - V_Doutput curves for different gate contact voltages V_G overlap prior to saturation due to the Schottky source being only 5 pm long in the device simulation. Restrictions upon the number of nodes used in the device simulation prevents simultaneously having a significantly longer source and capturing the fine detail in the region ofthe barrier inhomogeneity.

Figure 3E schematically depicts current densities for the source-gated transistor 100 of Figure 3D. Particularly, Figure 3E shows profiles of current densities |/| across the Schottky source contact 150 ofthe SGT 100 of Figure 3D for different gate contact voltages V_G from 0.2 V to 2 V in 0.2 V steps. The SGT 100 has an oxide semiconductor channel thickness H of 20 nm and the oxide semiconductor is IGZO. The barrier inhomogeneity 180 has a width L_o of 10 nm and a magnitude Δ = 0.3 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end ofthe Schottky source contact 150.

In more detail, to establish the origin ofthe non-linear behaviour shown in Figure 3D, profiles ofthe current density across the Schottky source contact 150 were taken for drain voltages V_D below saturation. Figure 3E shows that the current density |/| is dominated by the contribution from the inhomogeneity 180. Unlike the current density |/| contribution from the rest of the Schottky source contact 150, this current density |/| increases exponentially, by two orders of magnitude, as the drain voltage V_D increases from 0.2 V to 2 V.

Figure 3F schematically depicts E_c - z depth profiles of conduction band minima for the sourcegated transistor of Figure 3D. That is, Figure 3F schematically depicts conduction band E_c minima as a function of depth z . Particularly, Figure 2F shows E_c - z depth profiles ofthe conduction band minima beneath a centre of the inhomogeneity for different V_D from 0 V to 2 V in 0.2 V steps for a V_Gof 10 V. The SGT has an oxide semiconductor channel thickness H of 100 nm and the oxide semiconductor is IGZO. The barrier inhomogeneity has a width L_o of 10 nm and a magnitude Δ = 0.3 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end ofthe Schottky source contact 150. The E_c - z depth profiles have respective saddle points SP (SP_QV SP_2V) (i.e. maxima). Only saddle points SP_0V and SP_2V are labelled, for clarity.

In more detail, an origin ofthe exponential growth ofthe current density |/|, described above with respect to Figure 3E, may be understood from Figure 3F. Particularly, Figure 3F shows profiles ofthe conduction band minima vertically from the centre of the inhomogeneity 180 down to the semiconductor - dielectric interface i.e. as a function of depth z . These profiles show that respective saddle points SP are established beneath the inhomogeneity due to pinch-off by the surrounding higher barrier regions. These respective saddle points SP act as effective barrier heights for the inhomogeneity and thus the entire Schottky source contact 150. The strong voltage dependence of the respective saddle points SP leads to the exponential dependence of the current prior to saturation.

Figure 3G schematically depicts E_c - z depth profiles of conduction band minima for source-gated transistors according to exemplary embodiments. Particularly, Figure 3G shows E_c-z depth profiles of the conduction band minima beneath a centre of inhomogeneity at zero bias (i.e. V = 0 V) as a function of oxide semiconductor channel thickness H for oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm. The oxide semiconductor is IGZO. The barrier inhomogeneity has a width L_o of 10 nm and a magnitude Δ = 0.3 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end of the Schottky source contact 150. A mean barrier height Φ/ is 0.5 eV. A dependence of the effective barrier height on the oxide semiconductor channel thickness H is shown.

The conduction band E_c minima at the interface of the Schottky source contact 150 - oxide semiconductor 140 is the same for all oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm.

The E_c - z depth profiles for oxide semiconductor channel thicknesses H of 20 nm, 30 nm, 50 nm and 100 nm have respective saddle points SP (SP_20nm, SP_30nm, SP_ZOnm, SP_100nm) (i.e. maxima). For these E_c - z depth profiles for oxide semiconductor channel thicknesses H of 20 nm, 30 nm, 50 nm and 100 nm, the conduction band minima E_c increase away from the interface of the Schottky source contact 150 - oxide semiconductor 140 through the oxide semiconductor 140, having respective maxima at the respective saddle points SP (SP_20nm, SP_30nm, SP_ZOnm, SP_100nm) before decreasing monotonically away from the interface through the oxide semiconductor 140. The respective saddle points SP_20nm, ^30nm. ^Spso_nm, ^spioonm ^{are at} respective depths of approximately 4 nm, 6 nm, 9 nm and 14 nm.

The E_c - z depth profile for the oxide semiconductor channel thicknesses H of 10 nm does not have a saddle point. Rather, the maximum of the conduction band minimum E_c for the oxide semiconductor channel thicknesses H of 10 nm is at the interface of the Schottky source contant 150 - oxide semiconductor 140 and the conduction band minimum E_c decreases monotonically away from the interface through the oxide semiconductor 140.

From the experimental results, as described above with respect to Figures 2B to 2F, the exponential dependence of the current prior to saturation disappears as the oxide semiconductor channel thicknesses H is reduced. Figure 3G compares the profiles of the conduction band minimum E_c for different oxide semiconductor channel thicknesses H at zero bias. An oxide semiconductor channel thickness H dependence of the saddle point SP, similar to that observed in Schottky diodes, is present. As the oxide semiconductor channel thickness H is reduced, the electric field increases and reduces a height of the saddle point SP. When the oxide semiconductor channel thickness H is sufficiently small, the saddle point SP is eventually removed entirely, such as when the oxide semiconductor channel thicknesses H of 10 nm, for this example. In the absence of a saddle point SP, the effective barrier height of the inhomogeneity 180 loses its voltage dependence and the drain current I_D will no longer increase exponentially with drain voltage V_D. Thus, the experimental trend is reproduced. This effect occurs for all inhomogeneities except those at the edge of the Schottky source contact 150, which cannot be pinched-off and so do not have a saddle point. If the Schottky source contact 150 is sufficiently long, injection from the edge of the Schottky source contact 150 can be discounted as other contributions dominate. Once the saddle point SP is lowered, the current dependence on voltage prior to saturation becomes linear as the diffusion current is only dependent on the increase in electric field, which should occur linearly with drain voltage V_D.

Once drain voltage V_D is large enough to deplete the oxide semiconductor 140 under the edge of the Schottky source contact 150, the SGT 100 saturates regardless of whether output was linear or exponential. However, just as in the experiments described above, there remains a dependence of the oxide semiconductor channel thicknesses H on the output impedance. Unlike the case prior to source saturation, the output impedance cannot be significantly affected by inhomogeneities everywhere in the Schottky source contact 150. This is because the potential from the drain contact 160 cannot penetrate to the source after saturation. The potential can penetrate the region at the front end of the Schottky source contact 150 and it is here that the small variations in barrier height can produce the changes in current that limit output impedance. Even the small changes in potential that get through are amplified by an exponential dependence of the current at the saddle point SP. Again, by reducing the oxide semiconductor channel thickness H, these saddle points SP are removed, leading to a voltage independent barrier height and a higher output impedance, as shown in Figures 2B to 2F. That barrier inhomogeneities 180 are the cause of this behaviour is further supported by simulated transfer curves, described with respect to Figure 7A and Figure 7B.

Intrinsic gain

The intrinsic gain A_v is the maximum voltage gain of a TFT and is thus an important measure of the

TFT’s ability to amplify a signal. Particularly, the intrinsic gain A_v of a TFT may be considered to be a figure of merit thereof. In display applications, TFTs having high intrinsic gains A_v may behave as excellent constant current sources. Furthermore, higher intrinsic gains A_v may also give greater noise margins in logic circuits, leading to greater immunity to noise. The intrinsic gain A_v may be calculated as the ratio of transconductance g_m to output conductance g_d or a product of the transconductance g_m and an output resistance r₀:

Or

Αγ — 9mTo

Where _ 4I_d ^9m~ di£ and ^9d r₀ dV_D

Currently, the intrinsic gain in an Si MOSFET is limited to 20 to 40, while for poly-Si TFTs having long channels, the intrinsic gain has been shown to be more than 100. Given the behaviour of the saddle point, it is possible to try to maximise intrinsic gain by reducing the thickness of the IGZO in our devices.

Figure 4A, Figure 4B and Figure 4C shows intrinsic gains A_v for different oxide semiconductor channel thicknesses H. The preferred or optimum SGT 100 has an oxide semiconductor channel thicknesses H of 20 nm, wherein the oxide semiconductor is IGZO, and achieves an intrinsic gain A_vof approximately 3,000 over a large range of drain voltages V_D (Figure 4A).

Figure 4A schematically depicts intrinsic gains A_v as functions of gate contact voltage V_G for a sourcegated transistor 100 according to an exemplary embodiment. Particularly, Figure 4A shows intrinsic gains A_v plotted against gate contact voltage V_G for different drain voltages V_D from 5 V to 15 V in 2 V steps for the SGT having an oxide semiconductor channel thickness H of 20 nm and wherein the oxide semiconductor is IGZO.

Figure 4B schematically depicts intrinsic gains A_v as functions of drain voltage V_D for the source-gated transistor of Figure 4A. Particularly, Figure 4B shows intrinsic gains A_v plotted against V_D for different gate contact voltages V_G from 10 V to 40 V in 5 V steps for the SGT having an oxide semiconductor channel thickness H of 20 nm and the oxide semiconductor is IGZO.

Figure 4C schematically depicts intrinsic gains A_v as functions of drain voltage V_D for a source-gated transistor 100 according to exemplary embodiments. Particularly, Figure 4C shows intrinsic gains A_vplotted against drain voltage V_D for a gate contact voltage V_G of 40 V for the SGTs 100 having oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm and 50 nm and wherein the oxide semiconductor is IGZO.

As shown in Figure 4C, the SGT 100 having an oxide semiconductor channel thicknesses H of 20 nm, wherein the oxide semiconductor is IGZO, achieves the highest intrinsic gain A_v of approximately 3,000 over a large range of drain voltages V_D, compared with other oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm and 50 nm. The SGT 100 having an oxide semiconductor channel thicknesses H of 50 nm has an intrinsic gain A_v of upto about 20 at a drain voltage V_D of 15 V. The SGTs 100 having oxide semiconductor channel thicknesses H of 20 nm and 30 nm respectively have similar intrinsic gains A_v of up to about 100 at a drain voltage V_D of 15 V. Particularly, the intrinsic gain A_v of approximately 3,000, for the SGT 100 having the oxide semiconductor channel thicknesses H of 20 nm, represents a huge improvement compared with a standard TFT. Compared to SGTs in other materials, the SGT 100 maintains an intrinsic gain A_v of over 1,000 over a far larger range of voltages. While some polysilicon SGTs have intrinsic gains A_v of up to 10,000 for very narrow ranges of drain voltage V_D, oxide semiconductor SGTs have thus far been limited to intrinsic gains A_v of only about 400. This huge improvement in intrinsic gain A_v of the SGTs 100 would not be possible through understanding the conventional operating mechanism of the SGT alone. Rather, detailed knowledge of barrier inhomogeneities, which are especially prevalent in oxide semiconductor Schottky junctions, is equally important. As a first effect, the source saturation shields the source region from large variations in potential. As a second effect, by reducing the oxide semiconductor channel thicknesses H, saddle points SP in the conduction band minima E_c, beneath the lower barrier regions provided at least in part by the barrier inhomogeneities, are reduced or removed. Combined, these two effects serve to prevent small variations in the drain voltage V_Dcausing otherwise large changes in the drain current I_D, thus maintaining a near constant current I_D.

Reducing the oxide semiconductor channel thicknesses H down to 10 nm, in this example, did not improve the intrinsic gain A_v further, as shown in Figure 4C. Rather, in SGTs 100 having such small oxide semiconductor channel thicknesses H, the electric field becomes so large that tunnelling and other barrier lowering mechanisms additionally affect the saturation current of the output curve. The maximum intrinsic gain A_v achieved in these examples may be dependent upon limiting gate contact leakage and/or traps that lead to hysteresis. These factors can make the gain measurements noisy, especially in such high gain SGTs 100.

Short channel effect

While oxide semiconductor, for example IGZO, TFTs suffer less from a short channel effect than TFTs made with other semiconductors, for example a-Si:H, these oxide semiconductor TFTs may suffer when a channel length L_CH is reduced below ~ 4pm. This may create a problem for device scaling.

SGTs have been shown to be independent of channel length down to 2 pm, due to the source contact being shielded from the drain contact. Using electron beam lithography, SGTs 100 having channel lengths L_CH of 2 pm, 1 pm, 0.8 pm and 0.6 pm were fabricated, in which the oxide semiconductor is IGZO. The I_D - V_D output curves of these SGTs 100 are shown in Figure 5A, Figure 5B, Figure 5C and Figure 5D, respectively.

Figure 5A schematically depicts I_D - V_D output curves for a source-gated transistor according to an exemplary embodiment. Particularly, Figure 5A shows I_D - V_D output curves for the SGT having an oxide semiconductor channel length L_CH of 2 pm and the oxide semiconductor is IGZO.

Figure 5B schematically depicts f ~ Vd output curves for a source-gated transistor according to an exemplary embodiment. Particularly, Figure 5B shows I_D - V_D output curves for the SGT having an oxide semiconductor channel length L_CH of 1 pm and the oxide semiconductor is IGZO.

Figure 5C schematically depicts I_D - V_D output curves for a source-gated transistor according to an exemplary embodiment. Particularly, Figure 5C shows I_D - V_D output curves for the SGT having an oxide semiconductor channel length L_CH of 0.8 pm and the oxide semiconductor is IGZO.

Figure 5D schematically depicts Id ~ Vd output curves for a source-gated transistor according to an exemplary embodiment. Particularly, Figure 5A shows I_D - V_D output curves for the SGT having an oxide semiconductor channel length L_CH of 0.6 pm and the oxide semiconductor is IGZO.

Flat saturation up to a drain voltage V_D of 20 V is maintained down to channel lengths L_CH of 0.8 pm (800 nm). Below this channel length L_CH, the electric field is sufficiently large as to induce barrier lowering in the Schottky source contact 150. The electric field from the drain contact 160 at a drain voltage V_D of 20 V is approximately 33 MV cm^-1, which is similar to the breakdown field in IGZO Schottky diodes.

Negative bias illumination temperature stress

In conventional TFTs, the oxide semiconductor, for example IGZO, channel is very sensitive to the combination of light and negative gate bias stress, known as Negative Bias Illumination Temperature Stress (NBITS). This causes the threshold voltage of the conventional TFTs to shift negatively during use and is a big problem for display applications which have back lights. The SGT 100 removes this problem almost entirely, by making the behaviour dependent on the source region only, thus removing the need for an extra shielding layer, as described below in more detail.

When conventional IGZO TFTs are held at negative bias under illumination of near band gap energy photons, there is a large negative shift in the threshold voltage V_T of the oxide semiconductor channel. This instability has been attributed to the presence of deep traps formed by oxygen vacancies, although the mechanism for this is still not fully understood. The near-bandgap light will excite electrons (holes) into the conduction (valance) band. The holes will be drawn towards the gate contact by the electric field and can become trapped either at the interface or in the gate contact dielectric. Once the bias is removed, these holes can remain trapped, leading to electron accumulation on the IGZO-side of the interface. While the threshold voltage V_T shift can be reduced by various measures including high pressure annealing and asymmetric source-drain contacts, until now it remains impractical to incorporate IGZO SGTs into displays without implementing light shielding measures. Such light shielding measures negate contact any advantages of transparency that may be offered by IGZO SGTs as well as introducing an additional fabrication step.

In contrast, the SGTs 100 do not exhibit the negative shift in the threshold voltage V_T exhibited by conventional IGZO TFTs. Negative bias illumination stress tests were carried out on IGZO SGTs 100. The SGTs 100 were held at -20 V and 80 °C under illumination from a white LED (around 2000 lx) at a distance of 3 cm away from the SGTs 100.

Figure 6 schematically depicts I_D - V_G curves related to negative bias illumination stress for a sourcegated transistor 100 according to an exemplary embodiment. Particularly, Figure 6 shows effects of negative bias illumination stress on the SGT wherein the oxide semiconductor is IGZO.

Almost no shift in on voltage V_0N is observed for the SGT 100 as shown in Figure 6. This is due to independence of the SGT 100 from a quality of the oxide semiconductor channel 140. As long as the oxide semiconductor channel 140 is sufficiently conductive so that the Schottky source contact 150 region controls the current, any instability in the oxide semiconductor channel 140 is negated. This behaviour offers a huge advantage over conventional IGZO TFTs, where post treatment is required and does not achieve this level of stability. The complete absence of a shift in on voltage V_0N of the SGT 100 opens the door to wider application in the display industry.

Simulations

Device simulations were carried out using Silvaco Atlas. Atlas solves Poisson’s equation, the charge carrier continuity equations and the charge transport equations. SGT structures were simulated with a barrier inhomogeneity 180 inserted into the Schottky source contact 150. The barrier height Φβ of the Schottky contact source 150 was fixed at 0.5 eV except at the inhomogeneity 180 where the barrier height was -Δ. The value of Δ was varied from 0, simulating a homogeneous source, to 0.3 eV. Inhomogeneity distance P with respect to the drain contact 160 end of the Schottky contact source 150 edge was varied, with P being 0, 10, 100, 1000 and 4000 nm. The inhomogeneity width L_o was also varied, with L_o being 3, 10 and 30 nm. Unless specified, the source length S and channel length L_ch were fixed at 5 pm and 2 pm, respectively. Oxide semiconductor channel thicknesses H were of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm. The oxide semiconductor was IGZO and the default Atlas model for IGZO was used. The dielectric was SiO₂ and the dielectric thickness was fixed at 100 nm. The length of the drain contact 160 was fixed at 1 pm and the gate contact overlapped the entirety of the device. The channel width L_GH was fixed at 1 pm.

Figure 7A schematically depicts |/_D| - V_G transfer curves for models of source-gated transistors according to exemplary embodiments. Particularly, Figure 7A shows simulated |/_D| - V_G transfer curves at V_D = 1V for the SGTs having a barrier inhomogeneity 1 pm from a drain contact end of the respective Schottky source contacts 150 for oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm. The barrier inhomogeneity has a width L_o of 10 nm and a magnitude Δ = 0.3 eV. A mean barrier height Φ_Β is 0.5 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end of the Schottky source contact 150. The results of these simulations are comparable with the experimental results as shown in Figure 2B. Similar results may also be shown for different values ofA and the mean barrier height Φ_Β.

Figure 7B schematically depicts |/_D| - V_G transfer curves for models of source-gated transistors of Figure 7A. Particularly, Figure 7B shows simulated \I_D | - V_G transfer curves at V_D = 10 V for the SGTs having a barrier inhomogeneity 1 pm from a drain contact end of the respective Schottky source contacts 150 for oxide semiconductor channel thicknesses H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm. The barrier inhomogeneity has a width L_o of 10 nm and a magnitude A = 0.3 eV. A mean barrier height Φ_Β is 0.5 eV. A lower barrier region (LBR) is at a distance P of 100 nm from a drain contact end of the Schottky source contact 150. The results of these simulations are comparable with the experimental results as shown in Figure 2C. Similar results may also be shown for different values of Δ and the mean barrier height Φ_Β.

Fabrication of Schottky diodes

IGZO-Pt Schottky diodes 10 were fabricated using Ti as an ohmic contact. SiO₂-Si wafers, providing the substrate 11, 12, were cleaned by sonic agitation in an ultrasonic bath using DECON 90, deionized water, acetone and isopropyl alcohol, respectively. Using radio-frequency (RF) sputtering of a Ti target, a 70 nm thick Ti layer was deposited on the wafers, to provide the ohmic contact layer 13. For Ti sputtering, the working gas was Ar, the pressure was 5 χ 10’³ mbar and the sputtering power was 150 W. A 150 nm thick IGZO layer was deposited via RF sputtering using an IGZO target with a molar ratio of 1:1:2 (ln2O3:Ga2O3:ZnO), available from the Kurt J Lesker Company Ltd (UK). For IGZO sputtering, the working gas was Ar, the pressure was 5x10³ mbar and the sputtering power was 100 W. Prior to Pt deposition, the structure was annealed at 300 °C in an N2 atmosphere for 1 hour. A 70 nm Pt layer, to form the Schottky source contact 15, was also deposited by RF sputtering a Pt target, available from Leybold Materials GmbH (Germany) in either pure Ar or 3% O₂/Ar mix at a pressure of 5 χ 10’³ mbar at a sputtering power of 60 W and for a 3 inch diameter target (i.e. a sputtering power of 60 W corresponds to 1.32 W/cm²), unless otherwise stated. The Schottky diodes were patterned using shadow masks.

Fabrication of source-gated transistors

SGTs 100 were fabricated using SiO₂-Si wafers with 100 nm thick SiO2. The wafers were cleaned by sonic agitation in an ultrasonic bath using DECON 90, de-ionized water, acetone and isopropyl alcohol, respectively. The oxide semiconductor channel 140 was IGZO, deposited via RF sputtering using an IGZO target with a molar ratio of 1:1:2 (ln₂O₃:Ga₂O₃:ZnO) available from the Kurt J Lesker Company Ltd (UK).. The working gas was Ar, the pressure was 5x10‘³ mbar and the sputtering power was 100 W. Prior to Pt deposition, the structure was annealed at 300 °C in an N₂ atmosphere for 1 hour. A 70 nm Pt layer, to form the Schottky source contact 150 and the drain contact 160, was also deposited by RF sputtering a Pt target available from Leybold Materials GmbH (Germany) in either pure Ar or 3% O₂/Ar mix at a pressure of 5 χ 10’³ mbar and at a sputtering power of 60 W, unless otherwise stated. The SGTs 100 were patterned using shadow masks and photolithography, except for the short-channel SGTs 100 which were patterned using standard electron beam lithography.

Figure 8 schematically depicts a method of forming a Schottky source contact on an oxidesemiconductor channel according to an exemplary embodiment.

At S801, the source contact is deposited on the oxide semiconductor channel in an atmosphere comprising oxygen.

The method may include any of the steps described herein.

Figure 9 schematically depicts a method of forming a Schottky source contact on an oxidesemiconductor channel according to an exemplary embodiment.

The oxide semiconductor channel is amorphous a(ln₂O₃).b(Ga₂O₃).c(ZnO), wherein a = 1, b = 1 and c = 2, and wherein a thickness H of the oxide semiconductor channel is in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nm to 30 nm, for example 20 nm or 25 nm.

The source contact is platinum.

At S901, the oxide semiconductor is annealed prior to depositing the source contact thereon. The annealing is in an inert atmosphere, preferably nitrogen, at a temperature in a range from 200 °C to

400 °C, preferably in a range from 250 °C to 350 °C, for example 300 °C for at least 30 minutes, preferably about 60 minutes.

At S902, the source contact is deposited on the oxide semiconductor channel in an atmosphere comprising oxygen. The atmosphere comprising the oxygen may be an inert gas, preferably argon, comprising the oxygen in a range from 0.1 % to 10 %, preferably in a range from 1 % to 5 %, for example 3% by partial pressure. The pressure of the atmosphere may be in a range from 1 χ 10’⁵mbar to 1 χ 10‘¹ mbar, preferably in a range from 1 χ 10’⁴ mbar to 1 χ 10’² mbar, for example 5 χ 10’³ mbar. Depositing the source contact on the oxide semiconductor channel may comprise sputtering the source contact on the oxide semiconductor channel at a sputtering power in a range from 0.4 W/cm² to 3 W/cm², preferably in a range from 0.6 W/cm² to 1.7 W/cm², for example 0.88 W/cm² or 1.32 W/cm². These sputtering powers correspond with a sputtering power in a range from 20 W to 150 W, preferably in a range from 30 W to 80 W, for example 40 W or 60W, respectively, for a 3 inch diameter sputtering target, as used herein.

The method may include any of the steps described herein.

Measurement

Room temperature measurements were carried out on a probe station and the diodes 10 and SGTs 100 were contacted with probes tips controlled using micromanipulators. For negative bias illumination temperature stress measurements, the SGTs were glued to a chip carrier and bonded with gold wire, prior to being connected to a temperature controlled stage inside a Advanced Research Systems, Inc. 4K cryostat. The source of illumination was a white LED (around 2000~lx) at a distance of 3~cm away from the SGTs. An Agilent E5260B semiconductor analyzer, contolled by an in-house Labview program, was used for all electrical measurements.

Although a preferred embodiment has been shown and described, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the scope of the invention, as defined in the appended claims and as described above.

In summary, the invention provides a source-gated transistor comprising a Schottky source contact on an oxide semiconductor channel that has an improved intrinsic gain, an improved short channel effect and/or an improved negative bias illumination temperature stress. The invention also provides a method of forming a Schottky source contact upon an oxide semiconductor channel that improves an intrinsic gain, a short channel effect and/or a negative bias illumination temperature stress.

Attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at most some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A source-gated transistor, SGT, comprising a Schottky source contact on an oxide semiconductor channel, the SGT having an intrinsic gain of at least 500, preferably at least 1,000, more preferably at least 2,000, most preferably at least 3,000.

2. The SGT according to claim 1, wherein an effective barrier height of the Schottky source contact is substantially independent of a drain voltage VD of the SGT, in use.

3. The SGT according to any previous claim, wherein a maximum potential of a conduction band minimum of the oxide semiconductor channel at zero bias is within 10 nm, preferably within 5 nm, more preferably within 3 nm of an interface between the Schottky source contact and the oxide semiconductor channel.

4. The SGT according to claim 3, wherein the oxide semiconductor channel has a thickness H sufficiently small such that the maximum potential of the conduction band minimum of the oxide semiconductor channel at zero bias is within 10 nm, preferable within 5 nm, more preferably within 3 nm of an interface between the Schottky source contact and the oxide semiconductor channel.

5. The SGT according to any previous claim, wherein the oxide semiconductor comprises and/or is a ZnO-based oxide semiconductor, preferably an amorphous ZnO-based oxide semiconductor.

6. The SGT according to claim 5, wherein the oxide semiconductor is amorphous a(ln2O3).b(Ga2O3).c(ZnO), wherein a, b, and c are real numbers where a > 0, b > 0, and/or c > 0.

7. The SGT according to any previous claim, wherein the oxide semiconductor channel has a thickness H in a range from 5 nm to 50 nm, preferably in a range from 10 nm to 40 nm, more preferably in a range from 15 nm to 30 nm, for example 20 nm or 25 nm.

8. The SGT according to any previous claim, wherein the Schottky source contact comprises and/or is formed of a material, for example a metal, an alloy, a non-metal, having a work function of at least 4.5 eV, preferably at least 5 eV.

9. The SGT according to any previous claim, wherein the oxide semiconductor channel is annealed before deposition of the Schottky source contact thereon.

10. The SGT according to any previous claim, wherein the Schottky source contact is deposited on the oxide semiconductor channel by sputtering in an atmosphere comprising oxygen.

11. An inverter, a logic gate, an integrated circuit, an analogue circuit or a display comprising a source-gated transistor according to any of claims 1 to 10.

12. A method of forming a Schottky source contact on an oxide semiconductor channel for a sourcegated transistor, SGT, the method comprising:

13. The method according to claim 12, wherein depositing the source contact on the oxide semiconductor channel comprises sputtering the source contact on the oxide semiconductor channel at a sputtering power in a range from 0.4 W/cm2 to 3 W/cm2, preferably in a range from 0.6 W/cm2 to 1.7 W/cm2.

14. The method according to any of claims 12 to 13, wherein the atmosphere comprising the oxygen is an inert gas, preferably argon, comprising the oxygen in a range from 0.1 % to 10 %, preferably in a range from 1 % to 5 % by partial pressure.

15. The method according to claim 14, wherein a pressure of the atmosphere is in a range from 1 χ 10’5 mbarto 1 χ 10‘1 mbar, preferably in a range from 1 χ 10’4 mbarto 1 χ 10’2 mbar, for example 5 x 10’3 mbar.

16. The method according to any of claims 12 to 15, comprising annealing the oxide semiconductor prior to depositing the source contact thereon.

17. The method according to claim 16, wherein the annealing is in an inert atmosphere, preferably nitrogen, at a temperature in a range from 200 °C to 400 °C, preferably in a range from 250 °C to 350 °C, for example 300 °C.