US20210143275A1 - Finfet stack gate memory and mehod of forming thereof - Google Patents

Finfet stack gate memory and mehod of forming thereof Download PDF

Info

Publication number
US20210143275A1
US20210143275A1 US16/815,151 US202016815151A US2021143275A1 US 20210143275 A1 US20210143275 A1 US 20210143275A1 US 202016815151 A US202016815151 A US 202016815151A US 2021143275 A1 US2021143275 A1 US 2021143275A1
Authority
US
United States
Prior art keywords
oxide
sti
memory
disposed
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/815,151
Other languages
English (en)
Inventor
Hsingya Arthur Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Integrated Silicon Solution Inc
Original Assignee
Integrated Silicon Solution Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Silicon Solution Inc filed Critical Integrated Silicon Solution Inc
Priority to US16/815,151 priority Critical patent/US20210143275A1/en
Assigned to INTEGRATED SILICON SOLUTION INC. reassignment INTEGRATED SILICON SOLUTION INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WANG, HSINGYA ARTHUR
Priority to TW110125956A priority patent/TWI794887B/zh
Priority to TW109126585A priority patent/TWI742792B/zh
Priority to CN202010776012.9A priority patent/CN112786598B/zh
Publication of US20210143275A1 publication Critical patent/US20210143275A1/en
Priority to US17/563,214 priority patent/US11616145B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present disclosure relates to a stack gate memory and a method of forming thereof. More particularly, the present disclosure relates to a FINFET stack gate memory and a method of forming thereof.
  • FIG. 8 is a schematic view of a structure of a stack gate memory 30 of prior art.
  • a SiO 2 film 31 is grown on a p-type silicon wafer 32 in a furnace at 1000° C., and a thickness of the SiO 2 film 31 is about 200 ⁇ .
  • masks and implants are applied to form a deep N-well, an N-well and a P-well.
  • a silicon nitride (Si 3 N 4 ) film 33 is deposited for about 2000 ⁇ , a photo printing active area (AA) pattern is applied for transistors, and a stack of Si 3 N 4 /SiO 2 /silicon is etched in sequence.
  • AA photo printing active area
  • CG structure forming step a portion of the FG structure is removed in the non-memory cell area of the memory structure, a second polysilicon is disposed on a surface of the ONO layer in the memory cell area and on the surface of the substrate and a surface of the STI oxide in the non-memory cell area of the memory structure to form a CG structure, and the FinFET stack gate memory is formed.
  • FIG. 1 is a step flow chart of a method of forming a FinFET stack gate memory according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic view of the FG structure forming step according to the embodiment of FIG. 1 .
  • FIG. 7 is a schematic view of the CG structure forming step according to the embodiment of FIG. 1 .
  • the nitride film 231 is formed on a thin oxide film 211 , and the thin oxide film 211 is disposed on a substrate 210 .
  • the substrate 210 can be made of a silicon.
  • the memory cell area 230 can be masked-off, and the nitride film 231 can be removed by an etching process in a non-memory cell area 240 .
  • the STI oxide 221 can be disposed in the STI structure 220 via a process of chemical vapor deposition (CVD), and the STI oxide is performed via a chemical-mechanical polishing (CMP).
  • CVD chemical vapor deposition
  • CMP chemical-mechanical polishing
  • the tunnel oxide 232 is disposed in the side-wall region formed in the stripping step S 102 , and it is favorable for increasing an effective memory cell channel width.
  • the mask is applied for covering the memory cell area 230 , and the ONO layer 234 and the FG structure 233 are removed via the etching process in the non-memory cell area 240 for reserving for a plurality of peripheral devices. Furthermore, source/drain junctions for the memory cell area 230 and the peripheral devices are formed, and contact/metal connections are formed to allow proper electric connections.
  • a channel width of a scaling barrier scaling below 120 nm can be maintained, and an effective channel width can be widen. Moreover, it is favorable for avoiding significant current loss and reliability issue, and also maintaining proper cell current. Further, a scaling limitation can be decreased, and a density of the FinFET stack gate memory can be increased.
  • the STI structure 220 is disposed on the substrate 210 , and includes the STI oxide 221 .
  • the STI oxide 221 is disposed in the STI structure 220 , the STI oxide 221 can be made of silicon oxide, and a thickness of the STI oxide 221 can be 600 ⁇ to 2400 ⁇ .
  • the memory cell area 230 includes the nitride film 231 , the tunnel oxide 232 , the FG structure 233 , the ONO layer 234 and the CG structure 235 .
  • the nitride film 231 is disposed on a surface of the STI structure 220 and below the surface of the substrate 210 .
  • the tunnel oxide 232 is disposed on the substrate 210 , the tunnel oxide 232 can be made of silicon oxide, and a thickness of the tunnel oxide 232 can be 70 ⁇ to 105 ⁇ . It is worth mentioning that the best thickness of the tunnel oxide 232 is 95 ⁇ , but is not limited thereto.
  • the FG structure 233 is disposed on the tunnel oxide 232 .
  • the non-memory cell area 240 is connected to the memory cell area 230 , and includes the plurality of peripheral devices. Moreover, the memory cell area 230 is isolated from the non-memory cell area 240 , and a short circuit will not be caused.
  • the peripheral devices includes a high voltage N-channel (HVN) logic device 241 , a low voltage N-channel (LVN) logic device 242 , a high voltage P-channel (HVP) logic device 243 and a low voltage P-channel (LVP) logic device 244 .
  • a triple P-well (its reference numeral is omitted) is located on a deep N-well (its reference numeral is omitted) of the substrate 210 in the memory cell area 230 , and a P-well (its reference numeral is omitted) is located beside an N-well (its reference numeral is omitted) of the substrate 210 in the non-memory cell area 240 .
  • an effective memory cell channel width is increased, a further memory cell size scaling can be allowed, and a current of the FinFET stack gate memory can be kept intact.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
US16/815,151 2019-11-11 2020-03-11 Finfet stack gate memory and mehod of forming thereof Abandoned US20210143275A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US16/815,151 US20210143275A1 (en) 2019-11-11 2020-03-11 Finfet stack gate memory and mehod of forming thereof
TW110125956A TWI794887B (zh) 2019-11-11 2020-08-05 Finfet堆疊閘記憶體
TW109126585A TWI742792B (zh) 2019-11-11 2020-08-05 Finfet堆疊閘記憶體與其形成方法
CN202010776012.9A CN112786598B (zh) 2019-11-11 2020-08-05 FinFET堆叠栅存储器的形成方法
US17/563,214 US11616145B2 (en) 2019-11-11 2021-12-28 FINFET stack gate memory and method of forming thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962933588P 2019-11-11 2019-11-11
US16/815,151 US20210143275A1 (en) 2019-11-11 2020-03-11 Finfet stack gate memory and mehod of forming thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/563,214 Division US11616145B2 (en) 2019-11-11 2021-12-28 FINFET stack gate memory and method of forming thereof

Publications (1)

Publication Number Publication Date
US20210143275A1 true US20210143275A1 (en) 2021-05-13

Family

ID=75847885

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/815,151 Abandoned US20210143275A1 (en) 2019-11-11 2020-03-11 Finfet stack gate memory and mehod of forming thereof
US17/563,214 Active US11616145B2 (en) 2019-11-11 2021-12-28 FINFET stack gate memory and method of forming thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/563,214 Active US11616145B2 (en) 2019-11-11 2021-12-28 FINFET stack gate memory and method of forming thereof

Country Status (2)

Country Link
US (2) US20210143275A1 (zh)
TW (2) TWI742792B (zh)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7332408B2 (en) * 2004-06-28 2008-02-19 Micron Technology, Inc. Isolation trenches for memory devices
JP2006286788A (ja) * 2005-03-31 2006-10-19 Fujitsu Ltd 半導体装置とその製造方法
TWI288966B (en) * 2005-09-05 2007-10-21 Promos Technologies Inc Memory structure with high coupling ratio and forming method thereof
KR100660543B1 (ko) * 2005-10-24 2006-12-22 삼성전자주식회사 낸드형 플래시 메모리 장치 및 그 제조 방법
JP2008071827A (ja) * 2006-09-12 2008-03-27 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
JP5076426B2 (ja) * 2006-09-29 2012-11-21 富士通セミコンダクター株式会社 半導体装置の製造方法
US7642616B2 (en) * 2007-05-17 2010-01-05 Micron Technology, Inc. Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device
US8837216B2 (en) * 2010-12-13 2014-09-16 Sandisk Technologies Inc. Non-volatile storage system with shared bit lines connected to a single selection device
US20130285134A1 (en) * 2012-04-26 2013-10-31 International Business Machines Corporation Non-volatile memory device formed with etch stop layer in shallow trench isolation region
KR102002942B1 (ko) * 2013-04-18 2019-07-24 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그 제조방법
US20150115346A1 (en) * 2013-10-25 2015-04-30 United Microelectronics Corp. Semiconductor memory device and method for manufacturing the same
KR102378342B1 (ko) 2015-06-24 2022-03-25 인텔 코포레이션 고품질 계면을 위한 대체 채널 에칭
US10510544B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory semiconductor device and manufacturing method thereof
US10192746B1 (en) 2017-07-31 2019-01-29 Globalfoundries Inc. STI inner spacer to mitigate SDB loading
US10937879B2 (en) 2017-11-30 2021-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TW202119599A (zh) 2021-05-16
TWI742792B (zh) 2021-10-11
US20220123146A1 (en) 2022-04-21
TW202141755A (zh) 2021-11-01
TWI794887B (zh) 2023-03-01
US11616145B2 (en) 2023-03-28

Similar Documents

Publication Publication Date Title
US6383861B1 (en) Method of fabricating a dual gate dielectric
US6146970A (en) Capped shallow trench isolation and method of formation
US7118972B2 (en) Method of manufacture of a semiconductor device
US7348245B2 (en) Semiconductor device and a method of manufacturing the same
JP2001094075A (ja) 不揮発性半導体記憶装置およびその製造方法
US20170125603A1 (en) Integration Of Metal Floating Gate In Non-Volatile Memory
US6479339B2 (en) Use of a thin nitride spacer in a split gate embedded analog process
CN100334732C (zh) 半导体集成电路器件及其制造方法
US9418864B2 (en) Method of forming a non volatile memory device using wet etching
US6818514B2 (en) Semiconductor device with dual gate oxides
KR100587186B1 (ko) 저전력 플래시 메모리 셀 및 방법
US6511887B1 (en) Method for making FET gate oxides with different thicknesses using a thin silicon nitride layer and a single oxidation step
US6627510B1 (en) Method of making self-aligned shallow trench isolation
US7588978B2 (en) Method for forming semiconductor device
US11616145B2 (en) FINFET stack gate memory and method of forming thereof
US6255167B1 (en) Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
US6627942B2 (en) Self-aligned floating gate poly for a flash E2PROM cell
CN112786598B (zh) FinFET堆叠栅存储器的形成方法
US6586313B2 (en) Method of avoiding the effects of lack of uniformity in trench isolated integrated circuits
KR20010055525A (ko) 얕은 트렌치 소자분리 방법
CN112786598A (zh) FinFET堆叠栅存储器与其形成方法
KR100545182B1 (ko) 반도체 소자 및 그의 제조 방법
WO2002025701A2 (en) Body-tied silicon on insulator semiconductor device structure and method therefor
KR19990017051A (ko) 반도체 장치의 소자분리 방법
CN116387316A (zh) 半导体结构的制作方法、半导体结构及存储器

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEGRATED SILICON SOLUTION INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WANG, HSINGYA ARTHUR;REEL/FRAME:052080/0187

Effective date: 20200113

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION