US20160141289A1 - Semiconductor device and method of manufacturing same - Google Patents

Semiconductor device and method of manufacturing same Download PDF

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Publication number
US20160141289A1
US20160141289A1 US14/934,745 US201514934745A US2016141289A1 US 20160141289 A1 US20160141289 A1 US 20160141289A1 US 201514934745 A US201514934745 A US 201514934745A US 2016141289 A1 US2016141289 A1 US 2016141289A1
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Prior art keywords
region
element isolation
semiconductor substrate
isolation region
gate electrode
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Inventor
Hideki Aono
Tetsuya Yoshida
Makoto Ogasawara
Shinichi Okamoto
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AONO, HIDEKI, OGASAWARA, MAKOTO, OKAMOTO, SHINICHI, YOSHIDA, TETSUYA
Publication of US20160141289A1 publication Critical patent/US20160141289A1/en
Priority to US16/291,620 priority Critical patent/US10651094B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, which are suited for use in, for example, a semiconductor device having an STI-type element isolation region and MISFET and a method of manufacturing the device.
  • the STI type element isolation region can be formed by burying an insulating film in a trench formed in a semiconductor substrate. An MISFET and the like are then formed in an active region of the semiconductor substrate surrounded by the element isolation region.
  • Patent Document 1 describes a technology of introducing, in forming an n type SOI transistor in an element region surrounded by a LOCOS layer, a parasitic channel preventing boron in an end portion of a channel region and introducing, as a diffusion reducing atom, fluorine or nitrogen in the end portion of the channel region.
  • Patent Document 2 describes a technology of relaxing an electric field between a gate electrode and an end portion of a drain to suppress generation of a leakage current.
  • Patent Document 3 describes a technology of carrying out channel doping with an n type impurity and also fluorine implantation.
  • Patent Document 4 Japanese Unexamined Patent Application Publication No. Hei 11(1999)-297812 (Patent Document 4) describes a technology relating to a semiconductor device using STI.
  • Patent Document 5 Japanese Unexamined Patent Application Publication No. 2004-207564 describes a technology relating to a semiconductor device using STI.
  • Non-patent Documents 1 and 2 describe a technology relating to NBTI.
  • a semiconductor device has a semiconductor substrate, an element isolation region buried in a trench formed in the semiconductor substrate, and a first gate electrode for first MISFET formed on the semiconductor substrate in a first active region surrounded by the element isolation region via a first gate insulating film.
  • the element isolation region is comprised mainly of silicon oxide; the trench in the semiconductor substrate has a nitrided inner surface; and a portion of the first gate electrode extends over the element isolation region. Below the first gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of the first MISFET.
  • a semiconductor device has a semiconductor substrate, an element isolation region buried in a trench formed in the semiconductor substrate, and a first gate electrode for first MISFET formed on the semiconductor substrate in a first active region surrounded by the element isolation region via a first gate insulating film.
  • the element isolation region is comprised mainly of silicon oxide; the trench in the semiconductor substrate has, on an inner surface thereof, a nitride layer obtained by nitriding the inner surface; and a portion of the first gate electrode extends over the element isolation region. Below the first gate electrode, the nitride layer is not formed at a boundary between the upper portion of the semiconductor substrate in the first active region and the upper portion of the element isolation region.
  • a method of manufacturing a semiconductor device includes the steps of: (a) providing a semiconductor substrate, (b) forming a trench in the semiconductor substrate, (c) nitriding an inner surface of the trench in the semiconductor substrate, and (d) after the step (c), forming an element isolation region comprised mainly of silicon oxide in the trench.
  • the method of manufacturing a semiconductor device further includes the steps of: (e) ion-implanting fluorine into the vicinity of a boundary between the element isolation region and the semiconductor substrate in the first active region surrounded by the element isolation region, and (f) after the step (e), forming a first gate electrode for first MISFET on the semiconductor substrate in the first active region via a first gate insulating film.
  • a method of manufacturing a semiconductor device includes the steps of: (a) providing a semiconductor substrate, (b) forming a trench in the semiconductor substrate, (c) nitriding an inner surface of the trench in the semiconductor substrate to form a nitride layer, and (d) after the step (c), forming an element isolation region comprised mainly of silicon oxide in the trench.
  • the method of manufacturing a semiconductor device further includes the steps of: (e) oxidizing an upper portion of the nitride layer at a boundary between the element isolation region and the semiconductor substrate in a first active region surrounded by the element isolation region, and (f) after the step (e), forming a first gate electrode for first MISFET on the semiconductor substrate in the first active region via a first gate insulating film.
  • a semiconductor device having improved reliability can be provided.
  • FIG. 1 is a fragmentary plan view of a semiconductor device according to First Embodiment
  • FIG. 2 is another fragmentary plan view of the semiconductor device according to First Embodiment
  • FIG. 3 is a fragmentary cross-sectional view of the semiconductor device according to First Embodiment
  • FIG. 4 is another fragmentary cross-sectional view of the semiconductor device of First Embodiment.
  • FIG. 5 is a fragmentary cross-sectional view of the semiconductor device according to First Embodiment during a manufacturing step thereof;
  • FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5 ;
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6 ;
  • FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7 ;
  • FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8 ;
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9 ;
  • FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10 ;
  • FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 11 ;
  • FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11 ;
  • FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 13 ;
  • FIG. 15 is a fragmentary plan view of the semiconductor device during a manufacturing step similar to that of FIG. 13 ;
  • FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13 ;
  • FIG. 17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 16 ;
  • FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16 ;
  • FIG. 19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 18 ;
  • FIG. 20 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18 ;
  • FIG. 21 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 20 ;
  • FIG. 22 is a fragmentary cross-sectional view of a semiconductor device of First Investigation Example
  • FIG. 23 is a fragmentary cross-sectional view of a semiconductor device of Second Investigation Example.
  • FIG. 24 is a graph showing the gate-width dependence of NBTI characteristics of the semiconductor device of First Investigation Example and the semiconductor device of Second Investigation Example;
  • FIG. 25 is a fragmentary plan view of a semiconductor device of another mode
  • FIG. 26 is a fragmentary cross-sectional view of a semiconductor device of First Modification Example
  • FIG. 27 is another fragmentary cross-sectional view of the semiconductor device of First Modification Example
  • FIG. 28 is a fragmentary cross-sectional view of a semiconductor device of Second Modification Example
  • FIG. 29 is another fragmentary cross-sectional view of the semiconductor device of Second Modification Example.
  • FIG. 30 is a fragmentary plan view of a semiconductor device of Second Embodiment.
  • FIG. 31 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment.
  • FIG. 32 is another fragmentary cross-sectional view of the semiconductor device of Second Embodiment.
  • FIG. 33 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof;
  • FIG. 34 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 33 ;
  • FIG. 35 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 33 ;
  • FIG. 36 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 35 ;
  • FIG. 37 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 35 ;
  • FIG. 38 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step similar to that of FIG. 37 ;
  • FIG. 39 is a fragmentary cross-sectional view of a semiconductor device of Third Modification Example.
  • FIG. 40 is another fragmentary cross-sectional view of the semiconductor device of Third Modification Example.
  • FIG. 41 is a fragmentary cross-sectional view of a semiconductor device of Fourth Modification Example.
  • FIG. 42 is another fragmentary cross-sectional view of the semiconductor device of Fourth Modification Example.
  • a description may be made after divided in a plurality of sections or embodiments if necessary for the sake of convenience. These sections or embodiments are not independent from each other unless otherwise particularly specified, but one of them may be a modification example, details, complementary description, or the like of a part or whole of the other one.
  • the number when a reference is made to the number (including the number, value, amount, range, or the like) of a component, the number is not limited to a specific number but may be more or less than the specific number, unless otherwise particularly specified or principally apparent that the number is limited to the specific number.
  • the constituent component (including component step or the like) is not always essential unless otherwise particularly specified or principally apparent that it is essential.
  • the constituent component when a reference is made to the shape, positional relationship, or the like of the constituent component, that substantially approximate or analogous to it is also embraced unless otherwise particularly specified or principally apparent that it is not. This also applies to the above-mentioned number, range, or the like.
  • FIGS. 1 and 2 are fragmentary plan views of the semiconductor device of the present embodiment.
  • FIGS. 3 and 4 are fragmentary cross-sectional views of the semiconductor device of the present embodiment.
  • the cross-sectional view taken along the line A 1 -A 1 of FIG. 1 nearly corresponds to FIG. 3
  • the cross-sectional view taken along the line B 1 -B 1 of FIG. 2 nearly corresponds to FIG. 4 .
  • FIGS. 1 and 2 show the same plane region, but in FIG. 2 , a fluorine implanted region (FR) is hatched with dots and the position of a gate electrode GE 1 is shown by a two-dot chain line.
  • FIG. 1 and 2 corresponds to a gate length direction of the gate electrode GE 1 so that it corresponds to a channel length direction of a channel region formed below the gate electrode GE 1 .
  • the direction Y shown in FIGS. 1 and 2 corresponds to a gate width direction of the gate electrode GE 1 so that it corresponds to a channel width direction of a channel region formed below the gate electrode GE 1 .
  • FIG. 3 is a cross-sectional view along the direction X and FIG. 4 is a cross-sectional view along the direction Y.
  • the gate width W 1 of the gate electrode GE 1 is indicated by W 1 .
  • the semiconductor device of the present embodiment has an STI (shallow trench isolation) type element isolation region and an MISFET (metal insulator semiconductor field effect transistor).
  • STI shallow trench isolation
  • MISFET metal insulator semiconductor field effect transistor
  • FIGS. 1 to 4 The structure of the semiconductor device of the present embodiment will hereinafter be described specifically referring to FIGS. 1 to 4 .
  • a semiconductor substrate SB has an MISFET on the main surface thereof.
  • the semiconductor substrate made of, for example, p type single crystal silicon having specific resistance of from about 1 to 10 ⁇ cm has active regions AC 1 defined by an element isolation region ST made of an insulator.
  • the active regions AC 1 are each surrounded by the element isolation region ST. This means that the active region AC 1 corresponds to a plane region not having the element isolation region ST therein and having a periphery surrounded by the element isolation region ST.
  • the semiconductor substrate SB in the active region AC 1 has a MISFET, more specifically, a p channel MISFETQp. Described specifically, the semiconductor substrate SB in the active region AC 1 has therein an n well NW and the n well NW has, on the surface thereof, a gate electrode GE 1 of the p channel MISFETQp via an insulating film GF functioning as a gate insulating film of the p channel MISFETQp.
  • the gate electrode GE 1 is made of a conductive film.
  • the gate electrode GE 1 may be obtained as a silicon gate electrode by forming the electrode GE 1 from a polysilicon film.
  • the polysilicon film preferably has a resistance reduced by introducing therein an impurity.
  • the insulating film GF is made of, for example, a thin silicon oxide film.
  • the gate electrode GE 1 has, on the side wall thereof, a sidewall spacer SW made of an insulating film.
  • the sidewall spacer SW can be regarded as a sidewall insulating film.
  • the n well NW has therein a source/drain region (semiconductor region for source or drain) SD 1 having an LDD (lightly doped drain) structure for the p channel MISFETQp.
  • the gate electrode GE 1 has on both sides of the gate electrode GE 1 (both sides in the gate length direction) the source/drain region SD 1 .
  • the source/drain region SD 1 is comprised of a p ⁇ type semiconductor region (extension region) E 1 and a p + type semiconductor region H 1 having a higher impurity concentration.
  • the p + type semiconductor region H 1 has a junction depth deeper and an impurity concentration higher than those of the p ⁇ type semiconductor region E 1 .
  • the p ⁇ type semiconductor region E 1 having a lower concentration lies below the sidewall spacer SW so as to be adjacent to a channel region (substrate region immediately below the gate electrode GE 1 ) of the p channel MISFETQp, while the p + type semiconductor region H 1 having a higher concentration lies so as to be adjacent to the p ⁇ type semiconductor region E 1 having a lower concentration and separated from the channel region of the p channel MISFETQp by a distance corresponding to the p ⁇ type semiconductor region E 1 .
  • the channel region (channel formation region) of the MISFETQp lies, in the semiconductor substrate SB (n well NW) in the active region AC 1 , below the insulating film GF below the gate electrode GE 1 . This means that the channel region of the MISFETQp is formed in a portion of the semiconductor substrate (SB) facing to the gate electrode GE 1 via the insulating film GF.
  • the MISFETQp (including the gate insulating film (insulating film GF), the gate electrode GE 1 , and the source/drain region SD 1 configuring the MISFETQp) lies in the active region AC 1 defined (surrounded) by the element isolation region ST. A portion of the gate electrode GE 1 however extends also over the element isolation region ST (the element isolation region ST surrounding the active region AC 1 ).
  • a portion of the gate electrode GE 1 extends over the element isolation region ST and the element isolation region ST and the gate electrode GE 1 have therebetween the insulating film GF.
  • the insulating film GF is formed by thermal oxidation, however, the element isolation region ST and the gate electrode GE do not have therebetween the insulating film GF and the element isolation region ST has the gate electrode GE 1 directly thereon.
  • the p + type semiconductor region H 1 or the gate electrode GE 1 has thereon a metal silicide layer SL formed by salicide (self aligned silicide) technology or the like.
  • the metal silicide layer SL is made of, for example, a cobalt silicide layer, a nickel silicide layer, or a platinum-added nickel silicide layer.
  • the metal silicide layer SL contributes to reduction in diffusion resistance or contact resistance.
  • the semiconductor substrate SB has thereon an interlayer insulating film IL 1 as an insulating film so as to cover the gate electrode GE 1 and the sidewall spacer SW.
  • the interlayer insulating film IL 1 is made of a single silicon oxide film or a stacked film comprised of a silicon nitride film and a silicon oxide film formed on the silicon nitride film with a thickness greater than that of the silicon nitride film.
  • the interlayer insulating film IL 1 has a planarized upper surface.
  • the interlayer insulating film IL 1 has a contact hole (opening portion, through-hole) CT and the contact hole CT has therein a conductive plug (contact plug) PG as a conductor portion for coupling.
  • the plug PG is comprised of a thin barrier conductor film formed on the bottom portion and side wall (side surface) of the contact hole CT and a main conductor film formed on this barrier conductor film to fill the contact hole CT.
  • the barrier conductor film and the main conductor film configuring the plug PG are shown as one film.
  • the barrier conductor film configuring the plug PG may be, for example, a titanium film, a titanium nitride film, or a stacked film of them, while the main conductor film configuring the plug PG may be a tungsten film.
  • the contact hole CT and the plug PG buried therein are formed over the p + type semiconductor region H 1 , the gate electrode GE 1 , and the like.
  • the plug PG placed on the p + type semiconductor region H 1 is electrically coupled to this p + type semiconductor region H 1 and the plug PG placed over the gate electrode GE 1 is electrically coupled to this gate electrode GE 1 .
  • the interlayer insulating film IL 1 having the plug PG buried therein has a wiring M 1 on the film.
  • the wiring M 1 is, for example, a damascene wiring (buried wiring) and it is buried in a wiring trench provided in the insulating film IL 2 formed on the interlayer insulating film IL 1 .
  • the wiring M 1 has thereover another wiring and another insulating film, but illustration and description on them are omitted here.
  • the wiring M 1 and wirings thereover can be formed not only as damascene wiring (buried wiring) but also formed by pattering a wiring conductor film.
  • a tungsten wiring, aluminum wiring, or the like can be used.
  • the element isolation region (STI insulating film, STI isolation film) ST is formed by STI (shallow trench isolation).
  • STI is a method of forming a trench (element isolation trench) in the main surface of a semiconductor substrate and then filling the trench with an insulating film.
  • the element isolation region ST is therefore comprised of an insulating film buried in a trench (element isolation trench) TR formed in the semiconductor substrate SB.
  • the insulating film buried in the trench TR is, more specifically, a silicon oxide film so that the element isolation region ST is comprised of a silicon oxide film buried in the trench TR formed in the semiconductor substrate SB.
  • the trench TR in the semiconductor substrate SB has a nitrided inner surface (side surface and bottom surface).
  • the semiconductor substrate SB configuring the inner surface of the trench TR has a nitrided surface and it has, on the surface thereof, a nitride layer (nitride film) SN.
  • the nitride layer SN is therefore adjacent to the side surface and bottom surface of the element isolation region ST (silicon oxide film buried in the trench TR).
  • the nitride layer SN is formed by, prior to filling the trench TR with a silicon oxide film, nitriding the surface (exposed surface) of the semiconductor substrate SB exposed from the inner surface of the trench TR.
  • the nitride layer SN is made of silicon nitride.
  • the nitride layer SN is preferably formed on the entirety of the inner surface (side surface and bottom surface) of the trench TR.
  • the semiconductor substrate SB including the element isolation region ST has, in the surface layer thereof, fluorine (F) implanted.
  • the fluorine (F) implanted region (which will hereinafter be called “fluorine implanted region FR”) is hatched with dots in FIGS. 2 to 4 .
  • Fluorine (F) implanted in the surface layer portion of the semiconductor substrate SB is, in plan view, not implanted in the entirety of the active region AC 1 but implanted into the vicinity of a boundary between the active region AC 1 and the element isolation region ST (meaning the outer peripheral portion of the active region AC 1 ).
  • Fluorine (F) is also implanted into the surface layer portion of the element isolation region ST.
  • the element isolation region ST With respect to the implantation in the element isolation region ST, it may be implanted, in plan view, only into the vicinity of a boundary between the active region AC 1 and the element region ST or may be implanted into the entirety of the element isolation region ST. Due to the presence of the nitride layer SN between the element isolation region ST and the semiconductor substrate SB in the active region AC 1 , fluorine (F) is also implanted into an upper portion of the nitride layer SN present between the element isolation region ST and the semiconductor substrate SB in the active region AC 1 .
  • fluorine (F) is also implanted into an upper portion of the nitride layer SN present between the element isolation region ST and the semiconductor substrate SB in the active region AC 1 .
  • fluorine (F) is implanted in order to suppress or prevent deterioration of deterioration in NBTI characteristics attributable to the nitride layer SN. It is important that in a region overlapping with the gate electrode GE 1 in plan view, fluorine (F) is introduced (implanted) into the vicinity of a boundary between the element isolation region ST and the channel region (channel region of the MISFETQp).
  • the fluorine implanted region FR may therefore be formed not only in a region hatched with dots in FIG. 2 but may be formed in a region shown later in FIG. 25 .
  • FIGS. 5 to 21 are fragmentary cross-sectional views or fragmentary plan views of the semiconductor device of the present embodiment during manufacturing steps thereof.
  • FIG. 15 is a fragmentary plan view
  • FIGS. 5 to 14 and FIGS. 16 to 21 are fragmentary cross-sectional views.
  • FIGS. 11, 13, 16, 18, and 20 show a cross-section corresponding to FIG. 3 , that is, a cross-section at a position corresponding to the line A 1 -A 1 in FIG. 1 ; and
  • FIGS. 5 to 10, 12, 14, 17, 19, and 21 show a cross-section corresponding to FIG. 4 , that is, a cross-section at a position corresponding to the line B 1 -B 1 in FIG. 1 .
  • FIG. 15 is a plan view but to facilitate understanding of it, a photoresist pattern is hatched with oblique lines.
  • a semiconductor substrate (semiconductor wafer) SB composed of, for example, p type single crystal silicon having a specific resistance of from about 1 to 10 ⁇ cm is provided (prepared).
  • an insulating film ZM is formed on the main surface (entire main surface) of the semiconductor substrate SB.
  • the insulating film ZM is made of, for example, a silicon nitride film and can be formed, for example, using CVD (chemical vapor deposition) (for example, thermal CVD).
  • CVD chemical vapor deposition
  • a silicon nitride film may be formed as the insulating film ZM on the resulting oxide film by CVD.
  • a photoresist layer is applied onto the main surface (entire main surface) of the semiconductor substrate SB, that is, onto the insulating film ZM and then the resulting photoresist layer is exposed and developed to form a photoresist pattern (resist pattern, resist layer, mask layer) PR 1 as a mask layer as shown in FIG. 5 .
  • the photoresist pattern PR 1 has an opening portion OP 1 in a trench TR formation region.
  • the trench TR is an element isolation trench, that is, a trench for the formation of the element isolation region ST.
  • the trench TR extends in the insulating film ZM and the semiconductor substrate SB. This means that the trench TR goes through the insulating film ZM and the bottom portion of the trench TR reaches the middle of the thickness of the semiconductor substrate SB.
  • the depth of the trench TR in the semiconductor substrate SB is, for example, from about 300 to 700 nm.
  • the surface (exposed surface) of the semiconductor substrate SB exposed on the inner surface (side surface and bottom surface) of the trench TR is nitrided.
  • This nitriding treatment of the semiconductor substrate SB can be achieved, for example, by nitrogen annealing, more specifically, heat treatment in a nitrogen atmosphere.
  • the inner surface (side surface and bottom surface) of the trench TR in the semiconductor substrate SB is nitrided.
  • the surface (exposed surface) of the semiconductor substrate SB configuring the inner surface of the trench TR is nitrided and a nitride layer (nitride film) SN is formed as shown in FIG. 7 .
  • the nitride layer SN is made of silicon nitride.
  • the nitride layer SN is formed on the entire inner surface (side surface and bottom surface) of the trench TR.
  • the thickness of the nitride layer SN can be set at, for example, from about 0.1 to 1.0 nm. Since the upper surface of the semiconductor substrate SB outside the trench TR is covered with the insulating film ZM, it can be prevented from being nitrided by this nitriding treatment.
  • a silicon nitride film may be deposited on the inner surface of the trench TR by using CVD or the like, but in order to prevent oxidation and expansion thereby of the element isolation region ST which will be formed later, it is preferred not to deposit a silicon nitride film by CVD or the like but to nitride the inner surface of the trench TR to form the nitride layer SN.
  • CVD chemical vapor deposition
  • the width of the trench TR decreases.
  • a silicon nitride film cannot be formed on the inner surface of the trench TR successfully by depositing the silicon nitride film on the inner surface of the trench TR by using CVD or the like instead of nitriding the inner surface of the trench TR to form the nitride layer SN.
  • the nitride layer SN is formed by nitriding the inner surface of the trench TR.
  • an insulating film UZ is formed (deposited) on the main surface (entire main surface) of the semiconductor substrate SB, that is, on the insulating film ZM so as to fill the trench TR.
  • the insulating film UZ is preferably made of a silicon oxide film and can be formed, for example, by CVD.
  • CVD plasma CVD is suited and HDP (high density plasma)-CVD is particularly suited.
  • the insulating film UZ is formed so as to be thick enough to fill the trench TR.
  • the insulating film UZ is polished by CMP (chemical mechanical polishing). By this polishing, as shown in FIG. 9 , the insulating film UZ outside the trench TR is removed and the insulting film UZ is left in the trench TR.
  • CMP chemical mechanical polishing
  • the upper surface of the insulating film ZM is exposed and the upper surface of the insulating film UZ remaining in the trench TR has a height almost equal to that of the upper surface of the insulating film ZM.
  • This CMP treatment performed under conditions under which the polishing rate of the insulating film ZM (silicon nitride film) is smaller than that of the insulating film UZ (silicon oxide film) enables the insulating film ZM to function as a stopper film (or protective film) for the CMP treatment.
  • an upper portion (upper surface) of the insulating film UZ in the trench TR is etched back by dry etching to retract the upper surface of the insulating film UZ in the trench TR.
  • This etching is performed preferably under etching conditions under which an etching rate of the insulating film ZM (silicon nitride film) becomes smaller than that of the insulating film UZ (silicon oxide film).
  • an etching rate of the insulating film ZM silicon nitride film
  • UZ silicon oxide film
  • the height of the upper surface of the insulating film UZ in the trench TR becomes lower than the height of the upper surface (here, the interface between the semiconductor substrate SB and the insulating film ZM) of the semiconductor substrate SB.
  • the height of the upper surface of the insulating film UZ in the trench TR is almost equal to or slightly higher than the height of the upper surface of the semiconductor substrate SB.
  • the insulating film ZM is removed by wet etching.
  • This wet etching is performed preferably under the conditions under which an etching rate of the insulating film UZ (silicon oxide film) becomes smaller than the etching rate of the insulating film ZM (silicon nitride film).
  • This wet etching can then selectively remove the insulating film ZM.
  • a silicon oxide film is formed on the upper surface of the semiconductor substrate SB prior to the formation of the insulating film ZM (silicon nitride film) in FIG. 5
  • the silicon oxide film (silicon oxide film below the insulating film ZM) may be removed. By this removal, the upper surface (surface, Si surface) of the semiconductor substrate SB is exposed.
  • the insulating film UZ is polished using CMP to obtain the structure shown in FIG. 9 and then, the structure shown in FIGS. 11 and 12 is obtained by etching back the insulating film UZ and then, removing the insulating film ZM.
  • the insulating film ZM can be polished and removed when the insulating UZ is polished using CMP. In this case, when the CMP step is completed, not the structure shown in FIG. 9 but the structure shown in FIGS. 11 and 12 can be obtained.
  • the element isolation region ST comprised of the insulating film UZ buried in the trench TR of the semiconductor substrate SB is formed in such a manner.
  • the element isolation region ST is formed by STI (shallow trench isolation).
  • the nitride layer SN is formed by nitriding the inner surface of the trench TR in the semiconductor substrate SB in the step shown in FIG. 7 so that the side surface and the bottom surface of the element isolation region ST are contiguous to the nitride layer SN. This means that the side surface and bottom surface of the element isolation region ST is covered with the nitride layer SN.
  • the active region (AC 1 ) is defined (partitioned) by the element isolation region ST in the semiconductor substrate SB and various semiconductor elements (MISFETQp, here) will be formed in this active region (AC 1 ) by steps performed later.
  • the element isolation region ST is formed by forming an element isolation trench (TR) in the semiconductor substrate SB in advance, nitriding the inner surface of the element isolation trench (TR), and filling the element isolation trench (TR) with an insulating film (preferably, a silicon oxide film).
  • an insulating film preferably, a silicon oxide film
  • FIG. 15 is a plan view just after formation of the photoresist pattern PR 2 .
  • the opening portion OP 2 of the photoresist pattern PR 2 has planar shape and size slightly greater than those of the opening portion OP 1 of the photoresist pattern PR 1 .
  • the opening portion OP 2 of the photoresist pattern PR 2 therefore includes, in plan view, the element isolation region ST and it has planar shape and size slightly greater than those of the element isolation region ST.
  • the photoresist pattern PR 2 covers the active region AC 1 , but in plan view, the photoresist pattern PR 2 is included in the active region AC 1 and has planar shape and size slightly smaller than those of the active region AC 1 .
  • the element isolation region ST, the nitride layer SN, and the outer peripheral portion of the active region AC 1 are therefore exposed from the opening portion OP 2 of the photoresist pattern PR 2 .
  • ion implantation IM 1 fluorine (F) is ion-implanted into the semiconductor substrate SB (including the element isolation region ST).
  • This ion implantation will hereinafter be called “ion implantation IM 1 ” and in FIGS. 13 and 14 , ion implantation IM 1 is schematically shown by an arrow.
  • fluorine (F) is ion-implanted into the semiconductor substrate SB exposed from the opening portion OP 2 of the photoresist pattern PR 2 .
  • fluorine (F) is ion-implanted into the surface layer portion of the element isolation region ST exposed from the opening portion OP 2 of the photoresist pattern PR 2 and an upper portion of the nitride layer SN exposed from the opening portion OP 2 of the photoresist pattern PR 2 .
  • fluorine (F) is ion-implanted also into an upper portion of a substrate region (the semiconductor substrate SB at the outer periphery of the active region AC 1 ) adjacent to the nitride layer SN.
  • a fluorine implanted region FR a region in which fluorine (F) has been implanted is hatched with dots.
  • fluorine (F) When viewed in the depth direction (direction substantially perpendicular to the main surface of the semiconductor substrate SB), fluorine (F) is ion-implanted into a region within depth L 1 (implantation depth) from the main surface of the semiconductor substrate SB.
  • the implantation depth of fluorine (F) can be set at, for example, from about 10 to 500 nm. This means that the depth position of the bottom surface (lower surface) of the fluorine implanted region FR can be set at from about 10 to 500 nm from the main surface of the semiconductor substrate SB.
  • a distance (interval) L 2 from the interface between the nitride layer SN and the substrate region to the end portion of the fluorine implanted region FR on the side of the active region AC 1 can be set at, for example, from about 10 to 500 nm. This means that in the semiconductor substrate SB in the active region AC 1 , fluorine (F) is implanted into a region within the distance (interval) L 2 from the nitride layer SN and fluorine (F) is not implanted into a region distant from the distance (interval) L 2 or more from the nitride layer SN.
  • the distance L 2 is a distance (interval) in a direction parallel to the main surface of the semiconductor substrate SB.
  • the concentration of the fluorine (F) thus implanted can be set at, for example, from about 1 ⁇ 10 18 to 1 ⁇ 10 21 /cm 3 .
  • substrate region corresponds to a portion of the semiconductor substrate SB, more specifically, a region made of single crystal silicon configuring the semiconductor substrate SB.
  • n well NW having a predetermined depth from the main surface of the semiconductor substrate SB is formed in the active region AC 1 defined by the element isolation region ST as shown in FIGS. 16 and 17 .
  • the n well NW can be formed by ion implantation of an n type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate SB.
  • a gate electrode GE 1 is formed on the surface of the semiconductor substrate SB, that is, on the surface of the n well NW via an insulating film GF. This step can be performed specifically in the following manner.
  • an insulating film GF for gate insulating film is formed on the surface of the semiconductor substrate SB, that is, on the surface of the n well NW.
  • the insulating film GF is made of, for example, a thin silicon oxide film and can be formed, for example, by thermal oxidation.
  • the insulating film GF is formed by oxidation treatment (for example, thermal oxidation)
  • the insulating film GF is formed on the semiconductor substrate SB in the active region AC 1 , that is, on the n well NW but the insulating film GF is not formed on the element isolation region ST.
  • a polysilicon film is formed as a conductive film for gate electrode on the main surface (entire main surface) of the semiconductor substrate SB.
  • This polysilicon film has an impurity introduced therein during or after film formation and therefore has a low resistivity.
  • a photoresist pattern (not shown) on the polysilicon film by photolithography
  • the polysilicon film is etched and patterned by dry etching with the resulting photoresist pattern as an etching mask.
  • a gate electrode GE 1 made of the patterned conductive film (here, the polysilicon film) can be formed as shown in FIGS. 16 and 17 .
  • the gate electrode GE 1 is formed on the semiconductor substrate SB (n well NW) via the insulating film GF.
  • the photoresist pattern is then removed.
  • the insulating film GF remains below the gate electrode GE 1 and becomes a gate insulating film.
  • a p ⁇ type semiconductor region (extension region) E 1 is formed by ion implantation of a p type impurity such as boron (B) into a region, in the n well NW, on both sides of the gate electrode GE 1 .
  • the gate electrode GE 1 can function as an ion implantation preventive mask, no impurity is ion-implanted into a region immediately below the gate electrode GE 1 in the n well NW and the p ⁇ type semiconductor region E 1 is formed in self alignment with the sidewall of the gate electrode GE 1 .
  • the p ⁇ type semiconductor region E 1 is not formed immediately below the gate electrode GE 1 so that it is shown in FIG. 18 but not shown in FIG. 19 .
  • a sidewall spacer SW made of, for example, silicon oxide, silicon nitride, or a stacked film of these insulating films is formed, as a sidewall insulating film, on the side wall of the gate electrode GE 1 .
  • the sidewall spacer SW can be formed, for example, by depositing an insulating film (a silicon oxide film, a silicon nitride film, or a stacked film of them) on the main surface (entire main surface) of the semiconductor substrate SB and then anisotropically etching the insulating film.
  • a p + type semiconductor region H 1 is formed by ion implantation of an n type impurity such as phosphorus (P) or arsenic (As) into a region, in the n well NW, on both sides of the gate electrode GE 1 and the sidewall spacer SW.
  • an n type impurity such as phosphorus (P) or arsenic (As)
  • the gate electrode GE 1 and the sidewall spacer SW on the side wall thereof can function as an ion implantation preventive mask, no impurity is ion implanted into a region, in the n well NW, immediately below the gate electrode GE 1 and immediately below the sidewall spacer SW on the side wall of the gate electrode GE 1 .
  • the p + type semiconductor region H 1 is therefore formed in self alignment with the side surface surface (surface on the side opposite to the side contiguous to the gate electrode GE 1 ) of the sidewall spacer SW on the side wall of the gate electrode GE 1 .
  • the p + type semiconductor region H 1 is not formed immediately below the gate electrode GE 1 so that it is shown in FIG. 18 but not shown in FIG.
  • the p + type semiconductor region H 1 has a junction depth deeper and an impurity concentration higher than those of the p ⁇ type semiconductor region E 1 .
  • the p ⁇ type semiconductor region E 1 having a low impurity concentration and the p + type semiconductor region H 1 having a high impurity concentration configure a source/drain region SD 1 having an LDD structure.
  • Annealing treatment (heat treatment) is then performed for activating the thus-introduced impurities.
  • a p channel MISFETQp is formed as a field effect transistor in the active region AC 1 defined by the element isolation region ST.
  • a metal silicide layer SL is formed on the surface (surface layer portion) of the gate electrode GE 1 and the p + type semiconductor region H 1 by salicide technology.
  • This metal silicide layer SL can be formed by depositing a metal film, for example, a cobalt (Co) film, a nickel (Ni) film, or a platinum-nickel alloy film on the gate electrode GE 1 and the p + type semiconductor region H 1 so as to cover them, followed by heat treatment. An unreacted portion of the metal film is then removed.
  • a metal film for example, a cobalt (Co) film, a nickel (Ni) film, or a platinum-nickel alloy film
  • an interlayer insulating film IL 1 is formed on the main surface (entire main surface) of the semiconductor substrate SB so as to cover the gate electrode GE 1 and the sidewall spacer SW. Then, the upper surface of the interlayer insulating film IL 1 may be polished or the like by CMP to planarize the upper surface of the interlayer insulating film IL 1 .
  • the interlayer insulating film IL 1 is dry etched to form a contact hole CT in the interlayer insulating film IL 1 .
  • a conductive plug PG composed mainly of, for example, tungsten (W) is formed in the contact hole CT.
  • the plug PG is formed, for example, by forming a barrier conductor film (for example, a titanium film, a titanium nitride film, or a stacked film of them) on the interlayer insulating film IL 1 including the inside (bottom portion and side wall) of the contact hole; forming a main conductor film made of a tungsten film or the like on the barrier conductor film so as to fill the contact hole CT therewith; and removing an unnecessary portion of the main conductor film and the barrier conductor film outside the contact hole CT by CMP or etch-back.
  • a barrier conductor film for example, a titanium film, a titanium nitride film, or a stacked film of them
  • an insulating film IL 2 is formed on the interlayer insulating film IL 1 having the plug PG buried therein.
  • the insulating film IL 2 may be formed as a single-layer insulating film or a stacked film of a plurality of insulating films.
  • a wiring M 1 which is a first-layer wiring is formed by the single damascene process. Described specifically, the wiring M 1 can be formed in the following manner. First, a wiring trench is formed in the insulating film IL 2 by using photolithography and dry etching. Then, after formation of a barrier conductor film on the insulating film IL 2 including the bottom surface and the inner wall of the wiring trench, a thin copper film is deposited as a seed film on the barrier conductor film by sputtering or the like. A copper plating film is then deposited as a main conductor film on the seed film by electroplating and the wiring trench is filled with this copper plating film.
  • Second and upper wirings are thereafter formed by the dual damascene process, but illustration and description of them are omitted.
  • the wiring M 1 and wirings thereabove are not limited to the damascene wiring but can be formed by patterning a wiring conductor film. For example, they may be formed as a tungsten wiring or aluminum wiring.
  • the semiconductor device of the present embodiment is manufactured as described above.
  • FIG. 22 is a fragmentary cross-sectional view of a semiconductor device of First Investigation Example investigated by the present inventors and FIG. 23 is a fragmentary cross-sectional view of a semiconductor device of Second Investigation Example investigated by the present inventors. Each shows a cross-section corresponding to FIG. 4 of the present embodiment.
  • the trench TR does not have a nitrided inner surface (side surface and bottom surface).
  • a step (the step of FIG. 7 ) of nitriding the inner surface (side surface and bottom surface) of the trench TR in the semiconductor substrate SB is not performed before formation of a silicon oxide film (insulating film UZ) which fills a trench TR formed in the semiconductor substrate SB.
  • a film corresponding to the nitride layer SN is therefore not formed between the element isolation region ST and the semiconductor substrate SB in the semiconductor device of First Investigation Example shown in FIG. 22 and the element isolation region ST and the substrate region are adjacent to each other.
  • the semiconductor device of First Investigation Example shown in FIG. 22 since a step (step shown in FIGS. 13 to 15 ) corresponding to the ion implantation IM 1 is not performed, the semiconductor device of First Investigation Example shown in FIG. 22 does not have therein a region corresponding to the fluorine implanted region FR.
  • the element isolation region ST in the trench TR may be re-oxidized and thereby expand in various steps after formation of the element isolation region ST.
  • the element isolation region ST which has filled the trench TR inevitably expands. Expansion of the element isolation region ST may cause crystal detects in the semiconductor substrate SB in the active region and as a result, the semiconductor device thus manufactured may have deteriorated reliability.
  • the trench TR of the semiconductor substrate SB has a nitrided inner surface (side surface and bottom surface). This means that in manufacturing steps of the semiconductor device of Second Investigation Example, after formation of the trench TR in the semiconductor substrate SB but before formation of the silicon oxide film (insulating film UZ) for filling the trench TR, the inner surface (side surface and bottom surface) of the trench TR in the semiconductor substrate SB is nitrided.
  • the element isolation region ST and the semiconductor substrate SB have therebetween the nitride layer SN.
  • the nitride layer SN extends over the entirety of the inner surface of the trench TR.
  • a step (step shown in FIGS. 13 to 15 ) corresponding to the ion implantation IM 1 is not performed so that the semiconductor device of Second Investigation Example shown in FIG. 23 does not have therein a region corresponding to the fluorine implanted region FR.
  • the entire inner surface of the trench TR in the semiconductor substrate SB is nitrided so that reoxidation and expansion thereby of the element isolation region ST filled in the trench TR can be suppressed or prevented.
  • the element isolation region ST which has filled the trench TR can be suppressed or prevented from expanding in the thermal oxidation step for forming an insulating film for a gate insulating film.
  • Generation of crystal defects in the semiconductor substrate SB in the active region due to expansion of the element isolation region ST can therefore be suppressed or prevented and as a result, the semiconductor device thus manufactured can have improved reliability.
  • NBTI characteristics means a phenomenon of MISFET characteristics (threshold voltage) varying due to application of a bias voltage (negative bias voltage) at high temperatures. Deterioration (worsening) of NBTI characteristics increases a change in the threshold voltage of the MISFET when a bias voltage (negative bias voltage) is applied at high temperatures.
  • the present inventors have found as a result of investigation that the semiconductor device of Second Investigation Example of FIG. 23 has greatly deteriorated NBTI characteristics and furthermore, the deterioration degree of NBTI characteristics depends on the gate width and with a decrease in the gate width, the deterioration of NBTI characteristics of the p channel MISFET becomes severer.
  • FIG. 24 is a graph showing the gate width dependence of NBTI characteristics of each of the semiconductor device of First Investigation Example and the semiconductor device of Second Investigation Example.
  • the gate width of the gate electrode of the p channel MISFET is plotted along the abscissa of the graph shown in FIG. 24 .
  • a change in the threshold voltage of the p channel MISFET before and after application of high-temperature negative bias voltage (NBT stress) is plotted along the ordinate in FIG. 24 .
  • Values along the ordinate in the graph of FIG. 24 are standardized based on a change in threshold voltage before and after application of an NBT stress when the gate width is 10 ⁇ m, in each of the semiconductor device of First Investigation Example and the semiconductor device of Second Investigation Example.
  • the semiconductor device of the present embodiment has the semiconductor substrate SB, the element isolation region ST buried in the trench TR formed in the semiconductor substrate SB, the gate electrode GE 1 formed, via the insulating film GF (first insulating film), on the semiconductor substrate SB in the active region AC 1 (first active region) surrounded by the element isolation region ST, and the source/drain region SD 1 formed in the semiconductor substrate SB in the active region AC 1 .
  • the gate electrode GE 1 (first gate electrode) is a gate electrode for MISFETQp (first MISFET), the insulating film GF (first gate insulating film) below the gate electrode GE 1 functions as a gate insulating film of the MISFETQp (first MISFET), the source/drain region SD 1 (first source/drain region) is a source/drain region for the MISFETQp (first MISFET).
  • the element isolation region ST is composed mainly of silicon oxide and more specifically, it is made of a silicon oxide film buried in the trench TR.
  • One of the main characteristics of the present embodiment is a nitrided inner surface (side surface and bottom surface) of the trench TR in the semiconductor substrate SB.
  • the element isolation region ST buried in the trench TR may be re-oxidized and thereby expand in various steps performed after formation of the element isolation region ST, as described above. This may generate crystal defects in the semiconductor substrate SB in the active region and as a result, the semiconductor device thus provided inevitably has deteriorated reliability.
  • the element isolation region ST can be suppressed or prevented from being re-oxidized and thereby expanding in various steps after formation of the element isolation region ST.
  • the element isolation region ST buried in the trench TR can be suppressed or prevented from expanding in a thermal oxidation step for the formation of an insulating film (corresponding to the insulating film GF) for gate insulating film. This therefore makes it possible to suppress or prevent generation of crystal defects in the semiconductor substrate SB in the active region, which would otherwise be caused by expansion of the element isolation region ST. As a result, the semiconductor device thus manufactured can have improved reliability.
  • Another one of the main characteristics of the present embodiment is that a portion of the gate electrode GE 1 extends over the element isolation region ST; and below the gate electrode GE 1 , fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the MISFETQp.
  • fluorine (F) is introduced into the vicinity of the boundary between the element isolation region ST and the channel region of the MISFETQp.
  • the gate electrode When the gate electrode extends over not only the semiconductor substrate but also the element isolation region surrounding the active region of the substrate, the nitrided inner surface of the trench in the semiconductor substrate SB to be filled with the element isolation region may lead to deterioration in NBTI characteristics.
  • deterioration in NBTI characteristics of the semiconductor device of Second Investigation Example shown in FIG. 23 is larger and at the same time, the deterioration degree of NBTI characteristics depends on the gate width. With a decrease in gate width, the deterioration degree of the NBTI characteristics of the p channel MISFET becomes severer.
  • Nitriding of the inner surface of the trench in the semiconductor substrate to be filled with the element isolation region is effective for preventing reoxidation and expansion thereby of the element isolation region, but it inevitably enhances deterioration of NBTI characteristics.
  • a gate electrode extends over a semiconductor substrate in an active region but does not extend over an element isolation region surrounding the active region; and the gate electrode has both end portions in the gate width direction on the semiconductor substrate in the active region.
  • this nitride layer is much distant from the gate insulating film or channel region of the MISFET so that the nitride layer has almost no influence on the NBTI characteristics of the MISFET and presence or absence of the nitride layer causes almost no change in NBTI characteristics.
  • the gate electrode extends also over an element isolation region.
  • This structure is employed to place, when a plug buried in a contact hole formed on a gate electrode is electrically coupled to the gate electrode, the contact hole and the plug to be buried therein on a portion of the gate electrode located on the element isolation region. Then, even if, during formation of the contact hole, the formation position of the contact hole slightly deviates from its designed position, the element isolation region is exposed from the contact hole and the substrate region remains unexposed so that the plug to be coupled to the gate electrode can be prevented from being electrically coupled to the semiconductor substrate.
  • the gate electrode is required to extend over the element isolation region between the MISFETs.
  • a portion of the gate electrode also extends over the element isolation region (element isolation region surrounding the active region).
  • the gate electrode extends not only over the semiconductor substrate in the active region but also over the element isolation region surrounding the active region, a nitride layer formed by nitriding the entire inner surface of the trench of the semiconductor substrate to be filled with the element isolation region is likely to adversely affect the NBTI characteristics of the MISFET because the nitride layer is near the gate insulating film or channel region of the MISFET.
  • the nitride layer SN is near the gate insulating film or channel region of the MISFET so that the nitride layer SN adversely affects the NBTI characteristics of the MISFET and enhances the deterioration in NBTI characteristics.
  • the degree of deterioration in NBTI characteristics depends on the gate width so that with a decrease in the gate width, the p channel MISFET is presumed to have severely deteriorated NBTI characteristics.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the MISFETQp. Nitrogen is an element promoting deterioration in NBTI characteristics, while fluorine (F) is an element effective for suppressing deterioration in NBTI characteristics.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the MISFETQp so that deterioration in NBTI characteristics can be suppressed or prevented.
  • dependence of the degree of deterioration in NBTI characteristics on the gate width can be suppressed or prevented.
  • introduction of fluorine (F) is effective for suppressing or preventing deterioration in NBTI characteristics.
  • a fluorine introduced region a region in the vicinity of a boundary between the element isolation region ST and the channel region of the MISFETQp below the gate electrode GE 1 is particularly effective.
  • the reason is that a portion of the nitride layer SN formed on the inner surface of the trench TR in the semiconductor substrate SB and near the gate insulating film or channel region of the MISFET is likely to contribute to the deterioration in NBTI characteristics. This is a portion of the nitride layer SN present in the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 .
  • introduction of fluorine (F) into a portion of the nitride layer SN or in the vicinity thereof which is likely to contribute to deterioration in NBTI characteristics is therefore effective for suppressing or preventing deterioration in NBTI characteristics due to the nitride layer SN.
  • introduction of fluorine (F) into the vicinity of a boundary between the element isolation region ST and the channel region of the MISFET (Qp) is therefore particularly effective for suppressing or preventing deterioration in NBTI characteristics of the MISFET (Qp).
  • introduction of fluorine (F) into a region hatched with dots in FIG. 25 is particularly effective for suppressing or preventing deterioration in NBTI characteristics.
  • FIG. 25 is a fragmentary plan view of a semiconductor device of another mode and it corresponds to FIG. 2 .
  • a region implanted with fluorine (F) (fluorine implanted region FR) is hatched with dots.
  • the cross-sectional view taken along the line B 1 -B 1 in FIG. 25 is similar to that in FIG. 4 , but the cross-sectional view taken along the line A 1 -A 1 in FIG. 25 corresponds to a drawing obtained by removing the fluorine implanted region FR from FIG. 3 .
  • fluorine (F) is introduced (implanted) into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 , but fluorine (F) is not introduced (implanted) into the other region.
  • fluorine (F) is introduced into the vicinity of a boundary between the active region AC 1 and the element isolation region ST surrounding the active region AC 1 .
  • Introduction of fluorine (F) into the vicinity of a boundary between the channel region and the element isolation region immediately below the gate electrode GE 1 is at least necessary.
  • Introduction of fluorine (F) into an upper portion of the nitride layer SN between the element isolation region ST and the channel region immediately below the gate electrode GE 1 is particularly effective for suppressing deterioration in NBTI characteristics.
  • the semiconductor substrate SB in the active region has fluorine (F) introduced therein, there is a risk of fluorine (F) causing an unintentional change in the characteristics of the MISFET formed in the active region.
  • fluorine (F) is preferably not implanted into a region other than the outer peripheral portion (region inside the outer peripheral portion). This makes it possible to reduce the risk of fluorine (F) thus introduced causing an unintentional change in the MISFET characteristics.
  • fluorine (F) may be implanted into a region adjacent to the active region AC 1 or fluorine may be implanted into the entirety of the element isolation region ST. This is because compared with introduction of fluorine (F) into the semiconductor substrate SB in the active region AC 1 , introduction of fluorine (F) into the element isolation region ST does not easily enhance the risk of the thus-introduced fluorine (F) causing an unintentional change in the MISFET characteristics.
  • the fluorine implanted region FR is therefore not limited to a region hatched with dots in FIG. 2 , but may be formed, for example, in a region hatched with dots in FIG. 25 .
  • the trench TR of the semiconductor substrate SB has a nitrided inner surface so that generation of crystal defects in the semiconductor substrate SB in the active region due to expansion of the element isolation region ST can be suppressed or prevented. Further, due to fluorine (F) introduced as described above, deterioration in NBTI characteristics can be suppressed or prevented.
  • the semiconductor device thus manufactured can therefore have properly improved reliability.
  • FIGS. 26 and 27 are fragmentary cross-sectional views showing a semiconductor device of First Modification Example of the present embodiment.
  • FIG. 26 shows a cross-section corresponding to FIG. 3 (cross-section along a gate length direction) and
  • FIG. 27 shows a cross-section corresponding to FIG. 4 (cross-section along a gate width direction).
  • a semiconductor substrate SB has thereon both a p channel MISFET and an n channel MISFET.
  • the semiconductor device of First Modification Example shown in FIGS. 26 and 27 has, in the semiconductor substrate SB, an element isolation region ST and active regions AC 1 and AC 2 surrounded by the element isolation region ST.
  • the active region AC 1 has therein a p channel MISFETQp and the active region AC 2 has therein an n channel MISFETQn.
  • the active region AC 1 , the element isolation region ST surrounding the active region AC 1 therewith, and the p channel MISFETQp formed in the active region AC 1 are similar to those described above referring to FIGS. 1 to 4 and FIG. 25 . Described specifically, the semiconductor substrate SB in the active region AC 1 has therein an n type well NW; the semiconductor substrate SB (n well NW) in the active region AC 1 has thereon a gate electrode GE 1 via an insulating film GF; and the semiconductor substrate SB (n well NW) in the active region AC 1 has therein a source/drain region SD 1 .
  • the gate electrode GE 1 is a gate electrode for p channel MISFETQp; the gate insulating film GF below the gate electrode GE 1 functions as a gate insulating film for p channel MISFETQp; and the source/drain region SD 1 is a source/drain region for the p channel MISFETQp.
  • the active region AC 2 , the element isolation region ST surrounding the active region AC 2 , and the n channel MISFETQn formed in the active region AC 2 are different in the following points from the active region AC 1 , the element isolation region ST surrounding the active region AC 1 , and the p channel MISFETQp formed in the active region AC 1 .
  • the semiconductor substrate SB in the active region AC 2 has therein a p well PW
  • the semiconductor substrate SB (p well PW) in the active region AC 2 has thereon a gate electrode GE 2 via the insulating film GF
  • the semiconductor substrate SB (p well PW) in the active region AC 2 has therein a source/drain region SD 2 .
  • the gate electrode GE 2 is a gate electrode for the n channel MISFETQn
  • the insulating film GF below the gate electrode GE 2 functions as a gate insulating film for the n channel MISFETQn
  • the source/drain region SD 2 is a source/drain region for the n channel MISFETQn.
  • the configuration of the p well PW, the gate electrode GE 2 , and the source/drain region SD 2 is almost similar to the configuration of the n type well NW, the gate electrode GE 1 , and the source/drain region SD 1 except for the conductivity type.
  • This means that the source/drain region SD 1 is a p type semiconductor region, while the source/drain region SD 2 is an n type semiconductor region.
  • the gate electrode GE 1 is made of p type doped polysilicon, while the gate electrode GE 2 is made of n type doped polysilicon.
  • the source/drain region SD 2 is therefore comprised of an n ⁇ type semiconductor region E 2 corresponding to the p ⁇ type semiconductor region E 1 and an n+ type semiconductor region H 2 corresponding to the p + type semiconductor region H 1 .
  • the n + type semiconductor region H 2 has an impurity concentration higher and a junction depth deeper than those of the n ⁇ type semiconductor region E 2 . Similar to a portion of the gate electrode GE 1 extending over the element isolation region ST surrounding the active region AC 1 , a portion of the gate electrode GE 2 extends over the element isolation region ST surrounding the active region AC 2 .
  • the gate electrode GE 1 has, on the side wall thereof, a sidewall spacer SW.
  • the p + type semiconductor region H 1 , the n + type semiconductor region H 2 , the gate electrode GE 1 , and the gate electrode GE 2 each have, on the upper portion thereof, a metal silicide layer SL.
  • An interlayer insulating film IL 1 covers the gate electrodes GE 1 and GE 2 and the sidewall spacer SW and a contact hole CT and a plug PG buried therein are present on the p + type semiconductor region H 1 , the n + type semiconductor region H 2 , the gate electrode GE 1 , the gate electrode GE 2 , and the like.
  • the element isolation region ST in First Modification Example shown in FIGS. 26 and 27 is also buried in the trench TR formed in the semiconductor substrate SB. It is composed mainly of silicon oxide. More specifically, it is made of a silicon oxide film buried in the trench TR.
  • the trench TR in the semiconductor substrate SB has a nitrided inner surface (side surface and bottom surface).
  • the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 2 are in common in this point.
  • the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 2 are in common in that the trench TR filled with the element isolation region ST has a nitride layer SN obtained by nitriding the inner surface of the trench.
  • the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 2 can therefore be suppressed or prevented from being re-oxidized and thereby expanding in various steps performed after formation of the element isolation region ST. This makes it possible to suppress or prevent generation of crystal defects in the semiconductor substrate SB in the active regions AC 1 and AC 2 which would otherwise be caused by expansion of the element isolation region ST. As a result, the semiconductor device thus manufactured can have improved reliability.
  • a portion of the gate electrode GE 1 of the p channel MISFETQp extends over the element isolation region ST and in a region below the gate electrode GE 1 , fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the p channel MISFETQp.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the p channel MISFETQp.
  • a portion of the gate electrode GE 2 of the n channel MISFETQn extends over the element isolation region ST.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the n channel MISFETQn below the gate electrode GE 2 and in some cases, fluorine (F) is not introduced therein.
  • n channel MISFET In the n channel MISFET, compared with the p channel MISFET, deterioration in the NBTI characteristics hardly occurs and at the same time, in the n channel MISFET, a negative voltage is not applied so frequently to the gate electrode of it. Suppression of deterioration in the NBTI characteristics is required in the p channel MISFET and in the n channel MISFET, compared with the p channel MISFET, suppression of deterioration in the NBTI characteristics is not required so much.
  • fluorine (F) is therefore introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 .
  • fluorine (F) is preferably not introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 2 .
  • fluorine (F) introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 makes it possible to suppress or prevent the p channel MISFETQp, which is required to have less deteriorated NBTI characteristics, from having deteriorated NBTI characteristics.
  • fluorine (F) is ion-implanted with the photoresist pattern PR 2 as an ion implantation preventive mask (mask layer).
  • this ion implantation it is recommended to cover the active region AC 2 for the n channel MISFET and the element isolation region ST surrounding it with the photoresist pattern PR 2 .
  • This makes it possible to prevent fluorine (F) from being ion-implanted by the above ion implantation IM 1 into the semiconductor substrate SB in the active region AC 2 or in the vicinity of a boundary between the semiconductor substrate SB in the active region AC 2 and the element isolation region ST.
  • the semiconductor device thus manufactured can therefore have no fluorine (F) introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 2 .
  • the step of forming the n channel MISFETQn is essentially similar to that of the p channel MISFETQp except that the conductivity type is opposite.
  • n well NW in the steps shown in FIGS. 16 and 17 , not only the n well NW but also a p well PW is formed. Since the n well NW and the p well PW are different in conductivity type, an ion implantation step for forming the n well NW and an ion implantation step for forming the p well PW are performed separately. In forming an insulating film GF in the steps shown in FIGS. 16 and 17 , the insulating film GF is formed on the surface of the n well NW and on the surface of the p well PW. By the steps shown in FIGS.
  • a polysilicon film is formed as a conductive film for gate electrode and the polysilicon film is then patterned to form a gate electrode GE 1 and a gate electrode GE 2 .
  • the gate electrode GE 1 is formed on the semiconductor substrate SB (n type well NW) via the insulating film GF and the gate electrode GE 2 is formed on the semiconductor substrate SB (p well PW) via the insulating film GF.
  • a p ⁇ type semiconductor region E 1 is formed in the steps shown in FIGS. 18 and 19 , not only the p ⁇ type semiconductor region E 1 but also an n ⁇ type semiconductor region E 2 is formed.
  • the p ⁇ type semiconductor region E 1 and the n ⁇ type semiconductor region E 2 are however different in conductivity type so that an ion implantation step for forming the p ⁇ type semiconductor region E 1 and an ion implantation step for forming the n ⁇ type semiconductor region E 2 are performed separately.
  • the sidewall spacer SW is formed on the side wall of the gate electrode GE 1 and the side wall of the gate electrode GE 2 .
  • a p + type semiconductor region H 1 in the steps shown in FIGS. 18 and 19 not only the p + type semiconductor region H 1 but also an n + type semiconductor region H 2 is formed.
  • an ion implantation step for forming the p + type semiconductor region H 1 and an ion implantation step for forming the n + type semiconductor region H 2 are performed separately.
  • the metal silicide layer SL is formed on the surface of the gate electrode GE 1 , the gate electrode GE 2 , the p + type semiconductor region H 1 , and the n + type semiconductor region H 2 . Steps other the above-described ones are essentially similar to those described referring to FIGS. 3 to 21 so that overlapping description is omitted here.
  • FIGS. 28 and 29 are fragmentary cross-sectional views showing a semiconductor device of Second Modification Example of the present embodiment.
  • FIG. 28 shows, similar to FIG. 26 , a cross-section (cross-section along a gate length direction) corresponding to FIG. 3 and
  • FIG. 29 shows, similar to FIG. 27 , a cross-section (cross-section along a gate width direction) corresponding to FIG. 4 .
  • the semiconductor device of Second Modification Example shown in FIGS. 28 and 29 has, on the semiconductor substrate SB thereof, a low-breakdown-voltage MISFET and a high-breakdown-voltage MISFET.
  • the semiconductor device of Second Modification Example shown in FIGS. 28 and 29 has, on the semiconductor substrate SB thereof, an element isolation region ST and active regions AC 1 and AC 3 surrounded by the element isolation region ST.
  • the active region AC 1 has therein a low-breakdown-voltage p channel MISFETQp and the active region AC 3 has therein a high-breakdown-voltage p channel MISFETQp 3 .
  • the active region AC 1 , the element isolation region ST surrounding the active region AC 1 , and the low-breakdown-voltage p channel MISFETQp formed in the active region AC 1 are similar to those described above referring to FIGS. 1 to 4 and FIG. 25 . Described specifically, the semiconductor substrate SB in the active region has therein an n well NW; the semiconductor substrate SB (n well NW) in the active region AC 1 has thereon a gate electrode GE 1 via an insulating film GF; and the semiconductor substrate SB (n well NW) in the active region AC 1 has therein a source/drain region SD 1 .
  • the gate electrode GE 1 is a gate electrode for low-breakdown-voltage p channel MISFETQp; the insulating film GF below the gate electrode GE 1 functions as a gate insulating film for low-breakdown-voltage p channel MISFETQp; and the source/drain region SD 1 is a source/drain region for the low-breakdown-voltage p channel MISFETQp.
  • the active region AC 3 , the element isolation region ST surrounding the active region AC 3 , and the high-breakdown-voltage p channel MISFETQp 3 formed in the active region AC 3 are different in the following points from the active region AC 1 , the element isolation region ST surrounding the active region AC 1 , and the low-breakdown-voltage p channel MISFETQp formed in the active region AC 1 .
  • the semiconductor substrate SB in the active region AC 3 has therein an n well NW 3 ; the semiconductor substrate SB (n well NW 3 ) in the active region AC 3 has thereon a gate electrode GE 3 via an insulating film GF 3 ; and the semiconductor substrate SB (n well NW 3 ) in the active region AC 3 has therein a source/drain region SD 3 .
  • the gate electrode GE 3 is a gate electrode for high-breakdown-voltage p channel MISFETQp 3 ; the insulating film GF 3 below the gate electrode GE 3 functions as a gate insulating film for high-breakdown-voltage p channel MISFETQp 3 ; and the source/drain region SD 3 is a source/drain region for high-breakdown-voltage p channel MISFETQp 3 .
  • the thickness of the gate insulating film (here, the gate insulating film GF 3 ) of the high-breakdown-voltage p channel MISFETQp 3 is greater than that of the gate insulating film (here, the gate insulating film GF) of the low-breakdown-voltage p channel MISFETQp.
  • the breakdown voltage of the p channel MISFETQp 3 is therefore larger than that of the p channel MISFETQp.
  • An operating voltage of the high-breakdown-voltage p channel MISFETQp 3 is greater than that of the low-breakdown-voltage p channel MISFETQp.
  • the high-breakdown-voltage p channel MISFETQp 3 is an MISFET used, for example, for I/O circuit (input/output circuit), while the low-breakdown-voltage p channel MISFETQp is an MISFET used, for example, for core circuit (such as control circuit) or SRAM.
  • the configuration of the n well NW 3 , the gate electrode GE 3 , and the source/drain region SD 3 is almost similar to the configuration of the n well NW, the gate electrode GE 1 , and the source/drain region SD 1 .
  • the source/drain region SD 3 is comprised of a p ⁇ type semiconductor region E 3 corresponding to the p ⁇ type semiconductor region E 1 and a p + type semiconductor region H 3 corresponding to the p + type semiconductor region H 1 .
  • the p + type semiconductor region H 3 has an impurity concentration higher and a junction depth deeper than those of the p ⁇ type semiconductor region E 3 . Similar to a portion of the gate electrode GE 1 extending over the element isolation region ST surrounding the active region AC 1 , a portion of the gate electrode GE 3 extends over the element isolation region ST surrounding the active region AC 3 .
  • the gate electrode GE 1 has, on the side wall thereof, a sidewall spacer SW.
  • the p + type semiconductor region H 1 , the p + type semiconductor region H 3 , the gate electrode GE 1 , and the gate electrode GE 3 each have, on an upper portion thereof, a metal silicide layer.
  • An interlayer insulating film IL 1 covers the gate electrodes GE 1 and GE 3 , and the sidewall spacer SW.
  • a contact hole CT and a plug PG buried therein are formed on the p + type semiconductor region H 1 , the p + type semiconductor region H 3 , the gate electrode GE 1 , the gate electrode GE 3 , and the like.
  • the element isolation region ST in Second Modification Example shown in FIGS. 28 and 29 is buried in a trench TR formed in the semiconductor substrate SB and it is composed mainly of silicon oxide, more specifically, is comprised of a silicon oxide film buried in the trench TR.
  • the trench TR in the semiconductor substrate SB has a nitrided inner surface (side surface and bottom surface). In this point, the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 3 are in common.
  • the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 3 are therefore in common in that the trench TR filled with the element isolation region ST has, on the inner surface thereof, a nitride layer SN obtained by nitriding the inner surface.
  • the element isolation region ST surrounding the active region AC 1 and the element isolation region ST surrounding the active region AC 3 can therefore be suppressed or prevented from being re-oxidized and thereby expanding in various steps after formation of the element isolation region ST. This makes it possible to suppress or prevent generation of crystal defects in the semiconductor substrate SB in the active regions AC 1 and AC 3 which would otherwise be caused by expansion of the element isolation region ST. As a result, the semiconductor device thus manufactured can have improved reliability.
  • a portion of the gate electrode GE 1 of the low-breakdown-voltage p channel MISFETQp extends over the element isolation region ST and below the gate electrode GE 1 , fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the p channel MISFETQp.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the p channel MISFETQp.
  • a portion of the gate electrode GE 3 of the high-breakdown-voltage p channel MISFETQp 3 extends over the element isolation region ST, but below the gate electrode GE 3 , fluorine (F) is sometimes introduced and sometimes is not introduced into the vicinity of a boundary between the element isolation region ST and the channel region of the p channel MISFETQp 3 .
  • both the low-breakdown-voltage p channel MISFETQp and the high-breakdown-voltage p channel MISFETQp 3 can be suppressed or prevented from having deteriorated NBTI characteristics.
  • a deterioration degree of the NBTI characteristics can be suppressed or prevented from depending on the gate width.
  • the gate width (channel width) of the high-breakdown-voltage MISFET is greater than the gate width (channel width) of the low-breakdown-voltage MISFET.
  • deterioration in NBTI characteristics due to the nitride layer SN is likely to increase when the gate width is small, but deterioration in NBTI characteristics due to the nitride layer SN relatively decreases with an increase in the gate width.
  • the low-breakdown-voltage MISFET having a small gate width is therefore required to be less deteriorated in NBTI characteristics.
  • the high-breakdown-voltage MISFET having a large gate width, compared with the low-breakdown-voltage one, is not so required to be less deteriorated in NBTI characteristics.
  • the gate width (channel width) of the high-breakdown-voltage p channel MISFETQp 3 is greater than the gate width (channel width) of the low-breakdown-voltage p channel MISFETQp.
  • Second Modification Example in the active region AC 1 for low-breakdown-voltage p channel MISFET and the element isolation region ST surrounding it, fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 .
  • the active region AC 3 for high-breakdown-voltage p channel MISFET and the element isolation region ST surrounding it it is preferred that no fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 3 .
  • the configuration described above referring to FIGS. 1 to 4 and FIG. 25 is applied to the low-breakdown-voltage MISFET and the configuration described above referring to Second Investigation Example shown in FIG. 23 is applied to the high-breakdown-voltage MISFET.
  • fluorine (F) is introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 , the low-breakdown-voltage p channel MISFETQp required to be less deteriorated in NBTI characteristics can be suppressed or prevented from having deteriorated NBTI characteristics.
  • fluorine (F) is not introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 3 so that a risk of the characteristics of the high-breakdown-voltage p channel MISFETQp 3 undergoing an unintentional change due to introduction of fluorine (F) can be avoided.
  • the semiconductor device thus manufactured can have more properly improved reliability.
  • Fluorine (F) is ion-implanted by the above ion implantation IM 1 , with the photoresist pattern PR 2 as an ion implantation preventive mask (mask layer). It is recommended to cover the active region AC 3 for the high-breakdown-voltage p channel MISFET and the element isolation region ST surrounding it with the photoresist pattern PR 2 . This makes it possible to prevent fluorine (F) from being ion-implanted by the above ion implantation IM 1 into the semiconductor substrate SB in the active region AC 3 or in the vicinity of a boundary between the semiconductor substrate SB in the active region AC 3 and the element isolation region ST. The semiconductor device thus manufactured can therefore have no fluorine (F) introduced into the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 3 .
  • a gate insulating film formation step can be performed as follows. Described specifically, in the steps shown in FIGS. 16 and 17 , after formation of n wells NW and NW 3 by ion implantation, an insulating film GF 3 is formed on the surface of the n well NW and on the surface of the n well NW 3 by thermal oxidation or the like, the insulating film GF 3 is removed from the surface of the n well NW, while leaving the insulating film GF 3 on the surface of the n well NW 3 .
  • an insulating film GF is formed on the surface of the n well NW by thermal oxidation or the like. During the thermal oxidation for forming the insulating film GF, the thickness of the insulating film GF 3 on the surface of the n well NW 3 increases. In such a manner, a structure is obtained in which the semiconductor substrate SB (n well NW) in the active region AC 1 has thereon the insulating film GF and the semiconductor substrate SB (on the n well NW 3 ) in the active region AC 3 has thereon the insulating film GF 3 thicker than the insulating film GF.
  • the steps of forming the high-breakdown-voltage p channel MISFETQp 3 are essentially similar to the steps of forming the low-breakdown-voltage p channel MISFETQp except for the gate insulating film formation step.
  • the gate electrodes GE 1 and GE 3 are formed by forming a polysilicon film as a gate electrode conductive film and then patterning the polysilicon film.
  • the gate electrode GE 1 is formed on the semiconductor substrate SB (n well NW) via the insulating film GF and the gate electrode GE 3 is formed on the semiconductor substrate SB (n well NW 3 ) via the insulating film GF 3 .
  • the p ⁇ type semiconductor region E 1 by the step shown in FIGS.
  • the metal silicide layer SL is formed on the surfaces of the gate electrode GE 1 , the gate electrode GE 3 , the p + type semiconductor region H 1 , and the p + type semiconductor region H 3 . Steps other than those described above are essentially similar to the manufacturing steps described above referring to FIGS. 3 to 21 so that an overlapping description is omitted here.
  • FIG. 30 is a fragmentary plan view of the semiconductor device of the present embodiment
  • FIGS. 31 and 32 are fragmentary cross-sectional views of the semiconductor device of the present embodiment.
  • FIGS. 30 to 32 correspond to FIGS. 1, 3, and 4 of First Embodiment, respectively. Therefore, the cross-sectional view taken along the line A 2 -A 2 of FIG. 30 substantially corresponds to FIG. 31 and the cross-sectional view taken along the line B 2 -B 2 of FIG. 30 substantially corresponds to FIG. 32 .
  • the semiconductor device of Second Embodiment shown in FIGS. 30 and 31 is different from the semiconductor device of First Embodiment in the following point.
  • fluorine (F) is not introduced into the vicinity of a boundary between the element isolation region ST and the semiconductor substrate SB in the active region AC 1 .
  • the semiconductor device of Second Embodiment does not have therein a region corresponding to the fluorine implanted region FR.
  • the manufacturing steps of the semiconductor device of Second Embodiment therefore do not include a step corresponding to the ion implantation IM 1 .
  • the trench TR in the semiconductor substrate SB has a nitride layer SN obtained by nitriding the inner surface of the trench, but has no nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST.
  • the trench TR does not have the nitride layer SN on the upper portion of the side surface of the trench TR but has it in the other region of the inner surface (side surface and bottom surface) of the trench TR. More specifically, the upper portion (portion adjacent to the upper portion of the side surface of the trench TR) of the nitride layer SN formed on the inner surface (side surface and bottom surface) of the trench TR is oxidized into an oxidation portion OX.
  • the other configuration of the semiconductor device of Second Embodiment is essentially similar to that of the semiconductor device of First Embodiment so that an overlapping description is omitted here.
  • FIG. 33 to FIG. 38 are fragmentary cross-sectional views of the semiconductor device of Second Embodiment during manufacturing steps thereof, in which FIGS. 33, 35, and 37 show cross-sections corresponding to FIG. 31 , that is, cross-sections at a position corresponding to the line A 2 -A 2 of FIG. 30 and FIGS. 34, 36, and 38 show cross-sections corresponding to FIG. 32 , that is, cross-sections at a position corresponding to the line B 2 -B 2 of FIG. 30 .
  • FIGS. 11 and 12 The structure shown in FIGS. 11 and 12 is obtained in a manner similar to that described in First Embodiment.
  • a photoresist layer is then applied to the main surface (entire main surface) of the semiconductor substrate SB, followed by exposure and development of the resulting photoresist layer to form a photoresist pattern (resist pattern, resist layer, mask layer) PR 3 as a mask layer on the semiconductor substrate SB as shown in FIGS. 33 and 34 .
  • An opening portion OP 3 of the photoresist pattern PR 3 has a planar shape and size slightly greater than those of the opening portion OP 1 of the photoresist pattern PR 1 .
  • the opening portion OP 3 of the photoresist pattern PR 3 embraces the element isolation region ST and has a planar shape and size slightly greater than those of the element isolation region ST.
  • the planar shape and size of the opening portion OP 3 are preferably set so that the element isolation region ST buried in the trench TR in the semiconductor substrate SB and the nitride layer SN formed on the inner surface of the trench TR in the semiconductor substrate SB are just exposed from the opening portion OP 3 of the photoresist pattern PR 3 . This means that it is preferred to expose the element isolation region ST and the nitride layer SN from the opening portion OP 3 of the photoresist pattern PR 3 and prevent exposure of the semiconductor substrate SB in the active region (AC 1 ) to the utmost.
  • an oxidation portion OX is formed as shown in FIGS. 35 and 36 by subjecting the semiconductor substrate SB to oxidation treatment to oxidize the upper portion of the nitride layer SN present between the semiconductor substrate SB in the active region (AC 1 ) and the element isolation region ST.
  • the above oxidation treatment will hereinafter be called “oxidation treatment of FIGS. 35 and 36 ”.
  • the oxidation treatment of FIGS. 35 and 36 is preferably thermal oxidation, with wet oxidation being particularly preferred.
  • the oxidation portion OX is composed mainly of silicon oxide.
  • the trench TR in the semiconductor substrate SB has, on an inner surface (side surface and bottom surface) thereof, the nitride layer SN, but by the oxidation treatment of FIGS. 35 and 36 , the upper portion (portion adjacent to the upper portion of the side surface of the trench TR) of the nitride layer SN formed on the inner surface (side surface and bottom surface) of the trench TR is oxidized into an oxidation portion OX, while the other portion of the nitride layer SN remains as is.
  • the nitride layer SN is formed on the inner surface (side surface and bottom surface) of the trench TR; and a portion of the nitride layer SN formed on the upper portion of the side surface of the trench TR is oxidized by the oxidation treatment of FIGS. 35 and 36 into an oxidation portion OX, while the other portion of the nitride layer SN remains without being oxidized.
  • a portion of the nitride layer SN sandwiched between the upper portion of the semiconductor substrate SB in the active region (AC 1 ) and the upper portion of the element isolation region ST is oxidized by the oxidation treatment of FIGS. 35 and 36 into the oxidation portion OX.
  • a size L 3 of a region of the nitride layer SN formed on the side surface of the trench TR and becoming the oxidation portion OX by oxidation treatment of FIGS. 35 and 36 that is, a size L 3 of the oxidation portion OX thus formed can be set at, for example, from about 1 to 10 nm.
  • the size L 3 is a depth-direction size, that is, a size (thickness, depth) in a direction substantially perpendicular to the main surface of the semiconductor substrate SB.
  • nitride layer SN present on the entire inner surface of the trench TR, a portion of the nitride layer SN having a depth corresponding to the size L 3 from the main surface of the semiconductor substrate SB is oxidized into the oxidation portion OX and the other portion of the nitride layer SN extending in a region deeper than the size L 3 remains as the nitride layer SN without being oxidized.
  • the oxidation treatment of FIGS. 35 and 36 is treatment for oxidizing the upper portion of the nitride layer SN at a boundary between the element isolation region ST and the semiconductor substrate SB in the active region (AC 1 ) surrounded by the element isolation region ST.
  • the oxidation treatment of FIGS. 35 and 36 is treatment for oxidizing, of the nitride layer SN formed on the inner surface (side surface and bottom surface) of the trench TR, a portion of the nitride layer SN formed on the upper portion of the side surface of the trench TR and thereby converting it into the oxidation portion OX.
  • the trench TR has, on the entire inner surface thereof, the nitride layer SN, but after the oxidation treatment of FIGS. 35 and 36 , the trench TR has, on the upper portion of the side surface thereof, no nitride layer SN.
  • the oxidation treatment of FIGS. 35 and 36 can therefore also be regarded as treatment of removing the nitride layer SN on the upper portion of the side surface of the trench TR.
  • the photoresist pattern PR 3 is removed. After removal of the photoresist pattern PR 3 , washing treatment can be performed. This washing treatment may etch the surface layer portion of the element isolation region ST or a portion of the oxidation portion OX.
  • the photoresist pattern PR 3 may be replaced by a hard mask (mask layer using an insulating film pattern). In this case, the formation position of the opening portion OP 3 in the hard mask is as described above.
  • the semiconductor device of Second Embodiment has the semiconductor substrate SB, the element isolation region ST buried in the trench TR formed in the semiconductor substrate SB, a gate electrode GE 1 formed, via a gate insulating film GF (first gate insulating film), on the semiconductor substrate SB in the active region AC 1 (first active region) surrounded by the element isolation region ST, and a source/drain region formed in the semiconductor substrate SB in the active region AC 1 .
  • a gate electrode GE 1 formed, via a gate insulating film GF (first gate insulating film), on the semiconductor substrate SB in the active region AC 1 (first active region) surrounded by the element isolation region ST, and a source/drain region formed in the semiconductor substrate SB in the active region AC 1 .
  • the gate electrode GE 1 (first gate electrode) is a gate electrode for MISFETQp (first MISFET), the gate insulating film GF (first gate insulating film) below the gate electrode GE 1 functions as a gate insulating film for MISFETQp (first MISFET), and the source/drain region SD 1 (first source/drain region) is a source/drain region for MISFETQp (first MISFET).
  • the element isolation region ST is composed mainly of silicon oxide, more specifically, is comprised of a silicon oxide film buried in the trench TR.
  • the trench TR of the semiconductor substrate has, on the inner surface (side surface and bottom surface) thereof, a nitride layer SN obtained by nitriding the inner surface.
  • the nitride layer thus formed can suppress or prevent the element isolation region ST buried in the trench TR from being re-oxidized and thereby expanding in various steps performed after formation of the element isolation region ST. For example, it can suppress or prevent the element isolation region ST buried in the trench TR from expanding in the thermal oxidation step for forming an insulating film (corresponding to the insulating film GF) for gate insulating film. Generation of defects in the semiconductor substrate in the active region due to expansion of the element isolation region ST can therefore be suppressed or prevented so that the semiconductor device thus manufactured can have improved reliability.
  • the other one of the main characteristics of Second Embodiment is that a portion of the gate electrode GE 1 extends over the element isolation region ST and no nitride layer SN is formed at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST. This makes it possible to suppress or prevent deterioration in NBTI characteristics and the semiconductor device thus obtained can have improved reliability. This will be described more specifically.
  • a nitride layer formed by nitriding the entire inner surface in the element isolation trench is likely to affect the NBTI characteristics because the nitride layer is close to a gate insulating film or channel region of MISFET.
  • the nitride layer SN is near the gate insulating film or channel region of the MISFET so that the nitride layer SN adversely affects the NBTI characteristics of the MISFET and enhances deterioration in NBTI characteristics.
  • the degree of deterioration in NBTI characteristics depends on the gate width so that with a decrease in the gate width, the p channel MISFET is presumed to have severely deteriorated NBTI characteristics.
  • a region, of the nitride layer SN formed on the inner surface of the trench TR in the semiconductor substrate SB, close to the gate insulating film or channel region of the MISFET has a large influence on the deterioration in NBTI characteristics.
  • a portion of the nitride layer formed on the upper portion of the side surface of the trench TR has a large influence.
  • a portion of the nitride layer SN formed on the lower portion of the side surface of the trench TR or on the bottom surface of the trench TR has a relatively small influence on the deterioration in NBTI characteristics because it is distant from the gate insulating film or channel region of the MISFET.
  • the nitride layer SN is not formed at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST. This means that on the inner surface (side surface and bottom surface) of the trench TR in the semiconductor substrate SB, the nitride layer SN is not formed on the upper portion of the side surface of the trench TR. More specifically, the upper portion (portion adjacent to the upper portion of the side surface of the trench TR) of the nitride layer SN formed on the inner surface (side surface and bottom surface) of the trench TR is oxidized into an oxidation portion OX.
  • the other portion of the nitride layer SN that is, a portion of the nitride layer SN formed on the inner surface of the trench TR except for the upper portion of the side surface is left as is in Second Embodiment.
  • the nitride layer SN formed on the entire inner surface of the trench TR in the semiconductor substrate SB causes deterioration in NBTI characteristics so that the nitride layer SN is not formed on the upper portion of the side surface of the trench TR where an influence on the deterioration in NBTI characteristics is likely to become large, compared with another portion of the inner surface of the trench TR in the semiconductor substrate SB.
  • the semiconductor device of Second Embodiment compared with the semiconductor device of Second Investigation Example shown in FIG.
  • the semiconductor device having such a structure can therefore have improved reliability.
  • the nitride layer SN is not formed at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST in order to suppress or prevent deterioration in NBTI characteristics.
  • a portion of the nitride layer SN formed on the inner surface of the trench TR in the semiconductor substrate SB and likely to contribute to deterioration in NBTI characteristics is near the gate insulating film or channel region of the MISFET. In short, it is the nitride layer SN present in the vicinity of a boundary between the element isolation region ST and the channel region below the gate electrode GE 1 .
  • nitride layer SN which is at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST, in a region below the gate electrode GE 1 (that is, a region overlapping with the gate electrode GE 1 in plan view).
  • the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST, in the entire outer periphery of the active region AC 1 .
  • the trench TR surrounding the active region AC 1 has, on the lower portion of the side surface and the bottom surface thereof, the nitride layer SN, but the trench TR does not have, on the upper portion of the side surface thereof, the nitride layer SN.
  • Second Embodiment it is also possible to avoid, only in a region in the periphery of the active region AC 1 and at the same time, below the gate electrode GE 1 (that is, a region overlapping with the gate electrode GE 1 in plan view), forming the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST.
  • the gate electrode GE 1 has, in a region therebelow, the nitride layer SN on the lower side surface and the bottom surface of the trench TR, but does not have the nitride layer SN on the upper portion of the side surface of the trench TR.
  • the trench TR In a region not overlapping with the gate electrode GE 1 in plan view, the trench TR has the nitride layer SN on the entire side surface and the bottom surface thereof.
  • the trench TR has the nitride layer SN obtained by nitriding the inner surface thereof, but the nitride layer SN is not formed, in at least a region below the gate electrode GE 1 (that is, a region overlapping with the gate electrode GE 1 in plan view), at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST.
  • the trench TR has the nitride layer SN obtained by nitriding the inner surface thereof but the nitride layer SN is not formed, in at least a region below the gate electrode GE 1 (that is, a region overlapping with the gate electrode GE 1 in plan view), on the upper portion of the side surface of the trench TR.
  • the MISFET(Qp) thus obtained can be suppressed or prevented from having deteriorated NBTI characteristics.
  • fluorine can be introduced only into a region hatched with dots in FIG. 25
  • an upper portion of the nitride layer SN can also be oxidized into the oxidation portion OX only in a region hatched with dots in FIG. 25 .
  • Second Embodiment or First Embodiment generation of crystal defects in the semiconductor substrate SB in the active region due to expansion of the element isolation region ST can be suppressed or prevented and in addition, deterioration in NBTI characteristics can be suppressed or prevented. As a result, the semiconductor device thus obtained can have improved reliability.
  • First Embodiment is advantageous over Second Embodiment from the standpoint of preventing as much as possible generation of crystal defects in the semiconductor substrate SB in the active region due to expansion of the element isolation region ST.
  • the semiconductor device of Second Embodiment does not have the nitride layer SN on the upper portion of the side surface of the trench TR in the semiconductor substrate SB, while the semiconductor device of First Embodiment has the nitride layer SN also on the upper portion of the side surface of the trench TR in the semiconductor substrate SB and therefore has the nitride layer SN on the entire inner surface of the trench TR in the semiconductor substrate SB.
  • the trench TR in the semiconductor substrate SB has, on the entire inner surface thereof, the nitride layer SN, the element isolation region ST can be suppressed or prevented more properly from being re-oxidized and thereby expanding.
  • Second Embodiment it is not necessary to introduce (implant) fluorine (F) for preventing deterioration in NBTI characteristics into the semiconductor substrate SB so that a risk of the characteristics of MISFET undergoing an unintentional change due to introduction of fluorine (F) can be avoided.
  • FIGS. 39 and 40 are fragmentary cross-sectional views showing a semiconductor device of Third Modification Example of Second Embodiment, in which FIG. 39 shows a cross-section (cross-section along a gate length direction) corresponding to FIG. 31 , and FIG. 40 shows a cross-section (cross-section along a gate width direction) corresponding to FIG. 32 .
  • the semiconductor device of Third Modification Example of Second Embodiment shown in FIGS. 39 and 40 has, on a semiconductor substrate SB, both a p channel MISFET and an n channel MISFET.
  • the semiconductor device of Third Modification Example of Second Embodiment shown in FIGS. 39 and 40 is different in the following points from the semiconductor device of First Modification Example of First Embodiment shown in FIGS. 26 and 27 .
  • the semiconductor device of Third Modification Example of Second Embodiment shown in FIGS. 39 and 40 does not have fluorine (F) in the vicinity of a boundary between the element isolation region ST and the semiconductor substrate SB in the active regions AC 1 and AC 2 .
  • the semiconductor device of Third Modification Example does not have a region corresponding to the fluorine implanted region FR. Manufacturing steps of the semiconductor device of Third Modification Example therefore do not include a step corresponding to the above-described ion implantation IM 1 .
  • the semiconductor device of Third Modification Example of Second Embodiment has a nitride layer obtained by nitriding the inner surface of the trench TR in the semiconductor substrate SB, but does not have the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST.
  • the semiconductor device of Third Modification Example of Second Embodiment does not have the nitride layer SN on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 but has it in the other region of the inner surface (side surface and bottom surface) of the trench TR surrounding the active region AC 1 .
  • the upper portion of the nitride layer SN formed on the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 is oxidized into an oxidation portion OX.
  • the nitride layer SN present between the element isolation region ST surrounding the active region AC 1 and the semiconductor substrate SB in the active region AC 1 has a configuration similar to that of the nitride layer SN present between the element isolation region ST surrounding the active region AC 1 and the semiconductor substrate SB in the active region AC 1 as shown above in FIGS. 30 to 32 .
  • the other configuration of the semiconductor device of Third Modification Example of Second Embodiment is essentially similar to that of First Modification Example of First Embodiment so that an overlapping description is omitted here.
  • the semiconductor device of Third Modification Example shown in FIGS. 39 and 40 has the nitride layer SN obtained by nitriding the inner surface of the trench TR in the semiconductor substrate SB, but does not have the nitride layer at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 for p channel MISFET and the upper portion of the element isolation region ST surrounding the active region AC 1 .
  • the semiconductor device does not have the nitride layer SN on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 .
  • the active region AC 1 for p channel MISFET therefore, generation of crystal defects in the the semiconductor substrate SB in the active region AC 1 due to expansion of the element isolation region ST can be suppressed or prevented and in addition, the p channel MISFETQp formed in the active region AC 1 can be suppressed or prevented from having deteriorated NBTI characteristics.
  • the reason is similar to that described above for the semiconductor device of FIGS. 30 to 32 .
  • the nitride layer SN is sometimes present and the nitride layer is sometimes not present.
  • the nitride layer SN is also present on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 2 .
  • the trench TR surrounding the active region AC 2 therefore has the nitride layer SN on the entire inner surface thereof.
  • the nitride layer SN When the nitride layer SN is not present at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 2 for n channel MISFET and the upper portion of the element isolation region ST, the nitride layer SN is not present on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 2 and the nitride layer SN is present in the other region of the inner surface of the trench TR surrounding the active region AC 2 .
  • the nitride layer SN When the nitride layer SN is not present at a boundary between the upper portion of the semiconductor substrate SB in the active regions (AC 1 and AC 2 ) and the upper portion of the element isolation region ST, in both the active region AC 1 for p channel MISFET and the active region AC 2 for n channel MISFET, the p channel MISFETQp and the n channel MISFETQn can each be prevented from having deteriorated NBTI characteristics. In addition, in both the p channel MISFETQp and the n channel MISFETQn, the deterioration degree of NBTI characteristics can be suppressed or prevented from depending on the gate width.
  • the p channel MISFET requires suppression of deterioration in NBTI characteristics and compared with the p channel MISFET, the n channel MISFET does not require suppression of deterioration in NBTI characteristics so eagerly.
  • the nitride layer SN is preferably present at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 2 for n channel MISFET and the upper portion of the element isolation region ST.
  • the nitride layer SN is also present preferably on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 2 for n channel MISFET and therefore, the nitride layer SN is present preferably on the entire side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 2 .
  • the active region AC 2 for n channel MISFET and the element isolation region ST surrounding the active region may be covered with the photoresist pattern PR 2 in advance.
  • the upper portion of the nitride layer SN present between the semiconductor substrate SB in the active region AC 1 and the element isolation region ST is oxidized into an oxidation portion OX by the oxidation treatment shown in FIGS. 35 and 36 , but the upper portion of the nitride layer SN present between the semiconductor substrate SB in the active region AC 2 and the element isolation region ST remains unoxidized.
  • the semiconductor device thus manufactured can therefore has a structure not having the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 for p channel MISFET and the upper portion of the element isolation region ST, but having the nitride layer at a boundary between the the upper portion of the semiconductor substrate SB in the active region AC 2 for n channel MISFET and the upper portion of the element isolation region ST.
  • each of the p channel MISFETQp and the n channel MISFETQn is similar to that of First Embodiment (including First Modification Example) so that a description on it is omitted here.
  • FIGS. 41 and 42 are fragmentary cross-sectional views showing a semiconductor device of Fourth Modification Example of Second Embodiment, in which FIG. 41 shows, similar to FIG. 39 , a cross-section (cross-section along a gate length direction) corresponding to FIG. 31 and FIG. 42 shows, similar to FIG. 40 , a cross-section (cross-section along a gate width direction) corresponding to FIG. 32 .
  • the semiconductor device of Fourth Modification Example of Second Embodiment shown in FIGS. 41 and 42 also has, on the semiconductor substrate SB, a low-breakdown-voltage MISFET (Qp) and a high-breakdown-voltage MISFET (Qp 3 ).
  • Qp low-breakdown-voltage MISFET
  • Qp 3 high-breakdown-voltage MISFET
  • the semiconductor device of Fourth Modification Example of Second Embodiment shown in FIGS. 41 and 42 is different in the following points from the semiconductor device of Second Modification Example of First Embodiment shown in FIGS. 28 and 29 .
  • the semiconductor device of Fourth Modification Example of Second Embodiment shown in FIGS. 41 and 42 does not have fluorine (F) introduced into a region in the vicinity of a boundary between the element isolation region ST and the semiconductor substrate SB in the active regions AC 1 and AC 3 .
  • F fluorine
  • the semiconductor device of Fourth Modification Example does not have a region corresponding to the fluorine implanted region FR.
  • Manufacturing steps of the semiconductor device of Fourth Modification Example therefore do not include a step corresponding to the above-described ion implantation IM 1 .
  • the semiconductor device of Fourth Modification Example of Second Embodiment has a nitride layer SN obtained by nitriding the inner surface of the trench TR in the semiconductor substrate SB, but does not have the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 and the upper portion of the element isolation region ST.
  • the semiconductor device of Fourth Modification Example of Second Embodiment does not have the nitride layer SN on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 , but has it in the other region of the inner surface (side surface and bottom surface) of the trench TR surrounding the active region AC 1 .
  • the upper portion of the nitride layer SN formed on the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 is oxidized into an oxidation portion OX.
  • the nitride layer SN present between the element isolation region ST surrounding the active region AC 1 and the semiconductor substrate SB in the active region AC 1 has a configuration similar to that of the nitride layer SN present between the element isolation region ST surrounding the active region AC 1 and the semiconductor substrate SB in the active region AC 1 as shown in FIGS. 30 to 32 .
  • the other configuration of the semiconductor device of Fourth Modification Example of Second Embodiment is essentially similar to that of the semiconductor device of Second Modification Example of First Embodiment so that an overlapping description is omitted here.
  • the semiconductor device of Fourth Modification Example shown in FIGS. 41 and 42 has the nitride layer SN obtained by nitriding the inner surface of the trench TR in the semiconductor substrate SB but does not have the nitride layer at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 for low-breakdown-voltage p channel MISFET and the upper portion of the element isolation region ST surrounding the active region AC 1 .
  • the nitride layer SN is not present on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 1 .
  • the active region AC 1 for low-breakdown-voltage MISFET generation of crystal defects in the semiconductor substrate SB in the active region AC 1 due to expansion of the element isolation region ST can be suppressed or prevented.
  • the low-breakdown-voltage MISFET (Qp) formed in the active region AC 1 can be suppressed or prevented from having deteriorated NBTI characteristics. The reason is similar to that described for the semiconductor device shown in FIGS. 30 to 32 .
  • the semiconductor device sometimes has the nitride layer SN and sometimes does not have the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET and the upper portion of the element isolation region ST surrounding the active region AC 3 .
  • the nitride layer SN When the nitride layer SN is present at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET and the upper portion of the element isolation region ST, the nitride layer SN is also present on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 3 and the nitride layer SN is present on the entire inner surface of the trench TR surrounding the active region AC 3 .
  • the nitride layer SN When the nitride layer SN is not present at the boundary between the upper portion of the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET and the upper portion of the element isolation region ST, the nitride layer SN is not present on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 3 and the nitride layer SN is present in the other region of the inner surface of the trench TR surrounding the active region AC 3 .
  • both the low-breakdown-voltage MISFET (Qp) and the high-breakdown-voltage MISFET (Qp 3 ) can be suppressed or prevented from having deteriorated NBTI characteristics.
  • a deterioration degree of NBTI characteristics can be suppressed or prevented from depending on the gate width.
  • the nitride layer SN is formed preferably at the boundary between the upper portion of the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET (Qp 3 ) and the upper portion of the element isolation region ST.
  • the nitride layer SN is preferably formed also on the upper portion of the side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET (Qp 3 ) and therefore, the nitride layer SN is present preferably on the entire side surface of the trench TR on the side adjacent to the semiconductor substrate SB in the active region AC 3 .
  • the semiconductor device thus obtained has a structure not having the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 1 for low-breakdown-voltage MISFET (Qp) and the upper portion of the element isolation region ST, while having the nitride layer SN at a boundary between the upper portion of the semiconductor substrate SB in the active region AC 3 for high-breakdown-voltage MISFET (Qp 3 ) and the upper portion of the element isolation region ST.
  • each of the low-breakdown-voltage p channel MISFETQp and the high-breakdown-voltage p channel MISFETQp 3 is similar to that of First Embodiment (including Second Modification Example) so that a description on it is omitted.
  • a method of manufacturing a semiconductor device including the steps of:
  • step (f) after the step (e), forming a first gate electrode for first MISFET on the semiconductor substrate in the first active region via a first gate insulating film;

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