JP2016096200A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
<半導体装置の構造について>
本実施の形態の半導体装置を図面を参照して説明する。図1および図2は、本実施の形態の半導体装置の要部平面図であり、図3および図4は、本実施の形態の半導体装置の要部断面図である。図1のA1−A1線の断面図が、図3にほぼ対応し、図1のB1−B1線の断面図が、図4にほぼ対応している。また、図1と図2とは、同じ平面領域が示されているが、図2では、フッ素が注入されている領域(フッ素注入領域FR)をドットのハッチングを付して示し、また、ゲート電極GE1の位置を二点鎖線で示してある。なお、図1および図2に示されるX方向は、ゲート電極GE1のゲート長方向に対応し、従って、ゲート電極GE1の下に形成されるチャネル領域のチャネル長方向に対応し、図1および図2に示されるY方向は、ゲート電極GE1のゲート幅方向に対応し、従って、ゲート電極GE1の下に形成されるチャネル領域のチャネル幅方向に対応している。図3は、X方向に沿った断面図であり、図4は、Y方向に沿った断面図である。なお、図1において、ゲート電極GE1のゲート幅W1を、符号W1を付して示してある。
次に、本実施の形態の半導体装置の製造工程について説明する。
次に、本発明者が検討した検討例について説明する。
本実施の形態の半導体装置は、半導体基板SBと、半導体基板SBに形成された溝TR内に埋め込まれた素子分離領域STと、素子分離領域STで囲まれた活性領域AC1(第1活性領域)の半導体基板SB上に絶縁膜GF(第1ゲート絶縁膜)を介して形成されたゲート電極GE1と、活性領域AC1の半導体基板SBに形成されたソース・ドレイン領域SD1と、を有している。
次に、本実施の形態の変形例(適用例)について説明する。
図28および図29は、本実施の形態の第2変形例の半導体装置を示す要部断面図であり、図28には、上記図26と同様に、上記図3に対応する断面(すなわちゲート長方向に沿った断面)が示され、図29には、上記図27と同様に、上記図4に対応する断面(すなわちゲート幅方向に沿った断面)が示されている。
<半導体装置の構造について>
本実施の形態2の半導体装置を図面を参照して説明する。図30は、本実施の形態の半導体装置の要部平面図であり、図31および図32は、本実施の形態の半導体装置の要部断面図である。図30〜図32は、上記実施の形態1の上記図1、図3および図4にそれぞれ対応するものである。このため、図30のA2−A2線の断面図が、図31にほぼ対応し、図30のB2−B2線の断面図が、図32にほぼ対応している。
次に、本実施の形態2の半導体装置の製造工程について説明する。
本実施の形態2の半導体装置は、半導体基板SBと、半導体基板SBに形成された溝TR内に埋め込まれた素子分離領域STと、素子分離領域STで囲まれた活性領域AC1(第1活性領域)の半導体基板SB上に絶縁膜GF(第1ゲート絶縁膜)を介して形成されたゲート電極GE1と、活性領域AC1の半導体基板SBに形成されたソース・ドレイン領域SD1と、を有している。
次に、本実施の形態2の変形例(適用例)について説明する。
図41および図42は、本実施の形態2の第4変形例の半導体装置を示す要部断面図であり、図41には、上記図39と同様に、上記図31に対応する断面(すなわちゲート長方向に沿った断面)が示され、図42には、上記図40と同様に、上記図32に対応する断面(すなわちゲート幅方向に沿った断面)が示されている。
(a)半導体基板を用意する工程、
(b)前記半導体基板に溝を形成する工程、
(c)前記半導体基板の前記溝の内面を窒化して窒化層を形成する工程、
(d)前記(c)工程後、前記溝内に、酸化シリコンを主体とする素子分離領域を形成する工程、
(e)前記素子分離領域と前記素子分離領域で囲まれた第1活性領域の前記半導体基板との境界において、前記窒化層の上部を酸化する工程、
(f)前記(e)工程後、前記第1活性領域の前記半導体基板上に、第1ゲート絶縁膜を介して、第1MISFET用の第1ゲート電極を形成する工程、
(g)前記第1活性領域の前記半導体基板に、前記第1MISFET用の第1ソース・ドレイン領域を形成する工程、
を有し、
前記第1ゲート電極は、一部が前記素子分離領域上に延在する、半導体装置の製造方法。
付記1記載の半導体装置の製造方法において、
前記第1MISFETは、pチャネル型である、半導体装置の製造方法。
GE1 ゲート電極
SB 半導体基板
ST 素子分離領域
TR 溝
Claims (13)
- 半導体基板と、
前記半導体基板に形成された溝内に埋め込まれた、酸化シリコンを主体とする素子分離領域と、
前記素子分離領域で囲まれた第1活性領域の前記半導体基板上に、第1ゲート絶縁膜を介して形成された、第1MISFET用の第1ゲート電極と、
前記第1活性領域の前記半導体基板に形成された、前記第1MISFET用の第1ソース・ドレイン領域と、
を有し、
前記半導体基板の前記溝の内面は窒化されており、
前記第1ゲート電極は、一部が前記素子分離領域上に延在し、
前記第1ゲート電極の下において、前記素子分離領域と前記第1MISFETのチャネル領域との境界付近に、フッ素が導入されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1MISFETは、pチャネル型である、半導体装置。 - 請求項1記載の半導体装置において、
前記素子分離領域で囲まれた第2活性領域の前記半導体基板上に、第2ゲート絶縁膜を介して形成された、第2MISFET用の第2ゲート電極と、
前記第2活性領域の前記半導体基板に形成された、前記第2MISFET用の第2ソース・ドレイン領域と、
を有し、
前記第2ゲート電極は、一部が前記素子分離領域上に延在し、
前記第2ゲート電極の下において、前記素子分離領域と前記第2MISFETのチャネル領域との境界付近には、フッ素が導入されていない、半導体装置。 - 請求項3記載の半導体装置において、
前記第1MISFETは、pチャネル型であり、
前記第2MISFETは、nチャネル型である、半導体装置。 - 請求項3記載の半導体装置において、
前記第2ゲート絶縁膜は、前記第1ゲート絶縁膜よりも厚い、半導体装置。 - 半導体基板と、
前記半導体基板に形成された溝内に埋め込まれた、酸化シリコンを主体とする素子分離領域と、
前記素子分離領域で囲まれた第1活性領域の前記半導体基板上に、第1ゲート絶縁膜を介して形成された、第1MISFET用の第1ゲート電極と、
前記第1活性領域の前記半導体基板に形成された、前記第1MISFET用の第1ソース・ドレイン領域と、
を有し、
前記第1ゲート電極は、一部が前記素子分離領域上に延在し、
前記半導体基板の前記溝の内面は窒化されて窒化層が形成されており、
前記第1ゲート電極の下において、前記第1活性領域の前記半導体基板の上部と前記素子分離領域の上部との境界には、前記窒化層が形成されていない、半導体装置。 - 請求項6記載の半導体装置において、
前記第1MISFETは、pチャネル型である、半導体装置。 - 請求項6記載の半導体装置において、
前記素子分離領域で囲まれた第2活性領域の前記半導体基板上に、第2ゲート絶縁膜を介して形成された、第2MISFET用の第2ゲート電極と、
前記第2活性領域の前記半導体基板に形成された、前記第2MISFET用の第2ソース・ドレイン領域と、
を有し、
前記第2ゲート電極は、一部が前記素子分離領域上に延在し、
前記第2活性領域の前記半導体基板の上部と前記素子分離領域の上部との境界においても、前記窒化層が形成されている、半導体装置。 - 請求項8記載の半導体装置において、
前記第1MISFETは、pチャネル型であり、
前記第2MISFETは、nチャネル型である、半導体装置。 - 請求項8記載の半導体装置において、
前記第2ゲート絶縁膜は、前記第1ゲート絶縁膜よりも厚い、半導体装置。 - (a)半導体基板を用意する工程、
(b)前記半導体基板に溝を形成する工程、
(c)前記半導体基板の前記溝の内面を窒化する工程、
(d)前記(c)工程後、前記溝内に、酸化シリコンを主体とする素子分離領域を形成する工程、
(e)前記素子分離領域と、前記素子分離領域で囲まれた第1活性領域の前記半導体基板との境界付近に、フッ素をイオン注入する工程、
(f)前記(e)工程後、前記第1活性領域の前記半導体基板上に、第1ゲート絶縁膜を介して、第1MISFET用の第1ゲート電極を形成する工程、
(g)前記第1活性領域の前記半導体基板に、前記第1MISFET用の第1ソース・ドレイン領域を形成する工程、
を有し、
前記第1ゲート電極は、一部が前記素子分離領域上に延在する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記第1ゲート電極の下において、前記素子分離領域と前記第1MISFETのチャネル領域との境界付近に、前記(e)工程でイオン注入したフッ素が存在している、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第1MISFETは、pチャネル型である、半導体装置の製造方法。
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