JP2016152255A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016152255A JP2016152255A JP2015027467A JP2015027467A JP2016152255A JP 2016152255 A JP2016152255 A JP 2016152255A JP 2015027467 A JP2015027467 A JP 2015027467A JP 2015027467 A JP2015027467 A JP 2015027467A JP 2016152255 A JP2016152255 A JP 2016152255A
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Abstract
Description
<半導体装置の構造について>
本実施の形態の半導体装置を、図面を参照して説明する。図1は、本実施の形態の半導体装置の要部断面図であり、図2および図3は、本実施の形態の半導体装置の要部平面図である。図2と図3とは、同じ平面領域が示されている。理解を簡単にするために、図2では、p+型半導体領域PR1、n+型半導体領域NR1、n+型半導体領域NR2および電極FPに細線の斜線のハッチングを付し、図3では、p+型半導体領域PR1、n+型半導体領域NR1およびn+型半導体領域NR2に細線の斜線のハッチングを付し、素子分離領域LSに太線の斜線のハッチングを付してある。また、図3では、素子分離領域LSに形成された溝TRの位置を点線で示してある。図2および図3のA−A線の断面図が、図1にほぼ対応している。
次に、本実施の形態の半導体装置の製造工程を、図面を参照して説明する。図4〜図31は、本実施の形態の半導体装置の製造工程中の要部断面図である。
本発明者が検討した検討例の半導体装置について説明する。図32は、本発明者が検討した第1検討例の半導体装置の要部断面図であり、図33は、本発明者が検討した第2検討例の半導体装置の要部断面図であり、いずれも本実施の形態の上記図1に相当する断面が示されている。
本実施の形態の半導体装置は、バイポーラトランジスタを備える半導体装置であって、半導体基板SUBと、半導体基板SUBに形成されたp型ウエルPW1(第1半導体領域)と、p型ウエルPW1に互いに離間して形成されたp+型半導体領域PR1(第2半導体領域)およびn+型半導体領域NR1(第3半導体領域)と、を有している。本実施の形態の半導体装置は、更に、p+型半導体領域PR1とn+型半導体領域NR1との間の半導体基板SUBの主面に形成された素子分離領域LS(素子分離絶縁膜)と、素子分離領域LS上に形成された電極FP(第1電極)と、を有している。本実施の形態の半導体装置は、更に、半導体基板SUB上に素子分離領域LSおよび電極FPを覆うように形成された層間絶縁膜ILと、層間絶縁膜ILに埋め込まれたエミッタ用プラグPGE(第1プラグ)、プラグPGF(第2プラグ)およびベース用プラグPGB(第3プラグ)と、を有している。
次に、本実施の形態の変形例について説明する。
図38は、本実施の形態2の半導体装置の要部断面図であり、図39および図40は、本実施の形態2の半導体装置の要部平面図である。図38は、上記図1に相当するものであり、図39は、上記図2に相当するものであり、図40は、上記図3に相当するものである。図39と図40とは、同じ平面領域が示されている。理解を簡単にするために、図39では、p+型半導体領域PR1、n+型半導体領域NR1、n+型半導体領域NR2、電極FPおよび電極FP2に細線の斜線のハッチングを付し、図40では、p+型半導体領域PR1、n+型半導体領域NR1およびn+型半導体領域NR2に細線の斜線のハッチングを付し、素子分離領域LSに太線の斜線のハッチングを付してある。また、図40では、素子分離領域LSに形成された溝TR,TR2の位置を点線で示してある。図39および図40のC−C線の断面図が、図38にほぼ対応している。
FP,FP2 電極
IL 層間絶縁膜
LS 素子分離領域
M1B ベース用配線
M1C コレクタ用配線
M1E エミッタ用配線
NB n+型埋込領域
NR1,NR2 n+型半導体領域
NS n+型シンカー領域
NW1 n型ウエル
PR1 p+型半導体領域
PW1 p型ウエル
SB 基板本体
SUB 半導体基板
TR,TR2 溝
PGB ベース用プラグ
PGC コレクタ用プラグ
PGE エミッタ用プラグ
PGF,PGF2 プラグ
Claims (15)
- バイポーラトランジスタを備える半導体装置であって、
半導体基板と、
前記半導体基板に形成された第1導電型の第1半導体領域と、
前記第1半導体領域に互いに離間して形成された、前記第1導電型の第2半導体領域および前記第1導電型とは逆の第2導電型の第3半導体領域と、
前記第2半導体領域と前記第3半導体領域との間の前記半導体基板の主面に形成された素子分離絶縁膜と、
前記素子分離絶縁膜上に形成された第1電極と、
前記半導体基板上に、前記素子分離絶縁膜および前記第1電極を覆うように形成された層間絶縁膜と、
前記層間絶縁膜に埋め込まれた第1プラグ、第2プラグおよび第3プラグと、
を有し、
前記第2半導体領域の不純物濃度は、前記第1半導体領域の不純物濃度よりも高く、
前記第1半導体領域および前記第2半導体領域は、前記バイポーラトランジスタのベース用の半導体領域であり、
前記第3半導体領域は、前記バイポーラトランジスタのエミッタ用の半導体領域であり、
前記第1プラグは、前記第3半導体領域上に配置されて、前記第3半導体領域と電気的に接続され、
前記第2プラグは、前記第1電極上に配置されて、前記第1電極と電気的に接続され、
前記第3プラグは、前記第2半導体領域上に配置されて、前記第2半導体領域と電気的に接続され、
前記第1プラグと前記第2プラグとは、電気的に接続され、
平面視において、前記第1電極は、前記第2半導体領域と前記第3半導体領域との間に形成され、
前記第1電極の少なくとも一部は、前記素子分離絶縁膜に形成された第1溝内に埋め込まれている、半導体装置。 - 請求項1記載の半導体装置において、
平面視において、前記第1溝は、前記第2半導体領域と前記第3半導体領域との間に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域と前記第3半導体領域との間に位置する前記素子分離絶縁膜の下には、前記第1半導体領域が延在している、半導体装置。 - 請求項1記載の半導体装置において、
前記層間絶縁膜上に形成された第1配線および第2配線を更に有し、
前記第1配線は、前記第1プラグを介して前記第3半導体領域と電気的に接続され、かつ、前記第2プラグを介して前記第1電極と電気的に接続され、
前記第2配線は、前記第3プラグを介して前記第2半導体領域と電気的に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1溝内に埋め込まれた部分の前記第1電極の直下の前記素子分離絶縁膜の厚みは、前記第1溝が形成されていない領域における前記素子分離絶縁膜の厚みよりも小さい、半導体装置。 - 請求項5記載の半導体装置において、
前記第1溝内に埋め込まれた部分の前記第1電極の直下の前記素子分離絶縁膜の厚みは、前記第1溝が形成されていない領域における前記素子分離絶縁膜の厚みの半分以下である、半導体装置。 - 請求項5記載の半導体装置において、
前記第1溝内に埋め込まれた部分の前記第1電極の直下の前記素子分離絶縁膜の厚みは、50nm以上である、半導体装置。 - 請求項5記載の半導体装置において、
前記第1溝内に埋め込まれた部分の前記第1電極の直下の前記素子分離絶縁膜の厚みは、50〜200nmである、半導体装置。 - 請求項1記載の半導体装置において、
前記素子分離絶縁膜は、LOCOS酸化膜またはSTI絶縁膜である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体領域を内包するように前記半導体基板に形成された、前記第2導電型の第4半導体領域と、
前記第4半導体領域内に、前記第1半導体領域と離間するように形成された、前記第2導電型の第5半導体領域と、
前記層間絶縁膜に埋め込まれた第4プラグと、
を更に有し、
前記第5半導体領域の不純物濃度は、前記第4半導体領域の不純物濃度よりも高く、
前記第4半導体領域および前記第5半導体領域は、前記バイポーラトランジスタのコレクタ用の半導体領域であり、
前記第4プラグは、前記第5半導体領域上に配置されて、前記第5半導体領域と電気的に接続されている、半導体装置。 - 請求項10記載の半導体装置において、
前記半導体基板に形成され、前記第4半導体領域の下に位置する、前記第2導電型の埋め込み半導体領域を更に有し、
前記埋め込み半導体領域の不純物濃度は、前記第4半導体領域の不純物濃度よりも高い、半導体装置。 - 請求項10記載の半導体装置において、
前記層間絶縁膜上に形成された第3配線を更に有し、
前記第3配線は、前記第4プラグを介して前記第5半導体領域と電気的に接続されている、半導体装置。 - 請求項10記載の半導体装置において、
前記第2半導体領域、前記第3半導体領域および前記第5半導体領域を囲むように、前記半導体基板の主面に前記素子分離絶縁膜が形成されており、
前記素子分離絶縁膜上に形成された第2電極と、前記層間絶縁膜に埋め込まれた第5プラグとを更に有し、
前記第5プラグは、前記第2電極上に配置されて、前記第2電極と電気的に接続され、
前記第5プラグと前記第3プラグとは、電気的に接続され、
前記第2電極の少なくとも一部は、前記素子分離絶縁膜に形成された第2溝内に埋め込まれている、半導体装置。 - 請求項13記載の半導体装置において、
前記層間絶縁膜上に形成された第1配線および第2配線を更に有し、
前記第1配線は、前記第1プラグを介して前記第3半導体領域と電気的に接続され、かつ、前記第2プラグを介して前記第1電極と電気的に接続され、
前記第2配線は、前記第3プラグを介して前記第2半導体領域と電気的に接続され、かつ、前記第5プラグを介して前記第2電極と電気的に接続されている、半導体装置。 - 請求項13記載の半導体装置において、
平面視において、前記第2電極は、前記第2半導体領域、前記第3半導体領域および第1電極を囲み、かつ、前記第1半導体領域と重なるように、形成されている、半導体装置。
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