CN111430447B - 电流源及其形成方法 - Google Patents
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 45
- 150000002500 ions Chemical class 0.000 claims description 24
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Abstract
本发明提供了一种电流源及其形成方法。由于电流源中的发射区包括相互连接的深阱区和延伸区,并直接围绕基区,因此该发射区不仅可用于构成电流源中的双极型晶体管,并且还可用于隔离基区。如此一来,即可使得本发明中的电流源能够免除沟槽隔离结构的限制,有利于实现器件尺寸的缩减,并且使本发明中的电流源器件与其他半导体逻辑器件之间,即使利用深度较低的沟槽隔离结构仍能够满足电性隔离的需求。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种电流源及其形成方法。
背景技术
电流源(Current Source)是一种应用广泛的基本电路单元,常用的例如有镜像电流源和比例电路源等。通常而言,电流源中设置有多个晶体管并分别构成输入端和输出端,并且输入端的输入电流可以镜像到输出端的输出电流。然而,现有的电流源器件难于与半导体逻辑器件集成。
例如,在专利号为US6255713B1中其公开了一种电流源,具体参考图1所示,所述电流源包括N掺杂的发射区(N-Well)、位于所述发射区上方的P掺杂的基区(P-Well)以及多个位于所述基区中的N掺杂的集电区,以构成多个用于实现电流镜像的双极型晶体管,并且还进一步利用沟槽隔离结构(OX)将该多个双极型晶体管进行隔离。具体的,图1所示的沟槽隔离结构(OX)围绕电流源的基区(P-Well),以隔离基区(P-Well),并且沟槽隔离结构(OX)不会阻断发射区(N-Well),以便于实现所述发射区(N-Well)的信号引出。因此,图1所示的沟槽隔离结构(OX)延伸在衬底中的深度应当低于基区(P-Well)的深度,并且发射区(N-Well)延伸在衬底中的深度应当进一步的低于沟槽隔离结构(OX)的深度。
由此可见,如上所述的电流源中,需使沟槽隔离结构的深度低于基区的深度,以隔离基区。然而应当认识到,基于现有的半导体技术,所形成的沟槽隔离结构的深度通常是不低于基区的深度,如此一来,将导致现有的电流源器件由于需更大深度的沟槽隔离结构与之匹配,进而无法与其他半导体逻辑器件兼容。
发明内容
本发明的目的在于提供一种电流源,以解决现有的电流源由于其结构限制,导致无法与其他半导体逻辑器件兼容的问题。
为解决上述技术问题,本发明提供一种电流源,包括:
衬底;
第一掺杂类型的基区,形成在所述衬底中;
第二掺杂类型的发射区,形成在所述衬底中并环绕所述基区,其中所述发射区包括一深阱区和一延伸区,所述深阱区位于所述基区的下方,所述延伸区从所述基区的侧面环绕所述基区,并且所述延伸区的底部连接所述深阱区,所述延伸区的顶部延伸至所述衬底的顶表面;
第二掺杂类型的第一集电区,形成在所述衬底的所述基区中;以及,
至少一个第二掺杂类型的第二集电区,形成在所述衬底的所述基区中。
可选的,所述电流源还包括:
第一掺杂类型的基极接触区,形成在所述衬底的所述基区中,并且所述基极接触区和所述第一集电区均电性均连接至同一电源端口。
可选的,所述基极接触区和所述第一集电区均延伸至衬底的顶表面,并且在所述基极接触区的衬底顶表面上以及所述第一集电区的衬底顶表面上均形成有金属硅化物层,以通过所述金属硅化物层电性连接至所述电源端口。
可选的,所述基极接触区具有相对于所述第二集电区更靠近所述第一集电区的部分,位于所述基极接触区上且靠近所述第一集电区的金属硅化物层和位于所述第一集电区上的金属硅化物层相互连接。
可选的,所述基极接触区的离子掺杂浓度大于所述基区的离子掺杂浓度,并且所述基极接触区具有位于所述第一集电区和所述第二集电区之间的部分。
可选的,所述基极接触区中位于所述第一集电区和所述第二集电区之间的部分邻接所述第一集电区。
可选的,所述基极接触区具有位于所述延伸区和所述第一集电区之间部分。
可选的,所述基极接触区中位于所述延伸区和所述第一集电区之间的部分邻接所述延伸区。
可选的,所述基极接触区具有位于所述延伸区和所述第二集电区之间部分。
可选的,所述基极接触区中位于所述延伸区和所述第二集电区之间的部分邻接所述延伸区。
可选的,所述电流源还包括:
第二掺杂类型的掩埋区,所述掩埋区连接所述深阱区和所述基区,并且所述掩埋区的离子掺杂浓度大于所述深阱区的离子掺杂浓度。
可选的,所述电流源还包括:
第二掺杂类型的发射极接触区,形成在所述延伸区中,并且所述发射极接触区的离子掺杂浓度高于所述延伸区的离子掺杂浓度。
可选的,所述电流源还包括:
沟槽隔离结构,形成在所述衬底中以界定出所述电流源的有源区域,所述发射区形成所述有源区域中,并且所述沟槽隔离结构延伸在所述衬底中的深度位置不低于所述基区的深度位置。
本发明的另一目的在于,提供一种电流源的形成方法,包括:
提供一衬底;
形成第一掺杂类型的基区和第二掺杂类型的发射区在所述衬底中,所述发射区包括一深阱区和一延伸区,所述深阱区位于所述基区的下方,所述延伸区从所述基区的侧面环绕所述基区,并且所述延伸区的底部连接所述深阱区,所述延伸区的顶部延伸至所述衬底的顶表面;以及,
形成第二掺杂类型的第一集电区和至少一个第二掺杂类型的第二集电区在所述基区中。
可选的,所述形成方法还包括:
形成第二掺杂类型的深埋区在所述衬底中,所述掩埋区连接所述深阱区和所述基区,并且所述掩埋区的离子掺杂浓度大于所述深阱区的离子掺杂浓度。
可选的,所述形成方法还包括:
形成第一掺杂类型的基极接触区在所述基区中,所述基极接触区还延伸至所述衬底的顶表面。
可选的,所述基极接触区的离子掺杂浓度大于所述基区的离子掺杂浓度,并且所述基极接触区中位于所述第一集电区和所述第二集电区之间的部分邻接所述第一集电区。
可选的,所述基极接触区具有位于所述延伸区和所述第一集电区之间部分,并且所述基极接触区中位于所述延伸区和所述第一集电区之间的部分邻接所述延伸区;以及,所述基极接触区还具有位于所述延伸区和所述第二集电区之间部分,并且所述基极接触区中位于所述延伸区和所述第二集电区之间的部分邻接所述延伸区。
可选的,所述形成方法还包括:
形成金属硅化物层在所述衬底上,其中在所述第一集电区、所述第二集电区和所述基极接触区上均形成有所述金属硅化物层。
可选的,所述基极接触区具有相对于所述第二集电区更靠近所述第一集电区的部分,位于所述基极接触区上且靠近所述第一集电区的金属硅化物层和位于所述第一集电区上的金属硅化物层相互连接。
可选的,所述形成方法还包括:
形成第二掺杂类型的发射极接触区在所述发射区的所述延伸区中,并且所述发射极接触区的离子掺杂浓度高于所述延伸区的离子掺杂浓度。
可选的,所述形成方法还包括:形成沟槽隔离结构在所述衬底中,以界定出所述电流源的有源区域;
以及,所述基区形成所述有源区域中,并且所述沟槽隔离结构延伸在所述衬底中的深度位置不低于所述基区的深度位置。
在本发明提供的电流源中,其发射区包括深阱区和延伸区,以利用所述发射区围绕基区并隔离所述基区。即,发射区不仅用于构成电流源的双极型晶体管,并且还用于实现基区的隔离。与传统的电流源中利用沟槽隔离结构隔离基区相比,本发明中的电流源可直接利用发射区隔离基区,从而可以屏除沟槽隔离结构的限制,有利于实现电流源器件的尺寸缩减。并且,根据现有的半导体工艺所形成的沟槽隔离结构,即使所形成的沟槽隔离结构的深度低于本发明中的电流源的基区的深度,仍能够满足对电流源的电性隔离,进而在所述沟槽隔离结构的隔离下,可以进一步实现电流源器件和其他半导体逻辑器件的集成设置。
附图说明
图1为现有的一种电流源的结构示意图;
图2a为一种电流源的等效电路图;
图2b为本发明一实施例中的电流源的版图;
图2c为图2b所示的本发明一实施例中的电流源沿着aa’方向的剖面示意图;
图2d为本发明一实施例中的电流源其互连结构的示意图;
图3为本发明一实施例中的电流源的形成方法的流程示意图;
图4a~图4d为本发明一实施例中的电流源的形成方法在其制备过程中的结构示意图。
其中,附图标记如下:
100-衬底;
101-衬底接触区;
110B-基区;
111B-基极接触区;
110E-发射区;
111E-深阱区;
112E-延伸区;
113E-发射极接触区;
110C1-第一集电区;
110C2-第二集电区;
120-掩埋区;
130-沟槽隔离结构;
200-介质层;
210-金属硅化物层;
220-导电插塞;
230-金属层;
240-掩膜层。
具体实施方式
以下结合附图和具体实施例对本发明提出的电流源及其形成方法作进一步详细说明。根据下面说明,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
图2a为一种电流源的等效电路图,图2b为本发明一实施例中的电流源的版图,图2c为图2b所示的本发明一实施例中的电流源沿着aa’方向的剖面示意图。结合图2a~图2c所示,所述电流源包括:
衬底100;
第一掺杂类型的基区(Base)110B,形成在所述衬底100中;
第二掺杂类型的发射区(Emitter)110E,形成在所述衬底100中并环绕所述基区110B,其中所述发射区110E包括一深阱区111E和一延伸区112E,所述深阱区111E位于所述基区110B的下方,所述延伸区112E从所述基区110B的侧面环绕所述基区110B,并且所述延伸区112E的底部连接所述深阱区111E,所述延伸区112E的顶部延伸至所述衬底100的顶表面;以及,
第二掺杂类型的第一集电区(Reference Collector)110C1和至少一个第二掺杂类型的第二集电区(Out Put Collector)110C2,所述第一集电区110C1和所述第二集电区110C2均形成在所述衬底100的所述基区110B中。其中,所述第一集电区110C1和第二集电区110C2还均延伸至衬底100的顶表面。
需要说明的是,所述第一掺杂类型和所述第二掺杂类型为相反的掺杂类型。例如,第一掺杂类型为N型掺杂类型,第二掺杂类型为P型掺杂类型;或者,第一掺杂类型为P型掺杂类型,第二掺杂类型为N型掺杂类型。本实施例中,以第一掺杂类型为P型、第二掺杂类型为N型为例进行解释说明。即,本实施例中,所述基区110B为P型,所述发射区110E为N型,所述第一集电区110C1和第二集电区110C2为N型。
其中,所述第一集电区110C1用于构成电流源的输入端三极管T1,并连接至一电源端口Vcc,用于接收参考电流IREF;以及,第二集电区110C2用于构成电流源的输出端三极管T2,用于根据所述参考电流IREF产生输出电流IO。
应当认识到,所述电流源可以包括一个第二集电区110C2,也可以包括多个第二集电区110C2,例如所述电流源中的第二集电区110C2可以为两个、三个或者四个等。以及,多个所述第二集电区110C2可以以所述第一集电区110C1为中心分散排布在所述第一集电区110C1的外围。本实施例中,以所述电流源具有两个第二集电区110C2为例进行解释说明,以及两个所述第二集电区110C2分别布置在所述第一集电区110C1的两侧。
如图2c所示,由于发射区110E包括深阱区111E和延伸区112E,从而可以由深阱区111E和延伸区112E直接围绕所述基区110B,实现基区110B的隔离。即,所述发射区110E用于构成电流源的双极型晶体管,同时还用于实现基区110B的隔离。具体的,本实施例中,所述衬底100为第一掺杂类型(例如,P型),从而可利用第二掺杂类型的发射区110E实现PN结隔离。
与现有的电流源中采用沟槽隔离结构隔离基区相比,本实施例中,直接利用发射区110E实现基区110B的隔离,从而不会受到沟槽隔离结构的限制,有利于实现电流源中双极型晶体管和半导体CMOS逻辑器件兼容,例如,可适用于与半导体的90nm、65nm、55nm以及40nm等工艺节点的半导体逻辑器件的兼容设置。
具体而言,本实施例中的电流源例如设置有沟槽隔离结构130,所述沟槽隔离结构130形成在所述衬底100中以界定出电流源的有源区域(active area,AA)。即,所述电流源的双极型晶体管形成在所述有源区域中,所述沟槽隔离结构130延伸在所述衬底中的深度位置可以低于所述基区110B的深度位置,或者所述沟槽隔离结构130延伸在所述衬底中的深度位置也可以不低于所述基区110B的深度位置,均可以实现电流源器件能够和其他半导体逻辑器件(例如,COMS逻辑器件)的集成兼容。
继续参考图2b和图2c所示,本实施例中的电流源还包括第一掺杂类型的基极接触区111B,所述基极接触区111B形成在所述衬底100的所述基区110B中,并且所述基极接触区111B的离子掺杂浓度高于所述基区110B的离子掺杂浓度,以用于实现所述基区110B的信号引出。其中,所述基极接触区111B和所述第一集电区110C1均电性连接至同一电源端口Vcc。
图2d为本发明一实施例中的电流源其互连结构的示意图,结合图2b和图2d所示,所述基极接触区111B、所述第一集电区110C1和所述第二集电区110C2均延伸至衬底100的顶表面,并且在所述基极接触区111B的衬底顶表面上、所述第一集电区110C1的衬底顶表面上以及第二集电区110C2的衬底顶表面上还均形成有金属硅化物层210,以通过所述金属硅化物层210实现信号引出。即,所述基极接触区111B和所述第一集电区110C1通过所述金属硅化物层210电性连接至所述电源端口。如此,即可使得所述基区110B、所述第一集电区110C1和所述第二集电区110C2能够在低接触电阻下进行信号引出。
需要说明的是,现有的电流源(例如图1所示的电流源)中,其设置有一栅极结构(Gate),并基于栅诱导漏极泄漏电流(gate-induced drain leakage,GIDL)实现集电区经由基区并最终至发射区之间的电流流通。即,图1所示的电流源中,基区中不设置有信号接触点,而是将基区和集电区之间等效于串联连接,如此将导致电流源的输入电阻较大。
然而,与现有的电流源相比,本实施例中,利用金属硅化物层210直接电性引出所述基区110B和所述第一集电区110C1,从而可以使得第一集电区110C1和基区110B具备较低的接触电阻,有效降低了电流源的输入电阻,有利于提高电流源的器件性能。
可选的方案中,所述基极接触区111B具有相对于所述第二集电区110C2更靠近所述第一集电区110C1的部分,从而有利于实现基极接触区111B和第一集电区110C1连接至同一电源端口。
继续参考图2b和图2c所述,本实施例中,所述基极接触区111B的部分边界与所述第一集电区110C1的部分边界重合,即所述基极接触区111B具有邻接所述第一集电区110C1的部分,从而可使位于所述基极接触区111B上且邻接所述第一集电区的金属硅化物层和位于所述第一集电区110C1上的金属硅化物层能够相互连接。即,所述基极接触区111B和所述第一集电区110C1通过同一金属硅化物层直接连接,并进一步电性连接至电源端口。
进一步的,所述基极接触区111B具有位于所述第一集电区110C1和所述第二集电区110C2之间的部分。更进一步的,所述基极接触区111B中位于所述第一集电区110C1和所述第二集电区110C2之间的部分邻接所述第一集电区110C1。即,所述第一集电区110C1面对所述第二集电区110C2的外周围上邻接有高浓度的基极接触区111B,从而有利于缓解由相邻第一集电区110C1和第二集电区110C2构成的寄生三极管所产生的漏电流现象。
具体而言,所述第一集电区110C1和第二集电区110C2设置在同一基区110B中,因此相邻的第一集电区110C1和第二集电区110C2容易形成寄生三极管(例如,寄生NPN管)。以及,由于所述第一集电区110C1构成电流源的输入端,在所述电流源的工作过程中,发射区110E中的载流子注入至所述基区110B中,并进一步被所述第一集电区110C1收集。此时,由相邻的第一集电区110C1和第二集电区110C2所构成的寄生三极管中,第一集电区110C1相当于所述寄生三极管的发射极。
基于此,本实施例中,由于第一集电区110C1面对第二集电区110C2的侧壁上围绕有高浓度的基极接触区111B,所述基极接触区111B和所述基区110B之间存在浓度梯度(所述基极接触区111B的离子掺杂浓度高于所述基区110B的离子掺杂浓度),如此一来,即可在所述第一集电区110C1的外围上产生一电场。此时,由相邻的第一集电区110C1和第二集电区110C2所构成的寄生三极管中,第一集电区110C1(相当于寄生三极管中的发射极)即能够在电场的作用下,阻挡第一集电区110C1中的载流子迁移,进而可以改善电流源由寄生效应所产生的漏电流现象。
由此可见,本实施例中,所述基极接触区111B不仅用于构成基区110B的信号引出点,以实现基区110B能够直接电性引出,以降低电流源的输入电阻;并且,所述基极接触区111B还用于构成第二掺杂类型的保护环,以缓解第一集电区110C1和相邻第二集电区110C2之间的寄生效应。
此外,本实施例中,所述电流源的发射区110E环绕所述基区110B的侧壁以延伸至衬底的顶表面,从而使得所述第一集电区110C1和/或第二集电区110C2横向靠近所述延伸区112E。例如,本实施例中,所述第一集电区110C1在垂直于aa’方向上,横向靠近所述延伸区112E;以及,第二集电区110C2在沿着aa’方向上,横向靠近所述延伸区112E。因此,所述第一集电区110C1和所述延伸区112E之间以及所述第二集电区110C2和所述延伸区112E之间均会横向形成一寄生三极管(例如,寄生NPN管)。
基于此,可进一步使得所述基极接触区111B具有位于所述第一集电区110C1和所述延伸区112E之间部分。可选的,所述基极接触区111B中位于所述第一集电区110C1和所述延伸区112E之间的部分邻接所述延伸区112E。以及,可使所述基极接触区111B还具有位于所述第二集电区110C2和所述延伸区112E之间部分。可选的,所述基极接触区111B中位于所述第二集电区110C2和所述延伸区112E之间的部分邻接所述延伸区112E。如此,即可以缓解由第一集电区110C1和延伸区112E以及由第二集电区110C2和延伸区112E所产生的寄生效应。
需要说明的是,本实施例中,由于基极接触区111B部分邻接所述延伸区112E,从而可以有效缩减所述电流源的器件尺寸。然而应当认识到,在其他实施例中,也可以使所述基极接触区111B不与所述延伸区112E邻接。
继续参考图2b和图2c所示,所述电流源还包括可选的第二掺杂类型的掩埋区120,所述掩埋区120连接所述深阱区111E和所述基区110B,并且所述掩埋区120的离子掺杂浓度高于所述深阱区111E的离子掺杂浓度。可以理解的是,所述掩埋区120可以构成发射区110E的一部分,在电流源的工作过程中,高浓度的掩埋区120可以为基区110B提供更多的载流子,以提高所述电流源的器件性能。
可选的,所述掩埋区120掩埋在衬底的预定深度位置中,并横向延伸至所述第一集电区110C1和第二集电区110C2的下方。可以理解的是,所述第一集电区110C1和第二集电区110C2的下方均具有所述掩埋区120。
进一步的,所述电流源还包括第二掺杂类型的发射极接触区113E,所述发射极接触区113E形成在所述发射区110E的所述延伸区112E中,并延伸至衬底100的顶表面,以及所述发射极接触区113E的离子掺杂浓度高于所述延伸区112E的离子掺杂浓度,以用于实现发射区110E的信号引出。所述发射区110E例如可通过所述发射极接触区113E电性连接至一接地端口。
同样的,在所述发射极接触区113E的衬底顶表面上也形成有金属硅化物层210,以通过所述金属硅化物层210使发射区110E能够在低接触电阻下实现电性连接。
可选的,在所述衬底100中还形成有第一掺杂类型的衬底接触区101,所述衬底接触区101位于所述延伸区112E远离所述基区110B的一侧,以用于实现衬底100的信号引出。其中,所述衬底接触区101例如也可电性连接至一接地端口。类似的,在所述衬底接触区101的衬底顶表面上也形成有金属硅化物层。
本实施例中,所述发射极接触区113E和所述衬底接触区101均连接至接地端口。基于此,可使所述发射极接触区113E以远离所述基区110B设置在所述延伸区112E的边缘中,以及所述衬底接触区101邻接所述延伸区112E,从而使所述衬底接触区101和所述发射极接触区113E紧邻设置。如图2d所示,位于所述衬底接触区101上的金属硅化物层和位于所述发射极接触区113E上的金属硅化物层可以相互连接,从而可使所述衬底接触区101和所述发射极接触区113E能够同时电性连接至接地端口。当然,在其他实施例中,所述衬底接触区101也可以不与所述发射极接触区113E紧邻设置。
继续参考图2d所示,在所述衬底100上还形成有互连结构,所述互连结构包括介质层200、多个导电插塞220和金属层230。其中,所述介质层200形成在所述衬底100上,并覆盖所述金属硅化物层210;所述导电插塞220贯穿所述介质层200,以和所述金属硅化物层210电性连接;以及,所述导电层230形成在所述介质层200上,以和所述导电插塞220的顶部电性连接。
本实施例中,位于所述衬底接触区101上的金属硅化物层和位于所述发射极接触区113E上的金属硅化物层连接至同一导电插塞220,以及位于所述第一集电区110C1上的金属硅化层和位于所述基极接触区111B上的金属硅化物层连接至同一导电插塞220。如此,即有利于简化电流源的版图结构。
接着参考图2b所示的版图结构,本实施例中,所述发射区110E中的延伸区112E呈环状结构并围绕所述基区110B,以及所述基极接触区111B沿着所述延伸区112E靠近基区110B的侧壁邻接所述延伸区112E,以使所述基极接触区111B环绕形成在所述基区110B中的第一集电区110C1和第二集电区110C2。并且,所述基极接触区111B中位于第一集电区110C1和第二集电区110C2之间部分,连接所述基极接触区111B中邻接所述延伸区的部分。
需要说明的是,本实施例中,所述发射区110E围绕出矩形的基区110B,以及在矩形的基区110B中形成有一矩形的第一集电区110C1和两个矩形的第二集电区110C2,两个第二集电区110C2分别位于第一集电区110C1的两侧。然而,在其他实施例中,所述发射区还可以围绕出其他任意形状的基区,以及第一集电区110C1和第二集电区110C2也可以为其他任意形状,例如为圆形、椭圆形或多边形等。
以及,电流源中的多个第二集电区110C2的面积可以相同也可以不同,具体可根据实际需求调整所述第二集电区110C2的面积。例如,可使第二集电区110C2的面积和第一集电区110C1的面积相等,如此以使所述电流源构成镜像电流源。或者,可使第二集电区110C2的面积和第一集电区110C1的面积呈比例设置,如此以构成比例电流源。本实施例中,两个第二集电区110C2的面积互不相同,以和第一集电区110C1的面积呈不同比例设置。
基于如上所述的电流源,本实施例还提供了一种电流源的形成方法。图3为本发明一实施例中的电流源的形成方法的流程示意图,图4a~图4d为本发明一实施例中的电流源的形成方法在其制备过程中的结构示意图。以下结合附图,对本实施例中形成电流源的各个步骤进行解释说明。
在步骤S100中,具体参考图4a所示,提供一衬底100,所述衬底100例如具有第一掺杂类型。本实施例中,所述衬底100为P型衬底。
可选的方案中,可在所述衬底100中形成有沟槽隔离结构130,以界定出一有源区域AA,后续需形成的电流源的双极型晶体管可均形成在所述有源区域AA中。以及,后续若使所形成的电流源器件和其他半导体逻辑器件集成设置时,则可直接利用所述沟槽隔离结构130实现电性隔离。
其中,所述沟槽隔离结构130可利用传统的半导体工艺形成,以及所形成的沟槽隔离结构130例如延伸在衬底的第一深度位置。
在步骤S200中,继续参考图4a所示,形成第一掺杂类型的基区110B和第二掺杂类型的发射区在所述衬底100中,所述发射区包括一深阱区111E和一延伸区112E,所述深阱区111E位于所述基区110B的下方,所述延伸区112E从所述基区110B的侧面环绕所述基区110B,并且所述延伸区112E的底部连接所述深阱区111E,所述延伸区112E的顶部延伸至所述衬底100的顶表面。
如图4a所示,本实施例中,所述基区110B延伸在衬底的第二深度位置,其中所述第二深度位置不高于沟槽隔离结构的第一深度位置。换言之,所述沟槽隔离结构130的深度不低于所述基区110B的深度,此时利用所述沟槽隔离结构130,仍能够实现后续所形成的电流源器件与其他半导体逻辑器件的兼容设置。
具体的,所述基区110B和所述发射区的形成方法例如包括如下步骤。
步骤一,形成第二掺杂类型的深阱区111E在所述衬底100中,所述深阱区111E位于所述衬底100的预定深度位置中。
步骤二,形成第二掺杂类型的延伸区112E在所述衬底100中,所述延伸区112E从衬底的顶表面上往衬底的内部延伸至所述深阱区111E,以和所述深阱区111E连接。
本实施例中,所述延伸区112E可沿着所述深阱区111E的边缘环绕所述深阱区111E,如此即可由所述深阱区111E和所述延伸区112E在衬底中围绕出一区域。
步骤三,形成第一掺杂类型的基区110B在由所述发射区围绕出的区域中。
需要说明的是,本实施例中,所述衬底100为第一掺杂类型,因此在形成所述深阱区111E和所述延伸区112E之后,则由所述深阱区111E和所述延伸区112E界定出的区域即为第一掺杂类型,此时可将界定出的区域直接构成所述基区110B。当然,也可对界定出的区域执行离子注入工艺,以调整由所述发射区界定出的区域中的离子掺杂浓度,以构成所述基区110B。
可选的方案中,在形成所述发射区之后,还包括形成第二掺杂类型的掩埋区120在所述衬底100中,所述掩埋区120的离子掺杂浓度高于所述深阱区111E的离子掺杂浓度。其中,所述掩埋区120具有与所述深阱区111E的上边界重叠的部分,并且所述掩埋区120还从所述深阱区111E的顶部向上延伸至所述基区110B中,从而使所述掩埋区120连接所述深阱区111E和所述基区110B。
在步骤S300中,具体参考图4b所示,形成第二掺杂类型的第一集电区110C1和至少一个第二掺杂类型的第二集电区110C2在所述基区110B中。本实施例中,以形成两个第二集电区110C为例进行说明。
具体的,所述第一集电区110C1和所述第二集电区110C2可以利用同一离子注入工艺同时形成。以及,所述第一集电区110C1和所述第二集电区110C2均从衬底的顶表面往衬底的内部延伸。
进一步的,在形成所述第一集电区110C1和所述第二集电区110C2时,还包括形成第二掺杂类型的发射极接触区113E,所述发射极接触区113E形成在所述延伸区112E中,并从所述衬底的顶表面往衬底的内部延伸。以及,所述发射极接触区113E的离子掺杂浓度高于所述延伸区112E的离子掺杂浓度,以用于实现所述发射区的电性引出。
此外,在形成所述第一集电区110C1和所述第二集电区110C2之前,或者在形成所述第一集电区110C1和所述第二集电区110C2之后,所述形成方法还包括:
形成第一掺杂类型的基极接触区111B在所述基区110B中,并且所述基极接触区111B的离子掺杂浓度高于所述基区110B的离子掺杂浓度,以实现所述基区110B的信号引出。
具体的,所述基极接触区111B具有相对于所述第二集电区110C2更靠近所述第一集电区110C1的部分,从而有利于实现基极接触区111B和第一集电区110C1能够同时连接至同一电源端口。
本实施例中,所述基极接触区111B具有位于所述第一集电区110C1和所述第二集电区110C2之间的部分,并且所述基极接触区111B中位于所述第一集电区110C1和所述第二集电区110C2之间的部分邻接所述第一集电区110C1。如此一来,还可利用所述基极接触区111B进一步缓解由相邻的第一集电区110C1和第二集电区110C2构成的寄生三极管所产生漏电流现象。
继续参考图4b所示,形成在所述基区110B中的第一集电区110C1和/或第二集电区110C2靠近所述发射区110E中的延伸区112E。基于此,则可使所述基极接触区111B具有位于所述延伸区112E和所述第一集电区110C1之间部分,并使所述基极接触区111B中位于所述延伸区112E和所述第一集电区110C1之间的部分邻接所述延伸区112E;以及,还可使所述基极接触区111B还具有位于所述延伸区112E和所述第二集电区110C2之间部分,并且所述基极接触区111B中位于所述延伸区112E和所述第二集电区110C2之间的部分邻接所述延伸区112E。如此,以进一步缓解由第一集电区110C1和延伸区112E之间以及由第二集电区110C2和延伸区112E之间所产生的横向寄生效应。
可选的方案中,在形成所述基极接触区111B时,还包括:形成第一掺杂类型的衬底接触区101在所述衬底100中,所述衬底接触区101形成在所述延伸区112E远离所述基区110B的一侧,以用于实现衬底100的信号引出。
本实施例中,所述衬底接触区101可电性连接至一接地端口,以及所述发射极接触区113E也可电性连接至接地端口,因此可使所述衬底接触区101和所述发射极接触区113E紧邻设置,以利于将所述衬底接触区101和所述发射极接触区113E电性连接至同一接地端口。
继续参考图3并结合图4c所示,所述电流源的形成方法还包括:步骤S400,形成金属硅化物层210在所述衬底100上,以利用所述金属硅化物层210实现各个接触区的信号引出。即,在所述第一集电区110C1、第二集电区110C2、基极接触区111B、发射极接触区113E和衬底接触区101上均形成有金属硅化物层210。
具体参考图4c所示,所述金属硅化物层210的形成方法例如包括如下步骤。
步骤一,形成一掩膜层240在所述衬底100上,所述掩膜层240中开设有多个开口,以暴露出需要形成金属硅化物层的区域。
本实施例中,所述掩膜层240中的多个开口分别暴露出所述第一集电区110C1、第二集电区110C2、基极接触区111B、发射极接触区113E和衬底接触区101。其中,第一集电区110C1和基极接触区111B紧邻设置,并使第一集电区110C1和基极接触区111B暴露于同一开口中;以及,发射极接触区113E和衬底接触区101紧邻设置,并使发射极接触区113E和衬底接触区101暴露于同一开口中。
步骤二,以所述掩膜层240为掩膜,形成金属硅化物层210在暴露于所述开口中的衬底上。其中,与所述第一集电区110C1连接的金属硅化物层和与所述基极接触区111B连接的金属硅化物层相互连接,与所述发射极接触区113E连接的金属硅化物层和与所述衬底接触区101连接的金属硅化物层相互连接。
进一步的,在形成所述金属硅化物层210之后,还包括:步骤S500,具体参考图4d所示,形成互连结构在所述衬底100上,以利用所述互连结构实现电流源中的各个电极的信号引出。
具体的,所述互连结构包括一介质层200、形成在所述介质层200中的多个导电插塞220以及形成在所述介质层200上的多个金属层230,所述导电插塞220贯穿所述介质层200并与所述金属硅化物层210电性连接,所述金属层230与所述导电插塞220的顶部电性连接。
综上所述,本发明提供的电流源包括基区、发射区、第一集电区和第二集电区,其中发射区具有深阱区和延伸区,以利用发射区围绕基区。可见,所述发射区不仅用于构成电流源的双极型晶体管,并且还直接利用发射区隔离基区。由于本发明中的电流源可以屏除沟槽隔离结构的限制,从而有利于实现器件尺寸的缩减。并且,基于本发明中的电流源,即使是利用传统工艺形成的深度较低的沟槽隔离结构,仍能够实现电流源器件和半导体逻辑器件之间的电性隔离,进而使电流源器件能够和半导体逻辑器件兼容。
进一步的,在所述基区中还形成有基极接触区,如此即可直接电性引出所述基区和第一集电区。与现有技术中利用栅诱导漏极泄漏电流实现基区和第一集电区的串联连接相比,本发明中直接电性连接所述基区和所述第一集电区,有利于降低电流源的输入电阻,从而可以提高电流源的器件性能。
更进一步的,可使基极接触区具有邻接第一集电区的部分,以缓解由第一集电区和相邻的第二集电区所产生的寄生效应。以及,还可使基极接触区还具有邻接延伸区的部分,如此,即可有效改善由延伸区和第一集电区之间的寄生效应,以及缓解由延伸区和第二集电区之间的寄生效应。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (21)
1.一种电流源,其特征在于,包括:
衬底;
第一掺杂类型的基区,形成在所述衬底中;
第二掺杂类型的发射区,形成在所述衬底中并环绕所述基区,其中所述发射区包括一深阱区和一延伸区,所述深阱区位于所述基区的下方,所述延伸区从所述基区的侧面环绕所述基区,并且所述延伸区的底部连接所述深阱区,所述延伸区的顶部延伸至所述衬底的顶表面;
第二掺杂类型的第一集电区,形成在所述衬底的所述基区中,所述第一集电区用于构成电流源的输入端三极管;以及,
至少一个第二掺杂类型的第二集电区,形成在所述衬底的所述基区中,所述第二集电区用于构成电流源的输出端三极管,所述第二集电区和所述第一集电区均被所述发射区环绕在内。
2.如权利要求1所述的电流源,其特征在于,还包括:
第一掺杂类型的基极接触区,形成在所述衬底的所述基区中,并且所述基极接触区和所述第一集电区均电性均连接至同一电源端口。
3.如权利要求2所述的电流源,其特征在于,所述基极接触区和所述第一集电区均延伸至衬底的顶表面,并且在所述基极接触区的衬底顶表面上以及所述第一集电区的衬底顶表面上均形成有金属硅化物层,以通过所述金属硅化物层电性连接至所述电源端口。
4.权利要求2所述的电流源,其特征在于,所述基极接触区的离子掺杂浓度大于所述基区的离子掺杂浓度,并且所述基极接触区具有位于所述第一集电区和所述第二集电区之间的部分。
5.如权利要求4所述的电流源,其特征在于,所述基极接触区中位于所述第一集电区和所述第二集电区之间的部分邻接所述第一集电区。
6.如权利要求2所述的电流源,其特征在于,所述基极接触区具有位于所述延伸区和所述第一集电区之间部分。
7.如权利要求6所述的电流源,其特征在于,所述基极接触区中位于所述延伸区和所述第一集电区之间的部分邻接所述延伸区。
8.如权利要求2所述的电流源,其特征在于,所述基极接触区具有位于所述延伸区和所述第二集电区之间部分。
9.如权利要求8所述的电流源,其特征在于,所述基极接触区中位于所述延伸区和所述第二集电区之间的部分邻接所述延伸区。
10.如权利要求1所述的电流源,其特征在于,所述电流源还包括:
第二掺杂类型的掩埋区,所述掩埋区连接所述深阱区和所述基区,并且所述掩埋区的离子掺杂浓度大于所述深阱区的离子掺杂浓度。
11.如权利要求1所述的电流源,其特征在于,所述电流源还包括:
第二掺杂类型的发射极接触区,形成在所述延伸区中,并且所述发射极接触区的离子掺杂浓度高于所述延伸区的离子掺杂浓度。
12.如权利要求1~11任一项所述的电流源,其特征在于,所述电流源还包括:
沟槽隔离结构,形成在所述衬底中以界定出所述电流源的有源区域,所述基区形成所述有源区域中,并且所述沟槽隔离结构延伸在所述衬底中的深度位置不低于所述基区的深度位置。
13.一种电流源的形成方法,其特征在于,包括:
提供一衬底;
形成第一掺杂类型的基区和第二掺杂类型的发射区在所述衬底中,所述发射区包括一深阱区和一延伸区,所述深阱区位于所述基区的下方,所述延伸区从所述基区的侧面环绕所述基区,并且所述延伸区的底部连接所述深阱区,所述延伸区的顶部延伸至所述衬底的顶表面;以及,
形成第二掺杂类型的第一集电区和至少一个第二掺杂类型的第二集电区在所述基区中,所述第一集电区用于构成电流源的输入端三极管,所述第二集电区用于构成电流源的输出端三极管,所述第二集电区和所述第一集电区均被所述发射区环绕在内。
14.如权利要求13所述的电流源的形成方法,其特征在于,所述形成方法还包括:
形成第二掺杂类型的深埋区在所述衬底中,所述掩埋区连接所述深阱区和所述基区,并且所述掩埋区的离子掺杂浓度大于所述深阱区的离子掺杂浓度。
15.如权利要求13所述的电流源的形成方法,其特征在于,所述形成方法还包括:
形成第一掺杂类型的基极接触区在所述基区中,所述基极接触区还延伸至所述衬底的顶表面。
16.如权利要求15所述的电流源的形成方法,其特征在于,所述基极接触区的离子掺杂浓度大于所述基区的离子掺杂浓度,并且所述基极接触区中具有位于所述第一集电区和所述第二集电区之间的部分,所述基极接触区中位于所述第一集电区和所述第二集电区之间的部分邻接所述第一集电区。
17.如权利要求15所述的电流源的形成方法,其特征在于,所述基极接触区具有位于所述延伸区和所述第一集电区之间部分;以及,所述基极接触区还具有位于所述延伸区和所述第二集电区之间部分,所述基极接触区中位于所述延伸区和所述第一集电区之间的部分邻接所述延伸区;以及,所述基极接触区中位于所述延伸区和所述第二集电区之间的部分邻接所述延伸区。
18.如权利要求15所述的电流源的形成方法,其特征在于,所述形成方法还包括:
形成金属硅化物层在所述衬底上,其中在所述第一集电区、所述第二集电区和所述基极接触区上均形成有所述金属硅化物层。
19.如权利要求18所述的电流源的形成方法,其特征在于,所述基极接触区具有相对于所述第二集电区更靠近所述第一集电区的部分,位于所述基极接触区上且靠近所述第一集电区的金属硅化物层和位于所述第一集电区上的金属硅化物层相互连接。
20.如权利要求13所述的电流源的形成方法,其特征在于,在形成所述发射区之后,还包括:
形成第二掺杂类型的发射极接触区在所述发射区的所述延伸区中,并且所述发射极接触区的离子掺杂浓度高于所述延伸区的离子掺杂浓度。
21.如权利要求13~20任一项所述的电流源的形成方法,其特征在于,所述形成方法还包括:形成沟槽隔离结构在所述衬底中,以界定出所述电流源的有源区域;
以及,所述基区形成所述有源区域中,并且所述沟槽隔离结构延伸在所述衬底中的深度位置不低于所述基区的深度位置。
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