JP2018006414A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2018006414A JP2018006414A JP2016127930A JP2016127930A JP2018006414A JP 2018006414 A JP2018006414 A JP 2018006414A JP 2016127930 A JP2016127930 A JP 2016127930A JP 2016127930 A JP2016127930 A JP 2016127930A JP 2018006414 A JP2018006414 A JP 2018006414A
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Abstract
【解決手段】支持基板である半導体基板SBと半導体基板SB上の絶縁層BXと絶縁層BX上の半導体層SMとを有するSOI基板1に、半導体層SMおよび絶縁層BXを貫通して底部が半導体基板SBに達する素子分離領域STが形成され、半導体層SM上にゲート絶縁膜GFを介してゲート電極GEが形成されている。半導体層SMに隣接する位置において素子分離領域STにディボットDTが形成され、ディボットDT内に埋込絶縁膜UZが形成されている。ゲート電極GEは、半導体層SM上にゲート絶縁膜GFを介して形成された部分と、埋込絶縁膜UZ上に位置する部分と、素子分離領域ST上に位置する部分とを有している。
【選択図】図25
Description
<半導体装置の製造工程について>
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1〜図24は、本発明の一実施の形態である半導体装置の製造工程中の要部断面図または要部平面図である。なお、図1〜図24のうち、図11および図15は要部平面図であり、図1〜図10、図12〜図14および図16〜図24は要部断面図である。なお、図1〜図10、図12〜図14および図16〜図24のそれぞれにおいて、左側にA−A断面の断面図を示し、右側にB−B断面の断面図を示してある。ここで、図11および図15の平面図に示されるA−A線に相当する位置での断面図が、A−A断面図に対応し、図11および図15の平面図に示されるB−B線に相当する位置での断面図が、B−B断面図に対応している。
上述のようにして製造された本実施の半導体装置の構造について説明する。
本発明者が検討した検討例について、図26〜図30を参照して説明する。図26〜図30は、検討例の半導体装置の製造工程中の要部断面図である。
本実施の形態の主要な特徴のうちの一つは、埋込絶縁膜UZを形成していることである。
本実施の形態2の半導体装置の製造工程を図面を参照して説明する。図31〜図35は、本実施の形態2の半導体装置の製造工程中の要部断面図である。上記実施の形態1と同様に、本実施の形態2の図31〜図35のそれぞれにおいても、左側にA−A断面の断面図を示し、右側にB−B断面の断面図を示してある。ここで、上記図11および図15の平面図に示されるA−A線に相当する位置での断面図が、A−A断面図に対応し、上記図11および図15の平面図に示されるB−B線に相当する位置での断面図が、B−B断面図に対応している。
BX 絶縁層
CP,CP101 キャップ絶縁膜
CPZ,CPZ101 絶縁膜
DT ディボット
EP,EP101 半導体層
EX n−型半導体領域
EZ 残存部
GE,GE101 ゲート電極
GF,GF101 ゲート絶縁膜
GF101a 絶縁膜
GP 半導体領域
IL1,IL2 絶縁膜
LT,LT101 積層体
M1 配線
P1 イオン注入
PG プラグ
PS,PS101 シリコン膜
PR1 フォトレジストパターン
SB 半導体基板
SD n+型半導体領域
SL 金属シリサイド層
SM 半導体層
ST 素子分離領域
SW1,SW2,SW101 サイドウォールスペーサ
SZ1,SZ2 絶縁膜
TR 溝
UZ 埋込絶縁膜
ZM1,ZM2,ZM3,ZM4 絶縁膜
Claims (20)
- MISFETを備える半導体装置であって、
支持基板、前記支持基板上の絶縁層、および前記絶縁層上の半導体層を有する基板と、
前記基板に形成され、前記半導体層および前記絶縁層を貫通して底部が前記支持基板に達する素子分離領域と、
前記半導体層上にゲート絶縁膜を介して形成された、前記MISFET用のゲート電極と、
を有し、
前記半導体層に隣接する位置において前記素子分離領域に窪み部が形成され、前記窪み部内に埋込絶縁膜が形成されており、
前記ゲート電極は、前記半導体層上に前記ゲート絶縁膜を介して形成された部分と、前記埋込絶縁膜上に位置する部分と、前記素子分離領域上に位置する部分とを有している、半導体装置。 - 請求項1記載の半導体装置において、
前記埋込絶縁膜の少なくとも一部は、前記半導体層の下に位置している、半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極の側壁上に形成された側壁絶縁膜と、
前記半導体層上に形成された、前記MISFETのソース・ドレイン用のエピタキシャル半導体層と、
を更に有する、半導体装置。 - 請求項1記載の半導体装置において、
前記埋込絶縁膜の上面の高さ位置は、前記半導体層の上面の高さ位置と同じか、または、前記半導体層の下面の高さ位置と同じか、あるいは、前記半導体層の上面の高さ位置よりも低くかつ前記半導体層の下面の高さ位置よりも高い、半導体装置。 - 請求項1記載の半導体装置において、
平面視において、前記埋込絶縁膜は前記半導体層の周囲を囲んでいる、半導体装置。 - (a)半導体基板と、前記半導体基板上の絶縁層と、前記絶縁層上の半導体層と、前記半導体層上の第1絶縁膜と、前記第1絶縁膜、前記半導体層および前記絶縁層を貫通して前記半導体基板に達する溝と、前記溝内に埋め込まれた素子分離領域と、を有する基板を準備する工程、
(b)前記(a)工程後、前記第1絶縁膜をエッチングにより除去して前記半導体層を露出させる工程、
(c)前記(b)工程後、前記半導体層の表面にゲート絶縁膜を形成する工程、
(d)前記(c)工程後、前記半導体層上に前記ゲート絶縁膜を介してゲート電極を形成する工程、
を有し、
前記半導体層に隣接する位置において前記素子分離領域に窪み部が形成され、前記窪み部内に埋込絶縁膜が形成された状態で、前記(c)工程が行われ、
前記(b)工程後で、前記(c)工程前に、
(c1)前記窪み部内を含む前記素子分離領域上および前記半導体層上に、前記埋込絶縁膜形成用の第2絶縁膜を形成する工程、
(c2)前記窪み部の外部の前記第2絶縁膜を除去し、前記窪み部内に前記第2絶縁膜を残して前記埋込絶縁膜を形成する工程、
を更に有する、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記窪み部は、前記(b)工程で、または、前記(b)工程後で前記(c1)工程前に、形成される、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記埋込絶縁膜の少なくとも一部は、前記半導体層の下に位置している、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(c2)工程では、前記第2絶縁膜をエッチバックすることにより、前記窪み部の外部の前記第2絶縁膜を除去し、前記窪み部内に前記第2絶縁膜を残して前記埋込絶縁膜を形成する、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(c2)工程で形成された前記埋込絶縁膜の上面の高さ位置は、前記半導体層の上面の高さ位置と同じか、または、前記半導体層の下面の高さ位置と同じか、あるいは、前記半導体層の上面の高さ位置よりも低くかつ前記半導体層の下面の高さ位置よりも高い、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(c2)工程では、前記第2絶縁膜を研磨することにより、前記窪み部の外部の前記第2絶縁膜を除去し、前記窪み部内に前記第2絶縁膜を残して前記埋込絶縁膜を形成する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(c2)工程で形成された前記埋込絶縁膜の上面の高さ位置は、前記半導体層の上面の高さ位置と同じである、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(d)工程は、
(d1)前記半導体層上、前記埋込絶縁膜上および前記素子分離領域上に、前記ゲート電極形成用の導電膜を形成する工程、
(d2)前記導電膜をパターニングして前記ゲート電極を形成する工程、
を有する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記ゲート電極は、前記半導体層上に前記ゲート絶縁膜を介して形成された部分と、前記埋込絶縁膜上に位置する部分と、前記素子分離領域上に位置する部分とを有している、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
(e)前記(d)工程後、前記ゲート電極の側壁上に側壁絶縁膜を形成する工程、
(f)前記(e)工程後、前記ゲート電極および前記側壁絶縁膜で覆われずに露出する前記半導体層上に、エピタキシャル半導体層をエピタキシャル成長させる工程、
を更に有する、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記絶縁層と前記第1絶縁膜と前記素子分離領域とは、酸化シリコンからなる、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記埋込絶縁膜は、窒化シリコンまたは酸化シリコンからなる、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(a)工程後で、前記(b)工程前に、
(b1)前記半導体基板に不純物をイオン注入して第1半導体領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項18記載の半導体装置の製造方法において、
前記(b1)工程では、平面視において前記半導体層に隣接する領域の前記素子分離領域にも、前記不純物が注入される、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(a)工程は、
(a1)前記半導体基板と、前記半導体基板上の前記絶縁層と、前記絶縁層上の前記半導体層と、前記半導体層上の前記第1絶縁膜と、前記第1絶縁膜上の第3絶縁膜とを有する前記基板を準備する工程、
(a2)前記(a1)工程後、前記第3絶縁膜、前記第1絶縁膜、前記半導体層および前記絶縁層を貫通して前記半導体基板に達する前記溝を形成する工程、
(a3)前記(a2)工程後、前記第3絶縁膜上に、前記溝内を埋めるように、第4絶縁膜を形成する工程、
(a4)前記(a3)工程後、前記溝の外部の前記第4絶縁膜を除去し、前記溝内に、前記第4絶縁膜からなる前記素子分離領域を形成する工程、
(a5)前記(a4)工程後、前記第3絶縁膜をエッチングにより除去する工程、
を有し、
前記絶縁層と前記第1絶縁膜と前記第4絶縁膜は、酸化シリコンからなり、
前記第3絶縁膜は、窒化シリコンからなる、半導体装置の製造方法。
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