US20150195912A1 - Substrates With Ultra Fine Pitch Flip Chip Bumps - Google Patents

Substrates With Ultra Fine Pitch Flip Chip Bumps Download PDF

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Publication number
US20150195912A1
US20150195912A1 US14/150,683 US201414150683A US2015195912A1 US 20150195912 A1 US20150195912 A1 US 20150195912A1 US 201414150683 A US201414150683 A US 201414150683A US 2015195912 A1 US2015195912 A1 US 2015195912A1
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United States
Prior art keywords
copper
multilayer composite
solderable
dielectric
electronic structure
Prior art date
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Abandoned
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US14/150,683
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English (en)
Inventor
Dror Hurwitz
Alex Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
Original Assignee
Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
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Application filed by Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd filed Critical Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
Priority to US14/150,683 priority Critical patent/US20150195912A1/en
Priority to JP2014049097A priority patent/JP6489460B2/ja
Assigned to ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD. reassignment ZHUHAI ADVANCED CHIP CARRIERS & ELECTRONIC SUBSTRATE SOLUTIONS TECHNOLOGIES CO. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, ALEX, HURWITZ, DROR
Priority to CN201410336766.7A priority patent/CN104134643B/zh
Priority to TW103128714A priority patent/TWI727918B/zh
Priority to KR1020140134963A priority patent/KR101659379B1/ko
Publication of US20150195912A1 publication Critical patent/US20150195912A1/en
Priority to KR1020160053768A priority patent/KR101832717B1/ko
Priority to US15/622,733 priority patent/US10779417B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention is directed to terminating interconnect structures and to coupling between chips and substrates.
  • one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate through to the latest metal layer for subsequent filling with a metal, usually copper, that is deposited therein by a plating technique.
  • This approach to creating vias is sometimes referred to as ‘drill & fill’, and the vias created thereby may be referred to as ‘drilled & filled vias’.
  • the filling process of the drilled via holes is usually achieved by copper electroplating. Electroplating into a drilled hole may result in dimpling, where a small crater appears at the end of the via. Alternatively, overfill may result, where a via channel is filled with more copper than it can hold, and a domed upper surface that protrudes over the surrounding material is created. Both dimpling and overfill tend to create difficulties when subsequently stacking vias one on end of the other, as required when fabricating high-density substrates and interposers. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in proximity to smaller vias within the same interconnecting layer of the interposer or IC substrate design.
  • Laser drilled vias in composite dielectric materials are practically limited to a minimum diameter of 60 ⁇ 10 ⁇ 6 m, and even so suffer from significant tapering shape as well as rough side walls due to the nature of the composite material drilled, in consequence of the ablation process involved.
  • An alternative solution that overcomes many of the disadvantages of the drill & fill approach, is to fabricate vias by depositing copper or other metal into a pattern created in a photo-resist, using a technology otherwise known as ‘pattern plating’.
  • a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern, and selectively removed to make trenches that expose the seed layer. Via posts are created by depositing Copper into the photo-resist trenches. The remaining photo-resist is then removed, the seed layer is etched away, and a dielectric material that is typically a polymer impregnated glass fiber mat, is laminated thereover and therearound to encase the via posts. Various techniques and processes can then be used to planarize the dielectric material, removing part of it to expose the ends of the via posts to allow conductive connection to ground thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
  • panel plating In an alternative but closely linked technology, known hereinafter as ‘panel plating’, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on end of the substrate, and a pattern is developed therein. The pattern of developed photo-resist is stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias.
  • a dielectric material such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. After planarizing, subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
  • via posts typically known as ‘via posts’ and feature layers from copper.
  • the substrate may be etched away leaving free standing, coreless laminar structures. Further layers may be deposited on the side previously adhered to the sacrificial substrate, thereby enabling a two sided build up, which minimizes warping and aids the attaining of planarity.
  • One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or via post features having various geometrical shapes and foams in a dielectric matrix.
  • the metal may be copper and the dielectric may be a fiber reinforced polymer, typically a polymer with a high glass transition temperature (T g ) is used, such as polyimide, for example.
  • T g glass transition temperature
  • These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers and the via may have non circular shapes. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd.
  • U.S. Pat. No. 7,682,972 to Hurwitz et al. titled “Advanced multilayer coreless support structures and method for their fabrication” describes a method of fabricating a free standing membrane including a via array in a dielectric, for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array.
  • An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias.
  • U.S. Pat. No. 7,669,320 to Hurwitz et al. titled “Coreless cavity substrates for chip packaging and their fabrication” describes a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
  • This publication is incorporated herein by reference in its entirety.
  • U.S. Pat. No. 7,635,641 to Hurwitz et al. titled “integrated circuit support structures and their fabrication” describes a method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist ; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first
  • Substrates enable chips to interface with other components. Chips have to be bonded to substrates in a manner that provides reliable electronic connections to enable electronic communication between chips and substrates.
  • solder bumps solder on Pad
  • copper bumps having solder or lead free solder on their tips
  • SoP solder on Pad
  • bumps are generally applied to the substrate terminating pads by stencil printing followed by reflow, or by electroplating processes followed by reflow.
  • Such bumps are usually “coined” by using heat and pressure to generate a top flat surface that can assist with the placement of the bumps from the die side.
  • the solder material of the SoP bumps helps to generate a reliable mechanical and electronic contact with the Chip bump. Without the SoP, the solder material of the chip bumps may not be sufficient or may not be able to completely flow and wet the entire surface of the substrate's terminating pad thereby creating a reliability hazard or even a disconnect between the chip and the substrate. This is an especially a valid concern since most of the substrates have a solder mask external protective layer that by nature extends above the terminating substrate pads thereby making these pads difficult to access without the SoP bumps.
  • SoP bumps must be aligned as much possible to those of the SoP bumps.
  • chips With ongoing developments in chip technology, chips become ever denser, and connection bumps will have to become ever smaller and more densely packed as ever higher concentrations of contacts are required. Consequently, the application of SoP bumps on the substrate becomes ever more challenging.
  • the application of SoP is, by nature, a lower yield process than earlier substrate manufacturing steps, and it is one of the final processing steps in the substrate fabrication, thereby increasing scrap, rework, test and cost rates. Additionally, the more fine the pitch of subsequent generations of SoP bumps, the greater will be the likelihood of failure by shorting between adjacent bumps after reflow and during chip assembly, thereby further reducing yields and increasing the total package cost.
  • soldering is also tricky, in that too little solder may result in some connections being broken. However, too much solder risks shorting between nearby connections.
  • Electroplating of solder bumps is known. For example, see U.S. Pat. No. 5,162,257 and U.S. Pat. No. 5,293,006 to Yung and U.S. Pat. No. 6,117,299 to Rinne.
  • a particular problem of fabricating solder bumps on substrates is aligning them correctly with underlying copper vias, as required to provide good electronic and mechanical coupling.
  • Embodiments of the present invention address these issues.
  • a first aspect of the invention is directed to providing a multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one micro bump wherein the at least one micro bump comprises a via pillar capped with a solderable material.
  • the at least one outer layer of terminations comprises a two dimensional array of microbumps.
  • the thickness of the micro bump is between 15 micron and 50 micron.
  • the solderable material is selected from the group consisting of lead, tin, lead-tin alloys, tin-silver alloys, tin silver copper alloys, tin copper alloys and tin copper nickel alloys.
  • solderable material is tin based.
  • the solderable material is lead free.
  • the diameter of the at least one micro bump is in a range compatible with chip bumps.
  • the diameter of the at least one micro bump is in a range of 60 to 110 microns.
  • the diameter of the at least one micro bump is a minimum of 25 micron.
  • the separation of adjacent micro bumps is a minimum of 15 micron.
  • the pitch of the micro bumps is 40 microns.
  • the outer dielectric has a smoothness of less than 100 nm.
  • the outer dielectric has a smoothness of less than 50 nm.
  • the outer dielectric is selected from the group consisting of NX04H (Sekisui), HBI-800TR67680 (Taiyo) and GX-13 (Afinomoto).
  • a second aspect is directed to a method of terminating a side of a multilayer composite structure having an outer layer of via posts embedded in a dielectric, comprising the steps of:
  • the dielectric outer layer is selected from the group consisting of a film dielectric and a dry film solder mask.
  • step (xv) of applying a finishing treatment to the solderable cap comprises coining by applying pressure to the solder cap along axis of the via post resulting in a flat coined solderable cap.
  • step (xv) of applying a finishing treatment to the solderable cap comprises coining by applying pressure along axis of the via post together with heat to cause reflow under pressure, resulting in a flat coined solderable cap.
  • step (xv) of applying a finishing treatment to the solderable cap comprises applying heat to cause reflow without applying pressure such that the solderable cap assumes a dome shape to surface pressure.
  • the method further comprises step (xii) of planarizing the dielectric outer layer.
  • the planarizing comprises Chemical Mechanical Polishing.
  • the step of plasma etching comprises exposing to ion bombardment in a low pressure atmosphere comprising ionizing at least one of the gases selected from the group consisting of oxygen, tetrafluoride carbon and fluorine.
  • the method further comprises applying terminations on other side of the substrate.
  • applying terminations comprises:
  • a third aspect is directed to a method of applying solderable bumps to ends of via posts comprising electroplating the via posts into a patterned photoresist;
  • the method further comprises applying a finishing treatment to the solderable caps.
  • the compacting comprises at least one of (i) applying pressure along axis of the via posts to coin the solderable caps and (ii) applying heat to cause reflow of the solderable caps.
  • FIG. 1 is a flowchart illustrating the steps of a process for manufacturing very fine pitch ball grid array terminations on a multilayer composite electronic structure for connecting an IC thereto, using flip chip technology;
  • FIG. 1( i ) is a schematic illustration of a multilayer composite electronic structure
  • FIG. 1( ii ) is a schematic illustration of the multilayer composite electronic structure of FIG. 1( i ) having a first side thinned to expose the ends of embedded pillars;
  • FIG. 1( iii ) is a schematic illustration of the multilayer composite electronic structure of FIG. 1( ii ) with a copper seed layer sputtered onto the thinned surface;
  • FIG. 1( iv ) is a schematic illustration of the multilayer composite electronic structure of FIG. 1( ii ) after application, exposure and developing of a photoresist to provide a pattern of pads;
  • FIG. 1( v ) is a schematic illustration of the multilayer composite electronic structure of FIG. 1( iv ) after plating copper into the photoresist;
  • FIG. 1( vi ) is a schematic illustration of the multilayer composite electronic structure with upstanding copper pads after stripping away the photoresist;
  • FIG. 1( vii ) is a schematic illustration of the multilayer composite electronic structure after application, exposure and developing of a photoresist to provide a pattern of termination pegs;
  • FIG. 1( viii ) is a schematic illustration of the multilayer composite electronic structure after plating copper into the patterned photoresist
  • FIG. 1( ix ) is a schematic illustration of the multilayer composite electronic structure after plating a solderable metal or alloy over the copper into the patterned photoresist;
  • FIG. 1( x ) is a schematic illustration of the multilayer composite electronic structure with an array of upstanding copper and solder bumps after stripping away the photoresist;
  • FIG. 1( xi ) is a schematic illustration of the multilayer composite electronic structure with an array of upstanding copper and solder bumps after etching away the copper seed layer;
  • FIG. 1( xii ) is a schematic illustration of the multilayer composite electronic structure with a film dielectric or dry film solder mask laminated over the solder bumps array;
  • FIG. 1( xiii ) is a schematic illustration of the multilayer composite electronic structure after an optional stage of planarizing the film dielectric or dry film solder mask laminated over the solder bumps array, typically using chemical mechanical polishing (CMP);
  • CMP chemical mechanical polishing
  • FIG. 1( xiv ) a shows the other side of the multilayer composite electronic structure ground down to expose the ends of the copper vias
  • FIG. 1( xiv ) b shows the other side of the multilayer composite electronic structure with a copper seed layer sputtered thereon;
  • FIG. 1( xiv ) c shows the other side of the multilayer composite electronic structure with a pattern of photoresist after application, exposure and development;
  • FIG. 1( xiv ) d shows the other side of the multilayer composite electronic structure with a copper layer electroplated into the pattern of photoresist
  • FIG. 1( xiv ) e shows the other side of the multilayer composite electronic structure after stripping away the photoresist
  • FIG. 1( xiv ) f shows the other side of the multilayer composite electronic structure after etching away the seed layer
  • FIG. 1( xiv ) g shows the other side of the multilayer composite electronic structure after depositing a patterned solder mask
  • FIG. 1( xv ) shows the first side after thinning the dielectric film to expose the solderable cap over the copper via post;
  • FIG. 1( xvi ) a shows the first side after densifying under pressure
  • FIG. 1( xvi ) b shows the first side after densifying by reflow
  • FIG. 2 is a flowchart illustrating the process for terminating the other side of the substrate with a ball grid array
  • FIG. 3 is a schematic illustration of an in-line plasma etching station
  • FIG. 4 a is a scanning electron micro photograph (SEM micrograph) showing copper pads separated with dielectric on the surface of a substrate and showing upstanding copper via posts thereupon from above, i.e. from an angle of 0°;
  • FIG. 4 b is a scanning electron micrograph showing copper pads separated with dielectric on the surface of the substrate and having upstanding copper via posts thereupon from above and from an angle of 45°, at a magnifications such that the scale bar is 100 microns;
  • FIG. 4 c is a scanning electron micrograph showing copper pads separated with dielectric on the surface of the substrate and having upstanding copper via posts thereupon from above and from an angle of 45°, at a magnifications such that the scale bar is 20 microns, and the copper via post and tin layer electroplated thereover are both clearly visible;
  • FIG. 4 d is a scanning electron micrograph at the magnification and tilt of FIG. 4 c , showing the tin layer 410 as a dome, after reflow;
  • FIG. 4 e is a scanning electron micrograph at very high magnification wherein the scale bar is 10 microns.
  • An upstanding copper via 405 with a tin cap 407 electroplated thereover using the same patterned photoresist to achieve perfect alignment is shown;
  • FIG. 4 f is a scanning electron micrograph at very high magnification wherein the scale bar is 10 microns.
  • FIG. 4 g is an intermediate magnification scanning electron micrograph of solderable caps that have been subjected to pressure in the direction of the axis of the via posts;
  • FIG. 4 h is a higher magnification scanning electron micrograph of a solderable cap that that has been pressed in the direction of the axis of the via posts;
  • FIG. 4 i is an intermediate magnification scanning electron micrograph of solderable caps that have been subjected to pressure in the direction of the axis of the via posts;
  • FIG. 4 j is a higher magnification scanning electron micrograph of a solderable cap that that has been subjected to pressure in the direction of the axis of the via posts by inserting into a press, and heated to cause reflow.
  • support structures consisting of metal vias in a dielectric matrix, particularly, copper via posts in a polymer matrix, such as polyimide, epoxy or BT (Bismaleimide/Triazine) or their blends, reinforced with glass fibers are considered.
  • vias fabricated by electroplating using photoresists may be narrower than vias created by drill & fill.
  • the narrowest drill & fill vias are about 60 microns.
  • By electroplating using photoresists a resolution of under 50 microns, or even as little as 30 microns is achievable.
  • Coupling ICs to such substrates is challenging.
  • One approach for flip chip coupling is to provide solder on pads (SoP) terminations, where solder bumps are applied to the support structure to terminate copper vias. This is difficult to achieve because of the fine pitch and small scale.
  • Embodiments of the present invention address this issue by providing solder bumps at the end of the copper vias of the support structure.
  • One embodiment consists of Cu pillars with a tin tip.
  • the multilayer support structures 100 includes functional layers 102 , 104 , 106 of components or features 108 separated by layers of dielectric 110 , 112 , 114 , 116 , which insulate the individual layers. Vias 118 through the dielectric layer provide electrical connection between features 108 in the adjacent functional or feature layers 102 , 104 , 106 .
  • the feature layers 102 , 104 , 106 include features 108 generally laid out within the layer, in the X-Y plane, and vias 118 that conduct current across the dielectric layers 110 , 112 , 114 , 116 .
  • Vias 118 are generally designed to have minimal inductance and are sufficiently separated to have minimum capacitances therebetween.
  • the vias could be fabricated by drill & fill, but to provide greater flexibility in fabrication, higher precision and more efficient processing by enabling large numbers of vias to be fabricated simultaneously, preferably the vias are fabricated by electroplating using the technology described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 to Hurwitz et al.
  • the via post technology allows different diameter vias, non circular vias, faraday cages, embedded passive components and other features.
  • FIG. 1( i ) is a schematic illustration for purposes of explanation. Real substrates may have more or less feature layers and more or less vias. Typically, substrates 100 comprise very large numbers of vias.
  • the relative dimensions of vias, feature layers and dielectric, and, in subsequent schematics, of additional elements, are illustrative only, and are not to scale.
  • step (ii) The side of the multilayer composite electronic structure 100 to which a chip is to be coupled by flip chip bonding is first thinned—step (ii) to expose the ends of the copper vias 110 , see FIG. 1( ii ). Chemical, mechanical, or preferably, Chemical Mechanical Polishing CMP may be used. Next, a seed layer of copper 120 is sputtered over the thinned surface—step (iii). The resulting structure is schematic illustrated in FIG. 1( iii ).
  • a layer of photoresist 122 is applied, exposed and developed to provide a pattern of pads—step (iv).
  • copper pads 124 are then plated into the photoresist—step (v), the copper seed layer 120 serving as an anode.
  • step (vi) the photoresist 122 FIG. 1( vi ) is stripped away—step (vi), exposing the upstanding copper pads 124 and the seed layer 120 therebetween.
  • a second layer of photoresist 126 is applied, exposed and developed to provide a pattern of termination pegs—step (vii).
  • Step (viii) Copper is now plated into the patterned photoresist 126 —Step (viii) to provide the structure schematically shown in FIG. 1( viii ).
  • a solderable metal or alloy 130 is electroplated over the copper 128 into the patterned photoresist 126 —step (ix), providing the structure illustrated schematically in FIG. 1( ix ).
  • solderable alloys that may be electroplated. The most common of these is the tin-lead eutectic mixture Sn63Pb37 having a melting point of 183° C. Other solder materials include pure lead. However, in the drive to limit usage of lead, various lead free solders have been developed.
  • tin-silver Sn96.5Ag3.5 having a melting point of 221° C.
  • various tin silver copper alloys such as Sn96.5Ag3.0Cu.5 with a melting point of 218-219° C., Sn95.8Ag3.5Cu.7 with a melting point of 217-219° C., Sn95.5Ag3.8Cu.7 with a melting point of 217-219° C., Sn95.2Ag3.8Cul with a melting point of 217° C. and Sn95,5Ag4Cu.5 with a melting point of 217-219° C.
  • silver free compositions such as Sn99.3Cu.7 with a melting point of 227° C.
  • step x The photoresist 126 is now stripped away—step x, providing the structure illustrated in FIG. 1( x ) which shows the multilayer composite electronic structure with an array of upstanding copper and solder bumps.
  • step (xi) The copper seed layer 120 is now etched away—step (xi). Providing the structure shown in FIG. 1( xi ).
  • a film dielectric or dry film solder mask 132 is laminated—step (xii) over the array of solder bumps 130 .
  • a schematic illustration of the multilayer composite electronic structure 100 with the film dielectric or dry film solder mask 132 laminated over the array of solder bumps 130 is shown in FIG. 1( xii ).
  • refluxing whilst the solder caps 130 on the underlying copper via posts 128 are isolated from each other, is one way to prevent solder flow from shorting adjacent bumps.
  • CMP chemical mechanical polishing
  • FIG. 2 The process for so doing is shown in FIG. 2 , and the various structures are illustrated in FIG. 1( xiv ) a to FIG. 1( xiv ) g.
  • step a to expose the ends of the copper vias 116 , as schematically shown in FIG. 1( xiv ) a .
  • Copper is then sputtered—step b—over the ground surface to form a copper seed layer 134 as schematically shown in FIG. 1( xiv ) b .
  • photoresist 136 is now applied, exposed and developed—step c. As shown in FIG.
  • a copper layer 138 is now electroplated—step d—into the pattern of photoresist 136 .
  • the photoresist 136 is now stripped away—step e, providing the structure as illustrated in FIG. 1( xiv ) e .
  • the seed layer 134 is now etched away—step f, providing the structure illustrated in FIG. 1( xiv ) f , and then a patterned solder mask 140 is applied—step g—around and overlapping the copper pads 138 . forming the structure shown in Fig. FIG. 1( xiv ) g .
  • Solder balls may then be applied onto the copper pads 138 to create a ball grid array (BGA) interconnect of the finished package (after die assembly).
  • BGA ball grid array
  • an in-line plasma etching station 300 is schematically shown. This consists of a vacuum chamber 302 within which a carrier 304 supports a substrate 306 . Gases to be ionized for the plasma etching process, such as Oxygen, Tetrafluoro-carbon (CF 4 ) and Argon, for example, may be introduced through inlet 312 into the vacuum chamber 302 . By maintaining a potential difference between the substrate 306 and an upper electrode 308 , a plasma zone 314 is created. Optical emission spectrometer analyzers 310 detect the end point when the Sn is exposed and the copper is just covered in real time, allowing accurate computer control.
  • CF 4 Tetrafluoro-carbon
  • Argon Argon
  • the dielectric film 132 may be removed to expose the solderable cap 130 , typically of tin or a tin alloy—step (xv), see FIG. 1( xv ).
  • solderable alloys may include high surface roughness that without the usage of the right flux material during die assembly—may create voids between the substrate bumps to the die bumps during the die assembly process.
  • a finishing treatment such as to “smooth” or “coin” the top surface of the electro-plated bump on the substrate in order to further ease and assist with the flip chip assembly process—step (xvi)a.
  • Different surface treatment techniques may be used.
  • solderable caps may be coined.
  • heat may also be applied, to cause reflow of the substrate bumps.
  • Having an array of flat solderable caps with a fine, smooth surface 130 a aids attachment of a bump array of a flip chip and prevents voids at the interface of the die to substrate bumps.
  • the solderable caps on the substrate may be exposed to sufficient heat to cause reflow, which, in the absence of a compressing force to generate coining, results in the solderable material melting and forming dome shaped caps 130 b due to surface tension of the solder meniscus— FIG. 1( xvi ) b .
  • the non-coined bumps on the substrate may be directly attached to non bumped die—directly on its flat pads that may contain Ni/Au or other final metal finishes.
  • FIG. 4 a there is shown a scanning electron microphotograph (SEM micrograph) showing copper pads 402 separated with dielectric 404 on the surface of a substrate and showing upstanding copper via posts 406 thereupon from above, i.e. from an angle of 0°.
  • the scale bar is 100 microns, and shows that the via posts are approx. 50 microns in diameter.
  • FIG. 4 b there is shown a scanning electron micrograph showing copper pads separated with dielectric on the surface of the substrate and having upstanding copper via posts thereupon from above and from an angle of 45°, at a magnifications such that the scale bar is 100 microns.
  • FIG. 4 c a scanning electron micrograph is shown, illustrating copper pads 402 separated with dielectric 404 on the surface of the substrate and having upstanding copper via posts thereupon from above and from an angle of 45°, at a magnifications such that the scale bar 409 is 20 microns, and the copper via post 405 and tin layer 407 electroplated thereover are both clearly visible, the denser tin 407 is lighter than the copper 405 .
  • FIG. 4 d there is shown a scanning electron micrograph at the magnification and tilt of FIG. 4 c , showing the tin layer 410 as a dome, after reflow. This is the type of finish obtained by the process step xvi, variation b.
  • FIG. 4 e a scanning electron micrograph at very high magnification is shown, wherein the scale bar 411 shows 10 microns. This shows an upstanding copper via 405 with a tin cap 407 electroplated thereover using the same patterned photoresist to achieve perfect alignment.
  • FIG. 4 f a scanning electron micrograph at the very high magnification of FIG. 4 e is shown, wherein the scale bar shows 10 microns.
  • the tin cap 410 has been subject to heat and, due to reflow, has assumed a dome shape 410 . This is the type of finish obtained by the process step xvi, variation b.
  • FIG. 4 g an electron micrograph wherein a couple of solderable caps 420 that have been subjected to a pressing force without reflow are shown.
  • FIG. 4 h a single solderable cap that have been subjected to a pressing force without reflow is shown. Applying pressure compresses the solderable caps and densifies them, providing a surface to which the bumps of a flip chip IC may be attached.
  • copper vias 426 with compressed reflowed solderable caps 425 that have been subjected to pressure and reflow at the same time are shown.
  • flat, dense solderable caps are obtained which are dense and well adhered to the copper vias.
  • the substrate bump has a similar diameter to the solder bumps on the chips. There are typically 60 ⁇ m to 110 ⁇ m. The technology described hereinabove allows bump diameters of as little as 35 ⁇ m. These may be separated by a spacing of about 20 ⁇ m, providing a pitch of 55 ⁇ m. Indeed, micro bumps of 15 micron diameter separated by 15 micron spaces are also possible.
  • polymer dielectric films that are commercially available that have been found appropriate for laminating the very high pitch substrate arrays of the outer layers. These include NX04H available from Sekisui, HBI-800TR67680 available from Taiyo and GX-13 available from Ajinomoto.

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US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
CN107104052A (zh) * 2016-02-22 2017-08-29 欣兴电子股份有限公司 封装基板的线路制作方法
US10986726B2 (en) 2017-05-15 2021-04-20 Lg Innotek Co., Ltd. Flexible circuit board for all-in-one chip on film, chip package including same, and electronic device including same
US20190006196A1 (en) * 2017-07-03 2019-01-03 Boe Technology Group Co., Ltd. Method for packaging chip and chip package structure
CN108463053A (zh) * 2018-04-26 2018-08-28 歌尔股份有限公司 一种pcb板设计方法及pcb板
US11665826B2 (en) 2019-04-10 2023-05-30 AT&SAustria Technologie & Systemtechnik AG Component carrier and method of manufacturing the same
US11527462B2 (en) * 2019-12-13 2022-12-13 International Business Machines Corporation Circuit substrate with mixed pitch wiring

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CN104134643A (zh) 2014-11-05
US20170374747A1 (en) 2017-12-28
KR20150083008A (ko) 2015-07-16
JP6489460B2 (ja) 2019-03-27
CN104134643B (zh) 2018-11-16
TWI727918B (zh) 2021-05-21
US10779417B2 (en) 2020-09-15
TW201528461A (zh) 2015-07-16
KR101659379B1 (ko) 2016-09-23
KR101832717B1 (ko) 2018-02-28
KR20160054449A (ko) 2016-05-16
JP2015130467A (ja) 2015-07-16

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