US20130076424A1 - System and method for reducing cross coupling effects - Google Patents

System and method for reducing cross coupling effects Download PDF

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Publication number
US20130076424A1
US20130076424A1 US13/242,469 US201113242469A US2013076424A1 US 20130076424 A1 US20130076424 A1 US 20130076424A1 US 201113242469 A US201113242469 A US 201113242469A US 2013076424 A1 US2013076424 A1 US 2013076424A1
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United States
Prior art keywords
delay
input signal
bus line
inverter
delay element
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Abandoned
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US13/242,469
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English (en)
Inventor
Baker S. Mohammad
Paul D. Bassett
Martin Saint-Laurent
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Qualcomm Inc
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Qualcomm Inc
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Priority to US13/242,469 priority Critical patent/US20130076424A1/en
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BASSETT, PAUL D., MOHAMMAD, BAKER S., SAINT-LAURENT, MARTIN
Priority to PCT/US2012/056954 priority patent/WO2013044254A1/en
Priority to KR1020147010926A priority patent/KR101559436B1/ko
Priority to JP2014532079A priority patent/JP5930434B2/ja
Priority to CN201280045551.9A priority patent/CN103814366B/zh
Priority to EP12779196.0A priority patent/EP2758887B1/de
Publication of US20130076424A1 publication Critical patent/US20130076424A1/en
Priority to JP2015231635A priority patent/JP6158277B2/ja
Priority to US15/045,282 priority patent/US9785601B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure is generally related to reducing cross coupling effects.
  • wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users.
  • portable wireless telephones such as cellular telephones and internet protocol (IP) telephones
  • IP internet protocol
  • wireless telephones can communicate voice and data packets over wireless networks.
  • many such wireless telephones include other types of devices that are incorporated therein.
  • a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player.
  • such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
  • bus lines e.g., wires
  • the energy to charge the coupling capacitance may change due to relative switching activity between the bus lines. For example, when signals on two adjacent bus lines switch in the same direction at the same time, the voltage difference between the bus lines, and thus the energy to charge the coupling capacitance, may be about zero.
  • the voltage change may be V and the energy to charge the coupling capacitance may be equal to 1 ⁇ 2C c V 2 Joules, where C c is the effective capacitance between the bus lines and V is the voltage amplitude.
  • Systems and methods are disclosed that slow down (e.g., by increasing a switching delay) a rising edge of a switching signal (i.e., producing a delayed low-to-high transition) and speed up (e.g., by reducing a switching delay) a falling edge of a switching signal (i.e., producing a high-to-low transition), or vice versa, on proximately close bus lines.
  • a driver circuit may be coupled to one or more such adjacent or proximately close bus lines, where the driver circuit implements a first delay and a second delay.
  • the first delay may be in response to a high-to-low transition (e.g., in response to a signal transition from a logical ‘1’ to a logical ‘0’) and the second delay may be in response to a low-to-high transition (e.g., in response to a signal transition from a logical ‘0’ to a logical ‘1’).
  • the first and second delays may be chosen such that the difference between the first and second delays is sufficient to reduce power related to transmission of signals over the adjacent bus lines. By varying signal switching delays on adjacent bus lines, the energy dissipation due to the switching may be reduced.
  • the driver circuits may include a delay element that implements the first and second delay.
  • the delay element may be a skewed inverter, a level shifter, a latch, or a sense amplifier.
  • a device may include a plurality of driver circuits coupled to a plurality of bus lines.
  • a first driver circuit of the plurality of driver circuits may be coupled to a first bus line of the plurality of bus lines.
  • the first driver circuit may include a delay element configured to produce an output signal.
  • the output signal may transition after a first delay in response to a first digital value transition of an input signal from high to low and may transition after a second delay in response to a second digital value transition of the input signal from low to high.
  • the first delay may be different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.
  • the delay element may prevent signals on the first and second bus lines from switching at the same time, potentially reducing the energy required to switch the bus lines.
  • the delay element may include a skewed inverter, a level shifter, a latch, or a sense amplifier.
  • a second driver circuit including the delay element may be coupled to the second bus line (i.e., the second bus line may also include the delay element).
  • all of the plurality driver circuits coupled to the plurality of bus lines may include the delay element.
  • a method may include receiving a first input signal at a delay element coupled to a first bus line of a plurality of bus lines.
  • the first input signal has a first digital value transition from high to low.
  • the method further includes generating a first output signal at the delay element in response to the first input signal, where the first output signal transitions after a first delay.
  • the method further includes receiving a second input signal at the delay element.
  • the second input signal has a second digital value transition from low to high.
  • the method further includes generating a second output signal at the delay element, where the second output signal transitions after a second delay.
  • the delay element is configured to produce the output signal which transitions after the first delay in response to the first digital value transition of the input signal from high to low and transitions after the second delay in response to the second digital value transition of the input signal from low to high.
  • the first delay may be different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.
  • the delay element may prevent signals on the first and second bus lines from switching at the same time, potentially reducing the energy required to switch the bus lines.
  • the delay element may include a skewed inverter, a level shifter, a latch, or a sense amplifier.
  • an apparatus in another particular embodiment, includes means for delaying an output signal at a first bus line of a plurality of bus lines based on a digital value transition of an input signal at the first bus line.
  • the output signal transitions after a first delay in response to a first digital value transition of the input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high.
  • the first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.
  • the means for delaying comprises a skewed inverter, a level shifter, a latch, or a sense amplifier.
  • One particular advantage provided by at least one of the disclosed embodiments is a decrease in power dissipation due to cross coupling at adjacent bus lines or bus lines in close proximity.
  • Another particular advantage provided by at least one of the disclosed embodiments is an increase in battery life of an electronic device due to the decrease in power dissipation.
  • FIG. 1 is a block diagram of a particular illustrative embodiment of a system to reduce cross coupling effects on bus lines;
  • FIG. 2 is a diagram of a particular illustrative embodiment of signal transitions at the system of FIG. 1 ;
  • FIG. 3 is a diagram of a particular illustrative embodiment of a skewed inverter circuit that implements the delay element of FIG. 1 ;
  • FIG. 4 is a diagram of another particular illustrative embodiment of a skewed inverter circuit that implements the delay element of FIG. 1 ;
  • FIG. 5 is a diagram of a particular illustrative embodiment of a level shifter that implements the delay element of FIG. 1 ;
  • FIG. 6 is a diagram of another particular illustrative embodiment of a level shifter that implements the delay element of FIG. 1 ;
  • FIG. 7 is a diagram of a particular illustrative embodiment of a latch that implements the delay element of FIG. 1 ;
  • FIG. 8 is a diagram of a particular illustrative embodiment of a sense amplifier that implements the delay element of FIG. 1 ;
  • FIG. 9 is a flow chart of a particular illustrative embodiment of a method to reduce cross coupling effects on bus lines.
  • FIG. 10 is a block diagram of a wireless device including a system to reduce cross coupling effects on bus lines.
  • the system 100 includes a first component 120 coupled to a second component 130 via a plurality of bus lines 108 .
  • Each of the bus lines 108 may be coupled to one of a plurality of driver circuits 104 .
  • the first component 120 and the second component 130 are hardware components that are integrated into an electronic device, such as a wireless telephone.
  • the first component 120 and the second component 130 may include components of the electronic device described with reference to FIG. 10 .
  • a first driver circuit of the plurality of driver circuits 104 may be coupled to a first bus line (designated “1” in FIG. 1 ) of the plurality of bus lines 108 .
  • the first driver circuit may include a delay element 106 , receive an input signal 102 , and produce an output signal 110 .
  • the input signal 102 may be differential or single-ended.
  • the delay element 106 may include one of a skewed inverter, a level shifter, a latch, and a sense amplifier.
  • the input signal 102 and the output signal 110 may have the same logical value (e.g., may both be logical ‘1’ or both be logical ‘0’) or may have opposite logical values (e.g., one may be a logical ‘0’ and the other a logical ‘1’).
  • the delay element 106 includes a skewed inverter circuit (e.g., as illustrated in FIGS. 3-4 )
  • the output signal 110 may be the inverse of the input signal 102 .
  • the delay element 106 may also receive a clock signal (not shown) and may produce the output signal 110 in response to a transition in the clock signal (e.g., as further described with reference to the latch of FIG. 7 ).
  • the delay element 106 may be configured to produce the output signal 110 such that the output signal 110 transitions after a first delay in response to a first digital value transition of the input signal 102 from high to low and transitions after a second delay in response to a second digital value transition of the input signal 102 from low to high.
  • the delay element 106 may have a delay in a transitioning from a logical “0” to a logical “1” that is different than a delay in transitioning from a logical “1” to a logical “0.”
  • the first delay may be different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line (designated “2” in FIG. 1 ) in close physical proximity to the first bus line.
  • the delay elements may prevent opposite signal transitions at the bus lines from occurring simultaneously, thereby reducing cross coupling effects (e.g., illustrated in phantom at 140 ) at the bus lines.
  • FIG. 2 illustrates operation of the system 100 of FIG. 1 and is generally designated 200 .
  • the first component 120 may transmit signals to the second component 130 via the plurality of bus lines 108 .
  • the first component 120 may transmit the signals 102 , 202 across the adjacent first bus line and second bus line, respectively.
  • the signals 102 and 202 may transition in opposite directions, as illustrated in FIG. 2 .
  • driver circuits 104 coupled to the bus lines may delay corresponding output signals so as to reduce the effect of cross coupling between the bus lines.
  • the driver circuits 104 of FIG. 1 may have a “fast rising” and “slow falling” output, such that a time difference between a transition in an input signal and a corresponding rise in a corresponding output signal is shorter than a time difference between a transition in the input signal and a corresponding fall in the corresponding output signal.
  • the output signals 110 A and 210 A depict an implementation having a “fast rising” and “slow falling” output.
  • the driver circuits 104 of FIG. 1 may implement “slow rising” and “fast falling” output, such that a time difference between a transition in an input signal and a corresponding rise in a corresponding output signal is longer than a time difference between a transition in the input signal and a corresponding fall in the corresponding output signal.
  • the output signals 110 B and 210 B depict an implementation having a “slow rising” and “fast falling” output.
  • a time difference T d corresponding to the difference in rising and falling delays may be selected such that the time difference T d is sufficient to reduce the effect of cross coupling between the bus lines.
  • the time difference T d may be determined after experimentation during hardware design and based on simulation of an electronic device or system, such as the system 100 of FIG. 1 .
  • the energy dissipated due to coupling capacitance may be 2C c V 2 .
  • Such a time difference T d may be determined based on simulation and experimentation at adjacent bus lines. It should be noted that the time difference T d should be large enough to prevent signals in adjacent bus lines from switching in opposite directions at the same time, but also not too large as to unnecessarily slow down signals transitioning through the plurality of bus lines.
  • the selected time difference T d may be implemented by introducing delay elements into the circuit.
  • circuit elements having transistors whose switching delays can implement the time difference T d may be used.
  • the time difference T d may be implemented as a number of picoseconds, a number of logic gate delays, or any other measure used by those having skill in the art.
  • the system 100 of FIG. 1 may thus decrease power dissipation due to cross coupling at adjacent bus lines or bus lines in close proximity.
  • the system 100 of FIG. 1 may provide an increase in battery life of an electronic device that includes the system 100 of FIG. 1 .
  • FIG. 3 is a diagram of a particular illustrative embodiment of a skewed inverter circuit 300 that may be used to implement a delay function of the delay element 106 of FIG. 1 .
  • the skewed inverter circuit 300 may receive the input signal 102 and may produce the output signal 110 .
  • the skewed inverter circuit 300 may include a first inverter 304 , a second inverter 306 , and a NAND gate 308 .
  • the first inverter 304 may receive the input signal 102 transmitted from the first component 120 of FIG. 1 .
  • the second inverter 306 may receive an output of the first inverter 304 .
  • the NAND gate 308 may receive the input signal 102 and an output of the second inverter 306 and may produce the output signal 110 .
  • the output signal 110 produced by the skewed inverter circuit 300 i.e., an output at the NAND gate 308
  • the NAND gate 308 may receive the input signal 102 via the inverters 304 , 306 at a first input 310 and may receive the input signal 102 directly at a second input 320 . Thus, any rises or falls in the input signal 102 may arrive at the second input 320 prior to arriving at the first input 310 . In response to a fall in the input signal 102 (e.g., from a logical ‘1’ to a logical ‘0’), the NAND gate 308 may produce a corresponding rise in the output signal 110 once the fall of the input signal 102 reaches the second input 320 .
  • the NAND gate 308 may not produce a corresponding fall in the output signal 110 until the rise in the input signal 102 reaches both inputs 310 , 320 .
  • the skewed inverter circuit 300 may thus produce a “fast rising, slow falling” output.
  • the difference between the rise and fall times at the output signal 110 may be based on characteristics of the inverters 304 , 306 .
  • FIG. 4 is a diagram of another particular illustrative embodiment of a skewed inverter circuit 400 that may be used to implement functionality of the delay element 106 of FIG. 1 .
  • the skewed inverter circuit 400 may receive the input signal 102 and may produce the output signal 110 .
  • the skewed inverter circuit 400 may include a first inverter 404 , a second inverter 406 , and a NOR gate 408 .
  • the first inverter 404 may receive the input signal 102 transmitted from the first component 120 of FIG. 1 .
  • the second inverter 406 may receive an output of the first inverter 404 .
  • the NOR gate 408 may receive the input signal 102 and an output of the second inverter 406 and may produce the output signal 110 .
  • the output signal 110 may be transmitted to the second component 130 of FIG. 1 via one of the bus lines 108 (e.g., the bus line designated ‘1’ in FIG. 1 ).
  • the NOR gate 408 may receive the input signal 102 via the inverters 404 , 406 at a first input 410 and may receive the input signal 102 directly at a second input 420 . Thus, any rises or falls in the input signal 102 may arrive at the second input 420 prior to arriving at the first input 410 . In response to a rise in the input signal 102 (e.g., from a logical ‘0’ to a logical ‘1’), the NOR gate 408 may produce a corresponding fall in the output signal 110 once the rise of the input signal 102 reaches the second input 420 .
  • the NOR gate 408 may not produce a corresponding rise in the output signal 110 until the fall in the input signal 102 reaches both inputs 410 , 420 .
  • the skewed inverter circuit 400 may thus produce a “slow rising, fast falling” output.
  • the difference between the rise and fall times at the output signal 110 may be based on characteristics of the inverters 404 , 406 .
  • FIGS. 3-4 depict skewed inverter circuits that introduce 2 gates delay between rising and falling output, any number of gates delay may be implemented by adding or removing inverters and changing the logic gate accordingly. For example, two additional inverters may be inserted into the skewed inverter circuit 400 between the first inverter 404 and the second inverter 406 to implement four gates delay between rising and falling output.
  • FIG. 5 is a diagram of a particular illustrative embodiment of a level shifter 500 that may be used to implement functionality of the delay element 106 of FIG. 1 .
  • the level shifter 500 may receive the input signal 102 and may produce the output signal 110 .
  • the level shifter 500 may include a first p-type field effect transistor (PFET) 506 , a second PFET 504 , a third PFET 516 , and a fourth PFET 514 .
  • the level shifter 500 may also include a first n-type field effect transistor (NFET) 508 , a second NFET 518 , a first inverter 512 , and a second inverter 520 .
  • the first PFET 506 may be coupled in series between the second PFET 504 and the first NFET 508 .
  • the third PFET 516 may be coupled in series between the fourth PFET 514 and the second NFET 518 .
  • the first NFET 508 may receive the input signal 102 transmitted from the first component 120 of FIG. 1 at a gate of the first NFET 508 .
  • the input signal 102 may be coupled to a gate of the first PFET 506 and an inverse of the input signal 102 may be coupled to a gate of the third PFET 516 and to a gate of the second NFET 518 .
  • a gate of the second PFET 504 may be coupled to a terminal of the third PFET 516 and to a terminal of the second NFET 518 .
  • a gate of the fourth PFET 514 may be coupled to a terminal of the first PFET 506 , to a terminal of the first NFET 508 , and to the second inverter 520 which may generate the output signal 110 .
  • a source voltage (e.g., VDD out ) may be coupled to a terminal of the second PFET 504 and to a terminal of the fourth PFET 514 .
  • the same source voltage, VDD out may also be applied to the second inverter 520 .
  • a terminal of the first NFET 508 and a terminal of the second NFET 518 may be coupled to ground or to another voltage lower than the source voltage VDD out .
  • the output signal 110 produced by the level shifter 500 may be transmitted to the second component 130 of FIG. 1 via one of the bus lines 108 (e.g., the bus line designated ‘1’ in FIG. 1 ).
  • the first NFET 604 may receive the input signal 102 transmitted from the first component 120 of FIG. 1 at a gate of the first NFET 604 .
  • the input signal 102 may be coupled to an input of the fourth inverter 608
  • the second NFET 612 may be coupled to an output of the fourth inverter 608 .
  • a terminal of the first NFET 604 may be coupled to an output of the third inverter 606 and to an input of the first inverter 616 .
  • An output of the first inverter 616 may be coupled to an input of the second inverter 614 , to an input of the third inverter 606 , and to a terminal of the second NFET 612 .
  • the latch 700 may include a first n-type field effect transistor (NFET) 706 and a second NFET 716 . As illustrated in FIG. 7 , the first NFET 706 may be a “slow” NFET and the second NFET 716 may be a “fast” NFET.
  • the latch 700 may also include a first inverter 712 , a second inverter 714 , a third inverter 718 , and a fourth inverter 708 . As illustrated in FIG.
  • a gate of the fourth PFET 816 may be coupled to a gate of the fourth NFET 824 , a terminal of the sixth PFET 818 , and a terminal of the fifth NFET 826 .
  • a gate of the sixth PFET 818 may be coupled to a gate of the fifth NFET 826 , a terminal of the fourth PFET 816 , and a terminal of the fourth NFET 824 .
  • the sense amplifier 800 may include cross-coupled NAND gates 880 .
  • the cross-coupled NAND gates 880 may include a first NAND gate 881 and a second NAND gate 882 .
  • a first input of the first NAND gate 881 may be coupled to a node q 860 and may receive a signal produced at the node q 860 .
  • a second input of the first NAND gate 881 may be coupled to an output of the second NAND gate 882 .
  • a first input of the second NAND gate 882 may be coupled to an output of the first NAND gate 881 .
  • a second input of the second NAND gate 882 may be coupled to a node nq 862 and may receive a signal produced at the node nq 862 .
  • the output of the second NAND gate 882 may provide the output signal 110 of the sense amplifier 800 .
  • the output signal 110 produced by the sense amplifier 800 i.e., the output at the second NAND gate 882
  • the first NAND gate 881 may have a “slow rising” and “fast falling” output
  • the second NAND gate 882 may have a “fast rising” and “slow falling” output.
  • the cross-coupled NAND gates 880 are part of the sense amplifier 800 and coupled at nodes q 860 and nq 862 , and are shown separately from other components of the sense amplifier 800 merely for ease of illustration.
  • the sense amplifier 800 may delay the output signal 110 so as to reduce power dissipation due to cross coupling with an adjacent bus line or bus lines in close proximity.
  • the input signal 102 and the inverse 840 of the input signal 102 may be externally held high in a precharge state.
  • the nodes q 860 and nq 862 , and internal nodes x 870 and nx 872 may also be precharged high.
  • the cross-coupled NAND gates 880 (driven by the nodes q 860 and nq 862 ) may behave as inverters, thereby causing the output signal 110 of the sense amplifier 800 to maintain an initial state.
  • the first component 120 may transmit the input signal 102 to the second component 130 via the plurality of bus lines 108 .
  • the first bus line may be in close physical proximity to a second bus line.
  • a first driver circuit including the delay element 106 may be coupled to the first bus line (e.g., designated ‘1’ in FIG. 1 ) that is in close physical proximity to the second bus line (e.g., designated ‘2’ in FIG. 1 ).
  • the delay element 106 may receive the input signal 102 from the first component 120 .
  • the delay element is implemented using a clocked circuit (e.g., the latch 700 of FIG. 7 or the sense amplifier 800 of FIG. 8 where the enable signal 850 is a clock signal)
  • the method 900 may optionally include receiving a clock signal at the first driver circuit, at 915 .
  • the method 900 includes detecting a digital value transition in the input signal 102 , at 920 .
  • the delay element 106 may detect a digital value transition in the input signal 102 .
  • the method 900 may optionally include detecting a transition on the clock signal, at 925 .
  • the method 900 of FIG. 9 may reduce cross coupling at the bus lines by either delaying high to low digital value transitions more than low to high digital value transitions, or vice versa.
  • the second bus line referenced in FIG. 9 may be coupled to a second driver circuit having a second delay element.
  • the second delay element may receive a second input signal concurrently with the receipt of the input signal at the delay element, at 910 .
  • the second delay element may produce a second output signal. Similar to the output signal produced at 940 , the second output signal may transition after the first delay when the second input signal transitions from low to high.
  • the second output signal may transition after the second delay when the second input signal transitions from high to low.
  • the delay element 1094 may be coupled to a first bus line of the plurality of bus lines 1090 and the delay element 1096 may be coupled to a second bus line of the plurality of bus lines 1090 . It should be noted that the delay elements may be coupled to any bus line (or all bus lines) in the device 1000 that is used to transmit signals between the various components of the device 1000 .
  • the delay elements 1094 , 1096 may each be implemented by the skewed inverter circuit 300 of FIG. 3 , the skewed inverter circuit 400 of FIG. 4 , the level shifter 500 of FIG. 5 , the level shifter 600 of FIG. 6 , the latch 700 of FIG. 7 , or the sense amplifier 800 of FIG. 8 .
  • FIG. 10 also shows a display controller 1026 that is coupled to the DSP 1064 and to a display 1028 .
  • the coder/decoder (CODEC) 1034 can also be coupled to the DSP 1064 .
  • a speaker 1036 and a microphone 1038 can be coupled to the CODEC 1034 .
  • FIG. 10 also indicates that a wireless controller 1040 can be coupled to the DSP 1064 and to a wireless antenna 1042 .
  • the DSP 1064 , the display controller 1026 , the memory 1032 , the CODEC 1034 , the wireless controller 1040 , and the driver circuits 1090 including the delay element 1094 are included in a system-in-package or system-on-chip device 1022 .
  • an input device 1030 and a power supply 1044 are coupled to the system-on-chip device 1022 .
  • FIG. 10 illustrates that a wireless controller 1040 can be coupled to the DSP 1064 and to a wireless antenna 1042 .
  • the DSP 1064 , the display controller 1026 , the memory 1032 , the CODEC 1034 , the wireless controller 1040 , and the driver circuits 1090 including the delay element 1094 are included in a system-in-package or system-on-chip device 1022 .
  • an input device 1030 and a power supply 1044 are coupled to the
  • an apparatus includes means for delaying an output signal at a first bus line of a plurality of bus lines based on a digital value transition of an input signal at the first bus line.
  • the means for delaying may be one of the driver circuits 104 of FIG. 1 , the delay element 106 of FIG. 1 , the skewed inverter circuit 300 of FIG. 3 , the skewed inverter circuit 400 of FIG. 4 , the level shifter 500 of FIG. 5 , the level shifter 600 of FIG. 6 , the latch 700 of FIG. 7 , the sense amplifier 800 of FIG. 8 , one of the driver circuits 1090 of FIG. 10 , the delay element 1094 of FIG. 10 , the delay element 1096 of FIG. 10 , one or more other devices configured to delay the output signal, or any combination thereof.
  • the apparatus may also include means for providing the input signal to the means for delaying.
  • the means for providing may include the first component 120 of FIG. 1 , a component of the device 1000 of FIG. 10 (e.g., the CODEC 1034 ), one or more devices configured to provide the input signal to the means for delaying, or any combination thereof.
  • the output signal may transition after a first delay in response to a first digital value transition of the input signal from high to low and may transition after a second delay in response to a second digital value transition of the input signal from low to high.
  • the first delay amount may be different from the second delay amount by an amount sufficient to reduce power related to transmission of a signal over the first bus line and over a second bus line in close physical proximity to the first bus line.
  • a software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.
  • An exemplary non-transitory (e.g. tangible) storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an application-specific integrated circuit (ASIC).
  • ASIC application-specific integrated circuit
  • the ASIC may reside in a computing device or a user terminal.
  • the processor and the storage medium may reside as discrete components in a computing device or user terminal.

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US13/242,469 2011-09-23 2011-09-23 System and method for reducing cross coupling effects Abandoned US20130076424A1 (en)

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US13/242,469 US20130076424A1 (en) 2011-09-23 2011-09-23 System and method for reducing cross coupling effects
PCT/US2012/056954 WO2013044254A1 (en) 2011-09-23 2012-09-24 System and method for reducing cross coupling effects
KR1020147010926A KR101559436B1 (ko) 2011-09-23 2012-09-24 교차 결합 영향들을 감소시키기 위한 시스템 및 방법
JP2014532079A JP5930434B2 (ja) 2011-09-23 2012-09-24 交差結合効果を低減するためのシステムおよび方法
CN201280045551.9A CN103814366B (zh) 2011-09-23 2012-09-24 用于减小交叉耦合效应的系统和方法
EP12779196.0A EP2758887B1 (de) 2011-09-23 2012-09-24 System und verfahren zur verminderung von kreuzkopplungseffekten
JP2015231635A JP6158277B2 (ja) 2011-09-23 2015-11-27 交差結合効果を低減するためのシステムおよび方法
US15/045,282 US9785601B2 (en) 2011-09-23 2016-02-17 System and method for reducing cross coupling effects

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JP5930434B2 (ja) 2016-06-08
US20160162432A1 (en) 2016-06-09
EP2758887B1 (de) 2018-01-17
JP2014531673A (ja) 2014-11-27
CN103814366A (zh) 2014-05-21
JP2016042387A (ja) 2016-03-31
WO2013044254A1 (en) 2013-03-28
US9785601B2 (en) 2017-10-10
CN103814366B (zh) 2017-06-16
KR20140081834A (ko) 2014-07-01
JP6158277B2 (ja) 2017-07-05
KR101559436B1 (ko) 2015-10-12

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