US20120061637A1 - 3-d structured nonvolatile memory array and method for fabricating the same - Google Patents

3-d structured nonvolatile memory array and method for fabricating the same Download PDF

Info

Publication number
US20120061637A1
US20120061637A1 US13/131,601 US201113131601A US2012061637A1 US 20120061637 A1 US20120061637 A1 US 20120061637A1 US 201113131601 A US201113131601 A US 201113131601A US 2012061637 A1 US2012061637 A1 US 2012061637A1
Authority
US
United States
Prior art keywords
resistive
switching
memory array
switching memory
deep trenches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/131,601
Other languages
English (en)
Inventor
Yimao Cai
Ru Huang
Shiqiang Qin
Poren Tang
Lijie Zhang
Yu Tang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University
Original Assignee
Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University filed Critical Peking University
Assigned to PEKING UNIVERSITY reassignment PEKING UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAI, YIMAO, HUANG, RU, QIN, SHIQIANG, TANG, POREN, TANG, YU, ZHANG, LIJIE
Publication of US20120061637A1 publication Critical patent/US20120061637A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention refers to a field of nonvolatile memory in ULSI circuits manufacturing technology, and particularly refers to a three-dimensional-structured (3D-structured) nonvolatile memory array and a method for fabricating the same.
  • Nonvolatile memories represented by flash memory
  • storage devices and communication devices such as mobile phones, notebook computers, palmtop computers, and solid-state disks, etc.
  • flash memory has already occupied most of the market share of the nonvolatile semiconductor memory.
  • a resistive-switching memory achieves a function of nonvolatile storage by applying a voltage or a current to a resistive-switching material so as to change a resistance value thereof and holding a high resistance or a low resistance state after powered off.
  • the resistive-switching memory having advantages such as being compatible with the conventional LSI fabricating technology, excellent scalability, low operation voltage and fast operation speed, is a low cost and high performance nonvolatile memory with high capacity, which has a great potential in future applications. Meanwhile, a storage density of the nonvolatile memory can be greatly increased by employing a 3D structure, so that a cost of storage can be decreased.
  • a 3D structure of a resistive-switching memory is usually achieved by adopting a structure of cross bars and a stack of multiple layers (as shown in FIG.
  • the present invention provides a 3D-structured resistive-switching memory array which is capable of increasing a storage density of a resistive-switching memory, simplifying the fabrication process and reducing the cost of the process, and a method for fabricating the same.
  • a data storage layer is formed of a resistive-switching material
  • the resistive-switching material is disposed on sidewalls of deep trenches formed in bottom electrode metal layers and isolation dielectric layers
  • top electrodes and bottom electrodes are crossed over each other on the sidewalls of the deep trenches and, at cross-over points of the top electrodes and the bottom electrodes, the resistive-switching material is interposed between the top and bottom electrodes, thus the top electrodes and the bottom electrodes together with the interposed resistive-switching material form resistive-switching memory cells which are isolated by the isolation dielectric layers.
  • a 3D-structured resistive-switching memory array includes: a substrate and a stack structure of bottom electrodes/isolation dielectric layers; deep trenches etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer deposited on sidewalls of the deep trenches, wherein top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches, with the resistive-switching material layer being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell.
  • the resistive-switching memory cells altogether form a 3D-structure resistive-switching memory array, in which the resistive-switching memory cells are isolated by the isolation dielectric layers.
  • a thickness of the top electrode layer and the bottom electrode layers is preferably in a range of 50 nm-100 nm, a thickness of the isolation dielectric layers is normally in a range of 100 nm-200 nm, and a thickness of the resistive-switching material layer is in a range of 10 nm-50 nm.
  • the number of layers in the stack structure of the bottom electrodes/the isolation dielectric layers depends upon the fabrication process, and thus theoretically is not limited.
  • a depth of the deep trenches, which are etched in the stack structure of the bottom electrodes/the isolation dielectric layers, is in a range of 100 nm-200 nm.
  • the substrate may comprise a silicon substrate, or may comprise a quartz substrate or an organic substrate, etc.
  • the isolation dielectric layers may comprise a layer of any insulation material, such as aluminum oxide, silicon oxide, etc.
  • a method for fabricating a 3D-structured resistive-switching memory array includes the following steps:
  • the isolation dielectric layers such as silicon dioxide, silicon nitride, etc.
  • the electrode metal layers such as aluminum, copper, titanium nitride, etc.
  • a silicon substrate or other substrate such as a quartz substrate, a flexible substrate
  • An etching for forming deep trenches is performed on a stack structure in which the isolation dielectric layers and the electrode material layers are alternately deposited with the isolation dielectric layer on the substrate being used as a stop layer.
  • a resistive-switching material (such as hafnium oxide, zirconium oxide, titanium oxide, etc.) is deposited on the deep trenches, and then the resistive-switching material is etched back so that the resistive-switching material only remains on sidewalls of the deep trenches.
  • an electrode material is deposited, and then, a photolithography and an etching are performed with respect thereto so as to form patterns of top electrodes. In this way, the resistive-switching material is interposed at each of cross-over points where the top electrodes and the sidewalls of the pre-deposited electrode material cross over each other. Therefore, the 3D-structured resistive-switching memory array is formed in a vertical direction.
  • an isolation dielectric layer such as silicon dioxide, silicon nitride, etc.
  • an electrical isolation on a silicon substrate or other substrate (such as a quartz substrate, a flexible substrate);
  • steps (1) and (2) repeatedly to deposit a plurality of isolation dielectric layers and electrode metal layers.
  • the total number of the layers can be controlled flexibly, with the top-most layer being an isolation dielectric layer;
  • a resistive-switching material layer such as hafnium oxide, zirconium oxide, titanium oxide, etc.
  • the 3D resistive-switching device and the method for fabricating the same have advantages as follows when comparing to the prior art: firstly, comparing to the prior art in which a photolithography and an etching are needed to be performed each time when each electrode material layer is deposited, the method in which electrode material layers and dielectric material layers are firstly collectively deposited and then the photolithography and the etching are performed can effectively reduce the number of times by which the photolithography and the etching are performed, thus the number of steps of a fabrication process can be greatly reduced and a cost of the process can be decreased.
  • a size of the cross-over points at which the bottom electrodes and the top electrodes are crossed over each other is controlled by a deposition thickness of the bottom electrode material, therefore it is not limited by a resolution of the photolithography, and a size of the device can be further reduced effectively and the storage density can be improved.
  • the 3D-structured resistive-switching memory array as described above and the method for fabricating the same are economic and effective solutions for improving the density of the resistive-switching memory.
  • FIG. 1 is a schematic view of a conventional 3D-structured resistive-switching memory array, wherein “ 1 ” denotes top electrodes, “ 2 ” denotes bottom electrodes, and “ 3 ” denotes resistive-switching material.
  • FIG. 2 is a schematic view of a 3D-structured resistive-switching memory array according to the prevent invention, wherein “ 01 ” denotes a silicon substrate, “ 02 ” denotes bottom electrodes, “ 03 ” denotes isolation dielectric layers, “ 04 ” denotes resistive-switching material, and “ 05 ” denotes top electrodes.
  • FIGS. 3( a )- 3 ( e ) are schematic views illustrating a method for fabricating a 3D-structured resistive-switching memory array according to a preferred embodiment of the present invention.
  • a cross-sectional view indicating a structure of a device may not be scaled according to a normal proportion and may be enlarged partially for purpose of illustration.
  • the illustrative views are merely examples, which are not intended to limit the scope of the invention.
  • a 3D spatial size with length, width and depth should be included in an actual fabrication.
  • the inventor has found out, through research, that if a 3D technology is applied suitably to a resistive-switching memory device, advantages of both the new storage material and the 3D integrated technology can be combined, so that problems of decrease in scalability, high operational power consumption and high operational voltage of the conventional nonvolatile memory can be solved. Moreover, a storage density of the nonvolatile memory can be further increased, and a performance of the nonvolatile memory can be improved. The storage density and the performance of the nonvolatile memory can be improved greatly if a 3D-structured resistive-switching memory array and a method for fabricating the same can be proposed by optimizing a fabrication process without increasing a complexity of the process.
  • the present invention provides an innovative 3D resistive-switching memory array and a method for fabricating the same, in which a structure of 3D resistive-switching devices can be formed by depositing dielectric layers and electrode layers alternately to form a stack, performing an photolithography and an etching with respect to the entire stack, and forming a resistive-switching material on sidewalls.
  • a storage density can be increased, the number of steps of the process can be reduced, and a cost can be decreased.
  • a 3D resistive-switching memory array includes a silicon substrate 01 , bottom electrodes 02 , isolation dielectric layers 03 , resistive-switching material 04 , and top electrodes 05 .
  • the bottom electrodes 02 and the top electrodes 05 are crossed over each other on sidewalls of deep trenches in a stack structure of the bottom electrodes/the isolation dielectric layers, and the resistive-switching material 04 is interposed at respective cross-over points.
  • Each of the cross-over points forms a memory cell and is isolated by the dielectric layers, and the cells altogether form a 3D resistive-switching memory array.
  • a method for fabricating the above-mentioned 3D resistive-switching memory array includes following steps.
  • Isolation dielectric layers such as silicon dioxide, silicon nitride, etc.
  • electrode metal layers such as aluminum, copper, titanium nitride, etc.
  • An etching for forming deep trenches is performed on a stack structure in which the isolation dielectric layers and the electrode material layers are alternately deposited, with the isolation dielectric layer on the substrate being used as a stop layer.
  • Resistive-switching material such as hafnium oxide, zirconium oxide, titanium oxide, etc.
  • Resistive-switching material is deposited on the deep trenches, and then the resistive-switching material is etched so that the resistive-switching material only remains on sidewalls of the deep trenches.
  • electrode material is deposited, and an photolithography and an etching are performed with respect to the electrode material to form patterns of top electrodes. In this way, the resistive-switching material is interposed at respective cross-over points of the top electrodes and the sidewalls of the electrode materials deposited previously. Therefore, a 3D resistive-switching memory array is formed in the vertical direction.
  • An isolation dielectric layer (which comprises silicon dioxide in the present embodiment) having a thickness of 100 nm-200 nm, which functions as an electrical isolation, is deposited on a silicon substrate.
  • a TiN electrode layer having a thickness of 50 nm-100 nm is deposited on the isolation dielectric layer.
  • steps (1) and (2) are performed repeatedly to deposit a plurality of isolation dielectric layers and electrode metallic layers alternately, wherein the total number of the layers can be controlled flexibly, and the top-most layer is an isolation dielectric layer, as shown in FIG. 3( a ).
  • a photolithography and an etching are performed with respect to the structure of the plurality of the isolation dielectric layers/the electrode metallic layers deposited as described above until a bottom-most dielectric layer, so that a plurality of deep trenches are formed, wherein a width of each of the deep trenches is 100 nm-200 nm, and sidewalls of the deep trenches have a stack structure of isolation dielectric layers and electrode metal layers, as shown in FIG. 3( b ).
  • a resistive-switching material layer (which comprises titanium oxide in the present embodiment) having a thickness of 10 nm-50 nm is deposited by using the deep trenches as windows, and an etch-back process is performed so that only the resistive-switching material layer on the sidewalls of the deep trenches are remained, as shown in FIG. 3( c ).
  • a TiN electrode layer having a thickness of 50 nm-100 nm is deposited ( FIG. 3( d )), and a photolithography and an etching are performed with respect to the TiN electrode layer to form top electrodes, wherein the top electrodes, the resistive-switching material layer and the metallic layers on the sidewalls of the deep trenches form 3D resistive-switching memory device and an array thereof, as shown in FIG. 3( e ).
  • the semiconductor device and the method for fabricating the same can be also applied to other resistive-switching memory arrays comprising a substrate, resistive-switching material, an isolation dielectric layer and electrode material, and a detailed description thereof is omitted.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
US13/131,601 2010-09-13 2011-04-01 3-d structured nonvolatile memory array and method for fabricating the same Abandoned US20120061637A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN2010102795058A CN101976676A (zh) 2010-09-13 2010-09-13 一种三维结构非易失存储器阵列及其制备方法
CN201010279505.8 2010-09-13
PCT/CN2011/072370 WO2012034394A1 (fr) 2010-09-13 2011-04-01 Matrice mémoire non volatile à structure tridimensionnelle et son procédé de fabrication

Publications (1)

Publication Number Publication Date
US20120061637A1 true US20120061637A1 (en) 2012-03-15

Family

ID=43576544

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/131,601 Abandoned US20120061637A1 (en) 2010-09-13 2011-04-01 3-d structured nonvolatile memory array and method for fabricating the same

Country Status (3)

Country Link
US (1) US20120061637A1 (fr)
CN (1) CN101976676A (fr)
WO (1) WO2012034394A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130175496A1 (en) * 2012-01-11 2013-07-11 Hye-Jung Choi Semiconductor memory device, memory chip, memory module, memory system and method for fabricating the same
US20140145137A1 (en) * 2012-11-28 2014-05-29 Hyunsu Ju Resistive Random Access Memory Devices Having Variable Resistance Layers
US8829581B1 (en) 2013-04-19 2014-09-09 Hewlett-Packard Development Company, L.P. Resistive memory devices
US9099648B2 (en) 2013-05-02 2015-08-04 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor memory device and semiconductor memory device
US9190155B2 (en) 2013-01-21 2015-11-17 Samsung Electronics Co., Ltd. Memory system
US9269429B2 (en) 2014-07-18 2016-02-23 Samsung Electronics Co., Ltd. Resistive memory device, resistive memory system, and method of operating resistive memory device
CN106205681A (zh) * 2015-04-29 2016-12-07 复旦大学 用于三维竖直堆叠阻变存储器抑制IR drop电压降和读写干扰的架构和操作算法
US20180315794A1 (en) * 2017-04-26 2018-11-01 Sandisk Technologies Llc Methods and apparatus for three-dimensional nonvolatile memory

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976676A (zh) * 2010-09-13 2011-02-16 北京大学 一种三维结构非易失存储器阵列及其制备方法
CN102522418B (zh) * 2011-12-29 2013-09-11 北京大学 具有交叉阵列结构的自整流阻变存储器及制备方法
CN102522501A (zh) * 2011-12-29 2012-06-27 北京大学 具有交叉阵列结构的阻变存储器及制备方法
CN102969328B (zh) * 2012-12-06 2015-09-16 北京大学 阻变存储器交叉阵列结构及其制备方法
CN103022350B (zh) * 2012-12-28 2015-01-07 北京大学 忆阻器件及其制备方法
CN104409632B (zh) * 2014-05-31 2017-05-10 福州大学 一种多层结构有机阻变存储器的3d打印制备方法
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108305936A (zh) * 2017-01-12 2018-07-20 中芯国际集成电路制造(上海)有限公司 阻变随机存储器存储单元及其制作方法、电子装置
CN109256462B (zh) * 2018-09-11 2022-12-06 西安建筑科技大学 一种集成化阻变存储器及其制备方法
CN109962161A (zh) * 2018-12-03 2019-07-02 复旦大学 基于内置非线性rram的3d垂直交叉阵列及其制备方法
CN111312746B (zh) * 2020-04-07 2023-07-25 上海集成电路研发中心有限公司 一种阻变存储器阵列结构及制作方法
CN113421963A (zh) * 2021-06-10 2021-09-21 北京大学 一种低功耗三维阻变存储器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100155687A1 (en) * 2008-12-24 2010-06-24 Imec Method for manufacturing a resistive switching memory device and devices obtained thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100978911B1 (ko) * 2008-02-28 2010-08-31 삼성전자주식회사 반도체 장치 및 그의 형성방법
US8114468B2 (en) * 2008-06-18 2012-02-14 Boise Technology, Inc. Methods of forming a non-volatile resistive oxide memory array
KR101583717B1 (ko) * 2009-01-13 2016-01-11 삼성전자주식회사 저항 메모리 장치의 제조방법
TWI433302B (zh) * 2009-03-03 2014-04-01 Macronix Int Co Ltd 積體電路自對準三度空間記憶陣列及其製作方法
US8546861B2 (en) * 2009-03-05 2013-10-01 Gwangju Institute Of Science And Technology Resistance change memory device with three-dimensional structure, and device array, electronic product and manufacturing method therefor
JP5390918B2 (ja) * 2009-04-14 2014-01-15 シャープ株式会社 不揮発性半導体記憶装置とその製造方法
CN101976676A (zh) * 2010-09-13 2011-02-16 北京大学 一种三维结构非易失存储器阵列及其制备方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100155687A1 (en) * 2008-12-24 2010-06-24 Imec Method for manufacturing a resistive switching memory device and devices obtained thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130175496A1 (en) * 2012-01-11 2013-07-11 Hye-Jung Choi Semiconductor memory device, memory chip, memory module, memory system and method for fabricating the same
US20140145137A1 (en) * 2012-11-28 2014-05-29 Hyunsu Ju Resistive Random Access Memory Devices Having Variable Resistance Layers
US9059395B2 (en) * 2012-11-28 2015-06-16 Samsung Electronics Co., Ltd. Resistive random access memory devices having variable resistance layers and related methods
US9190155B2 (en) 2013-01-21 2015-11-17 Samsung Electronics Co., Ltd. Memory system
US8829581B1 (en) 2013-04-19 2014-09-09 Hewlett-Packard Development Company, L.P. Resistive memory devices
US9099648B2 (en) 2013-05-02 2015-08-04 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor memory device and semiconductor memory device
US9362500B2 (en) 2013-05-02 2016-06-07 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor memory device and semiconductor memory device
US9634064B2 (en) 2013-05-02 2017-04-25 Kabushiki Kaisha Toshiba Semiconductor memory device having stacked word lines and conductive pillar
US9269429B2 (en) 2014-07-18 2016-02-23 Samsung Electronics Co., Ltd. Resistive memory device, resistive memory system, and method of operating resistive memory device
CN106205681A (zh) * 2015-04-29 2016-12-07 复旦大学 用于三维竖直堆叠阻变存储器抑制IR drop电压降和读写干扰的架构和操作算法
US20180315794A1 (en) * 2017-04-26 2018-11-01 Sandisk Technologies Llc Methods and apparatus for three-dimensional nonvolatile memory

Also Published As

Publication number Publication date
WO2012034394A1 (fr) 2012-03-22
CN101976676A (zh) 2011-02-16

Similar Documents

Publication Publication Date Title
US20120061637A1 (en) 3-d structured nonvolatile memory array and method for fabricating the same
JP5859121B2 (ja) メモリセル構造
EP1916722B1 (fr) Mémoire de filament de carbone et procédé de fabrication
JP4763858B2 (ja) 半導体メモリの製造方法
EP3619752A1 (fr) Dispositif de mémoire vive résistive contenant des lignes de mots de remplacement et son procédé de fabrication
US10096654B2 (en) Three-dimensional resistive random access memory containing self-aligned memory elements
US8705274B2 (en) Three-dimensional multi-bit non-volatile memory and method for manufacturing the same
CN104425512A (zh) 半导体器件
TW201032315A (en) Three-dimensional semiconductor structure and method of fabricating the same
JP2015532789A (ja) ３次元メモリアレイアーキテクチャ
TWI686931B (zh) 三維記憶體陣列及其形成方法
CN102687298A (zh) 具有包括磁性隧道结的顶部电极及底部电极的装置的制造与集成
US11362140B2 (en) Word line with air-gap for non-volatile memories
CN102157688A (zh) 一种阻变存储器及其制备方法
CN103872055A (zh) 一种垂直沟道型三维半导体存储器件及其制备方法
US8895953B1 (en) Programmable memory elements, devices and methods having physically localized structure
US11152561B2 (en) Magnetic memory device
CN103137860A (zh) 非易失性三维半导体存储器件及制备方法
US9812641B2 (en) Non-volatile memory device and methods for fabricating the same
CN104465983B (zh) 磁性隧道结及其形成方法
CN104269407B (zh) 一种非易失性高密度三维半导体存储器件及其制备方法
US11955529B2 (en) Semiconductor device with interlayer insulation structure including metal-organic framework layer and method of manufacturing the same
CN102446541A (zh) 磁性随机存取存储器及其制造方法
CN111403410B (zh) 存储器及其制备方法
TW202218149A (zh) 用於形成記憶體裝置之方法以及相關裝置及系統

Legal Events

Date Code Title Description
AS Assignment

Owner name: PEKING UNIVERSITY, CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CAI, YIMAO;HUANG, RU;QIN, SHIQIANG;AND OTHERS;REEL/FRAME:026435/0446

Effective date: 20110524

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION