US20110298009A1 - Epitaxial substrate for electronic device and method of producing the same - Google Patents

Epitaxial substrate for electronic device and method of producing the same Download PDF

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US20110298009A1
US20110298009A1 US13/131,411 US200913131411A US2011298009A1 US 20110298009 A1 US20110298009 A1 US 20110298009A1 US 200913131411 A US200913131411 A US 200913131411A US 2011298009 A1 US2011298009 A1 US 2011298009A1
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substrate
epitaxial substrate
electronic device
single crystal
epitaxial
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Tetsuya Ikuta
Jo Shimizu
Tomohiko Shibata
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Dowa Electronics Materials Co Ltd
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Dowa Electronics Materials Co Ltd
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Assigned to DOWA ELECTRONICS MATERIALS CO., LTD. reassignment DOWA ELECTRONICS MATERIALS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IKUTA, TETSUYA, SHIBATA, TOMOHIKO, SHIMIZU, JO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to an epitaxial substrate for an electronic device and a method of producing the same and, in particular, to an epitaxial substrate for a HEMT and a method producing the same.
  • HEMT High electron mobility transistor
  • FET Field effect transistor
  • FIG. 1 Such a FET-type transistor as described above is generally formed, as schematically illustrated in FIG. 1 , for example, by laminating a channel layer 22 and an electron supply layer 23 on an insulating substrate 21 and then providing a surface of the electron supply layer 23 with a source electrode 24 , a drain electrode 25 and a gate electrode 26 .
  • this transistor device When this transistor device is operated, electrons are moved through the source electrode 24 , the electron supply layer 23 , the channel layer 22 , the electron supply layer 23 and the drain electrode 25 in this order, thereby defining a lateral direction of the device as a main current conducting direction.
  • This movement of electrons in the lateral direction is controlled by voltage applied on the gate electrode 26 .
  • electrons generated at a joint interface between the electron supply layer 23 and the channel layer 22 of which band gaps are different from each other can move significantly fast, as compared with electrons in a conventional semiconductor.
  • An epitaxial substrate formed by epitaxially growing a Group III nitride laminated body on a semiconductor substrate is generally used as an epitaxial substrate for a FET.
  • Examples of such a semiconductor substrate as described above include: a Si substrate having specific resistance exceeding 10 2 ⁇ cm for use to decrease substrate loss which deteriorates device performances, as disclosed in JP 2008-522447 Laid-Open; and a Si substrate having specific resistance of 1.0 to 500 ⁇ 19 cm or so for use to decrease leak current to the Si substrate, as disclosed in JP 2003-059948 Laid-Open.
  • JP 06-112120 Laid-open discloses a technique for decreasing the absolute value of warpage by determining in advance a warping direction in a semiconductor substrate and then adequately growing epitaxial layers on the substrate.
  • JP 06-112120 Laid-open simply aims at decreasing the absolute value of warpage of an epitaxial substrate and determines in advance only warpage derived from a slicing process of slicing a wafer from an ingot. Therefore, JP 06-112120 Laid-open cannot control a final warp configuration of the epitaxial substrate in a sufficient manner. JP 06-112120 Laid-open also has a problem that a production process thereof is complicated because it includes a process of determining a warping direction of the semiconductor substrate.
  • An object of the present invention is to solve the aforementioned problems and provide an epitaxial substrate for an electronic device, in which substrate a lateral direction thereof is defined as a main current conducting direction and a warp configuration thereof is adequately controlled, and a method of producing the epitaxial substrate.
  • the present invention is primarily structured as follows.
  • An epitaxial substrate for an electronic device including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ⁇ cm.
  • a method of producing an epitaxial substrate for an electronic device in which a Group III nitride laminated body is formed by epitaxially growing plural Group III nitride layers on a Si single crystal substrate such that a lateral direction of the substrate is defined as a main current conducting direction, comprising forming the Si single crystal substrate to be a p-type substrate having a specific resistance value of not larger than 0.01 ⁇ cm by adding boron thereto at a relatively high concentration.
  • a warp configuration of an epitaxial substrate for an electronic device can be appropriately controlled without deteriorating performances of the device, by setting a specific resistance value of a Si single crystal substrate at a preferred value or lower.
  • a warp configuration of an epitaxial substrate for an electronic device can be appropriately controlled by setting a specific resistance value of a Si single crystal substrate at a preferred value or lower by adding boron to the Si single crystal substrate at a relatively high concentration.
  • FIG. 1 is a schematic sectional view showing a typical field effect transistor (FET).
  • FET field effect transistor
  • FIG. 2 is a schematic sectional view of an epitaxial substrate for an electronic device according to the present invention.
  • FIG. 3 is a schematic view for explaining “BOW”.
  • FIG. 4 is a schematic view for explaining “SORI”.
  • FIGS. 5( a ) to 5 ( d ) are views of sectional warp configurations of various types.
  • FIGS. 6( a ) to 5 ( d ) are views of sectional warp configurations of various types.
  • FIGS. 7( a ) to 7 ( d ) are views each showing surface contour lines and a sectional configuration of the epitaxial substrate for an electronic device, measured by using a configuration measuring device.
  • FIG. 2 schematically shows a sectional structure of an epitaxial substrate for an electronic device according to the present invention.
  • an epitaxial substrate 1 for an electronic device of the present invention including: a Si single crystal substrate 2 ; and a Group III nitride laminated body 3 formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate 2 , wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate 2 is a p-type substrate having a specific resistance value of not larger than 0.01 ⁇ cm.
  • the present invention is based on a discovery that, in an epitaxial substrate for an electronic device, having such a structure as described above, a warp configuration thereof can be appropriately controlled without deteriorating performances of the device.
  • a lateral direction is defined as a main current conducting direction” means that electric current flows from the soured electrode to the drain electrode, i.e. predominantly in the widthwise direction of the laminated body, differing from, for example, a structure in which a semiconductor is interposed by a pair of electrodes such that electric current flows predominantly in the vertical direction, i.e. in the thickness direction of the laminated body.
  • a value of specific resistance of the Si single crystal substrate 2 is adjusted by adding a p-type impurity element to the Si single crystal substrate.
  • the p-type impurity element include boron, aluminum, gallium, and the like.
  • boron is preferably used because boron can be added at a relatively high concentration. In this regard, it is preferable to add boron at a concentration of 10 19 /cm 3 or higher in order to adjust a specific resistance value of the Si single crystal substrate 2 to not larger than 0.01 ⁇ cm.
  • the dimension of the Si single crystal substrate 2 can be appropriately selected depending on applications.
  • a face, for use, of the Si single crystal substrate is not particularly specified and any face such as (111) face, (100) face, (110) face can be used.
  • Use of (111) face is, however, preferable because then growth of (0001) face of Group III nitride is easily facilitated and surface-flatness of an epitaxial substrate improves.
  • a warp configuration of an epitaxial substrate for an electronic device can be optimized by adjusting a specific resistance value of the Si single crystal substrate 2 to not larger than 0.01 ⁇ cm, as described above.
  • appropriateness of a warp configuration is defined by the absolute value of a value obtained by subtracting “SORI” as shown in FIG. 4 from the absolute value of “BOW” as shown in FIG. 3 .
  • a “BOW” value represents, as shown in FIG.
  • a “SORI” value represents a distance in the vertical direction between a plane, passing through the highest position of a measurement surface of an epitaxial substrate and in parallel with the best-fit reference plane, and a plane, passing through the lowest position of the measurement surface and in parallel with the best-fit reference plane in a non-adsorbed state of the epitaxial substrate, as shown in FIG. 4 .
  • a sectional warp configuration of the epitaxial substrate 1 for an electronic device according to the present invention preferably satisfies a relationship formula below.
  • peripheral portions of the epitaxial substrate within 3 mm measured from edges of the substrate, are to be excluded in measurement of the BOW and SORI values because deformation in a relatively narrow range may be generated in the peripheral portion of the epitaxial substrate due to a SORI configuration of the Si single crystal substrate itself, a processed configuration of edges of the substrate, and the like.
  • FIGS. 5( a ) to 5 ( d ) are views of sectional warp configurations of various types.
  • FIGS. 6( a ) to 6 ( d ) are actually views of the same sectional warp configurations as those of FIGS. 5( a ) to 5 ( d ).
  • Broken lines in FIG. 5 and FIG. 6 are used to measure BOW values and SORI value.
  • FIGS. 5( a ) to 5 ( c ) and FIGS. 6( a ) to 6 ( c ) each represent a case where a value of
  • a sectional warp configuration of the epitaxial substrate 1 for an electronic device is preferably bowed monotonously in one direction, as show in FIG. 5( a ) and FIG. 6( a ).
  • differs from a value of SORI, whereby the larger absolute value of the difference between
  • a sectional warp configuration of the epitaxial substrate for an electronic device is preferably bowed monotonously over the entire width thereof, as show in FIG. 5( a ) and FIG. 6( a ), so that warp can be easily corrected to suppress exposure failure of the device due to maladsorption.
  • the peripheral portions of the epitaxial substrate, within 3 mm measured from edges of the substrate, are to be excluded in consideration of the sectional warp configuration of the epitaxial substrate, as described above.
  • a buffer 4 as an insulating layer between the Si single crystal substrate 2 and the Group III nitride laminated body 3 . Provision of the buffer 4 as an insulating layer prevents electric current from flowing into the Si single crystal substrate 2 , suppresses leak current in the vertical direction which could be facilitated by use of the Si substrate having relatively low specific resistance, and improves breakdown voltage of the substrate.
  • the buffer 4 preferably includes a lamination 4 a constituted of a superlattice multilayer structure.
  • the superlattice multilayer structure preferably contains C (carbon) at a concentration of 1 ⁇ 10 18 /cm 3 or more because then generation of carriers due to band discontinuities is suppressed and breakdown voltage of the buffer can be further improved.
  • C carbon
  • the upper limit of the C concentration is not particularly limited, the upper limit thereof is preferably not higher than 1 ⁇ 10 20 /cm 3 in terms of suppressing generation of pits in the Group III nitride laminated body 3 . Formation of the conventional superlattice generally involves steep changes in interfaces thereof.
  • the present invention may further include cases where another layer is inserted between interfaces, a composition of an interface is continuously varied, a composition of the superlattice multilayer structure is varied, and the like, within a scope not marring the technical effect of the present invention.
  • thickness of a layer having a relatively large band gap, of the lamination 4 a is preferably equal to or larger than the thickness capable of suppressing tunneling current and equal to or smaller than the thickness which reliably avoids generation of cracks.
  • a layer having a relatively large band gap, of the lamination 4 a is preferably formed by using AlN having the largest band gap among the Group III nitrides so as to have a thickness of 2 to 10 nm.
  • a layer having a relatively small band gap, of the lamination 4 a preferably contains at least Al so that carbon can be effectively incorporated at a sufficiently high concentration.
  • a layer having a relatively small band gap, of the lamination 4 a is preferably thicker than a layer having a relatively large band gap, of the lamination 4 a , and equal to or thinner than 40 nm in order to effectively demonstrate a strain-alleviating effect of the superlattice multilayer structure and suppress generation of cracks. Further, for similar reasons, difference in composition between a layer having a relatively small band gap and a layer having a relatively large band gap, of the lamination 4 a , is necessary and difference in composition of Al therebetween is preferably at least 50%, i.e.
  • the number of laminated-layer pairs of the superlattice multilayer structure is not particularly restricted. The larger number of such pairs results in the better suppression of leak current in the vertical direction and improvement of breakdown voltage.
  • the epitaxial substrate 1 for an electronic device of the present invention in which a lateral direction of the epitaxial substrate 1 is defined as a main current conducting direction, is characteristically produced by: forming a Si single crystal substrate 2 to be a p-type substrate having a specific resistance value of not larger than 0.01 ⁇ 19 cm by adding boron thereto at a relatively high concentration; and epitaxially growing plural Group III nitride layers on the Si single crystal substrate 2 to form a Group III nitride laminated body 3 . Due to such a structure as described above, the epitaxial substrate for an electronic device of the present invention can adequately control a warp configuration thereof without deteriorating performances of the device.
  • boron is added at a concentration of 10 19 /cm 3 or more so as to evenly exist across the entire region of the substrate.
  • Boron may be either added as an impurity to Si single crystal when the Si single crystal is produced by the CZ method, the FZ method or the like, or introduced to the substrate by ion injection, thermal diffusion, or the like.
  • boron need not be added across the entire region of the Si single crystal substrate at the preferred B content described above and it suffices that boron is added at the preferred content to at least a portion of the substrate.
  • the present invention includes an application where a substrate containing boron at the aforementioned concentration or more is provided with a Si film formed thereon of which boron content is lower than the aforementioned concentration and an application where portions having B content lower than the aforementioned preferred content locally exist within the Si substrate.
  • the present invention includes an application where a surface-modified layer such as a Si nitride film, a carbide film, an oxide film or the like is formed as an initial layer on the substrate surface and an application where the substrate includes a material other than Si and Group III nitrides.
  • the epitaxial substrate for an electronic device of the present invention may contain impurities other than B, such as Al, Ga, In, P, Sb, As, H, C, Ge, N, O and the like. Impurities are preferably added in order to increase hardness of the Si single crystal substrate.
  • a buffer as an insulating layer including a lamination constituted of a superlattice multilayer structure is formed on the Si single crystal substrate prior to formation of the Group III nitride laminated body and thereafter the Group III nitride laminated body having a HEMT structure is formed on the buffer.
  • Each of the lamination of a superlattice multilayer structure and the Group III nitride laminated body of a HEMT structure can be formed by a thin-film laminating method of various types, such as MOCVD, MBE, HYPE and the like.
  • FIGS. 1 to 6 show typical examples of the embodiments and the present invention is not restricted to these illustrated examples of the embodiments.
  • a Si single crystal substrate of 3-inch diameter (plate thickness: 625 ⁇ m, content of added boron: 2 ⁇ 10 19 /cm 3 : specific resistance: 0.005 ⁇ cm, crystal face (111)) was heated in an atmosphere of hydrogen and nitrogen at 1050° C. Thereafter, an AlN layer having film thickness 200 nm and an Al 0.25 Ga 0.75 N layer having film thickness 50 nm were formed on the Si single crystal substrate by adjusting supply rates of trimethylgallium (TMG), trimethylaluminum (TMA) and NH 3 by using the MOCVD method.
  • TMG trimethylgallium
  • TMA trimethylaluminum
  • NH 3 trimethylgallium
  • an insulating superlattice multilayer structure as a lamination of 80 pairs of alternately laminated an AlN film (film thickness: 4 nm) and an Al 0.15 Ga 0.85 N film (film thickness: 25 nm) was formed on the Al 0.25 Ga 0.75 N layer by adjusting supply rates of trimethylgallium (TMG), trimethylaluminum (TMA) and NH 3 .
  • TMG trimethylgallium
  • TMA trimethylaluminum
  • NH 3 NH 3
  • the average Carbon concentration of the superlattice multilayer structure was 2 ⁇ 10 18 /cm 3 .
  • a GaN layer of 1.5 ⁇ m thickness and an Al 0.25 Ga 0.75 N layer (film thickness 20 nm) functioning as lateral-direction current conducting layers were formed on the superlattice multilayer structure, whereby an epitaxial substrate for an electronic device was prepared.
  • An epitaxial substrate for an electronic device was prepared in the same manner as in Example 1, except that the content of added boron was 1 ⁇ 10 19 /cm 3 and specific resistance of the Si single crystal substrate was 0.01 ⁇ cm.
  • An epitaxial substrate for an electronic device was prepared in the same manner as in Example 1, except that the content of added boron was 4 ⁇ 10 18 /cm 3 and specific resistance of the Si single crystal substrate was 0.02 ⁇ cm.
  • An epitaxial substrate for an electronic device was prepared in the same manner as in Example 1, except that the content of added boron was 1.5 ⁇ 10 16 /cm 3 and specific resistance of the Si single crystal substrate was 1 ⁇ cm.
  • An epitaxial substrate for an electronic device was prepared in the same manner as in Example 1, except that the content of added boron was 8 ⁇ 10 14 /cm 3 and specific resistance of the Si single crystal substrate was 25 ⁇ cm.
  • An epitaxial substrate for an electronic device was prepared in the same manner as in Example 1, except that the content of added boron was 1 ⁇ 10 13 /cm 3 and specific resistance of the Si single crystal substrate was 5000 ⁇ cm.
  • FIGS. 7( a ) to 7 ( d ) show surface contour lines and sectional warp configurations of the epitaxial substrates of Example 1, Comp. Example 1, Comp. Example 2 and Comp. Example 4 obtained by the configuration measuring device, respectively.
  • Table 1 show the measurement results of the BOW values and the SORI values of these epitaxial substrates.
  • FIG. 7( a ) the sectional warp configuration of the epitaxial substrate for an electronic device of Example 1 of the present invention is monotonously bowed in one direction. It is also understood from FIGS. 7( b ) to 7 ( d ) that the sectional warp configurations of the epitaxial substrates for electronic devices of Comp. Example 1, Comp. Example 2 and Comp. Example 4 are not monotonously bowed in one direction. Further, it is understood from Tables 1 and 2 that Examples 1 and 2 according to the present invention can reduce a value itself of and variation in ⁇ Bow
  • Thickness and dimensions of the epitaxial substrate for an electronic device of the present invention are not particularly restricted to those in Examples described above and may be appropriately selected depending applications in use.
  • a warp configuration of an epitaxial substrate for an electronic device can be appropriately controlled without deteriorating performances of the device, by setting a specific resistance value of a Si single crystal substrate at a preferred value or lower.

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JP2008-302620 2008-11-27
JP2009260014A JP4519196B2 (ja) 2008-11-27 2009-11-13 電子デバイス用エピタキシャル基板およびその製造方法
JP2009-260014 2009-11-13
PCT/JP2009/069896 WO2010061865A1 (ja) 2008-11-27 2009-11-18 電子デバイス用エピタキシャル基板およびその製造方法

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Cited By (14)

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US20110240962A1 (en) * 2008-12-15 2011-10-06 Dowa Electronics Materials Co., Ltd. Epitaxial substrate for electronic device and method of producing the same
US20150171173A1 (en) * 2012-09-13 2015-06-18 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US20150194442A1 (en) * 2012-10-12 2015-07-09 Sumitomo Electric Industries, Ltd Group iii nitride composite substrate and method for manufacturing the same, and method for manufacturing group iii nitride semiconductor device
US9166031B2 (en) 2013-09-05 2015-10-20 Fujitsu Limited Semiconductor device
US9196685B2 (en) 2013-09-27 2015-11-24 Fujitsu Limited Semiconductor device and manufacturing method thereof
US20160059371A1 (en) * 2014-09-01 2016-03-03 Fu Tai Hua Industry (Shenzhen) Co., Ltd. System for machining surface of workpiece and method thereof
US20160111273A1 (en) * 2013-05-31 2016-04-21 Sanken Electric Co., Ltd. Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device
US20160118488A1 (en) * 2013-07-19 2016-04-28 Sharp Kabushiki Kaisha Field effect transistor
US9608103B2 (en) 2014-10-02 2017-03-28 Toshiba Corporation High electron mobility transistor with periodically carbon doped gallium nitride
US9673052B2 (en) 2013-05-31 2017-06-06 Sanken Electric Co., Ltd. Silicon-based substrate having first and second portions
EP3282041A1 (en) * 2013-02-15 2018-02-14 AZUR SPACE Solar Power GmbH P doping of group iii nitride buffer layer structure on a heterosubstrate
US9923063B2 (en) 2013-02-18 2018-03-20 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same
US10186451B2 (en) 2013-02-08 2019-01-22 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device
US20200194545A1 (en) * 2018-12-12 2020-06-18 Coorstek Kk Nitride semiconductor substrate

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5543866B2 (ja) * 2010-07-16 2014-07-09 Ｄｏｗａエレクトロニクス株式会社 Ｉｉｉ族窒化物エピタキシャル基板
JP5384450B2 (ja) * 2010-09-03 2014-01-08 コバレントマテリアル株式会社 化合物半導体基板
KR101720589B1 (ko) * 2010-10-11 2017-03-30 삼성전자주식회사 이 모드(Ｅ-ｍｏｄｅ) 고 전자 이동도 트랜지스터 및 그 제조방법
JP5059205B2 (ja) 2011-03-03 2012-10-24 株式会社東芝 ウェーハ及び結晶成長方法
JP5460751B2 (ja) * 2012-01-16 2014-04-02 株式会社東芝 半導体装置
JP2014022698A (ja) * 2012-07-24 2014-02-03 Dowa Holdings Co Ltd 窒化物半導体成長用Ｓｉ基板およびそれを用いた電子デバイス用エピタキシャル基板およびそれらの製造方法
JP2014072429A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 半導体装置
JP6154604B2 (ja) * 2012-12-07 2017-06-28 住友化学株式会社 窒化物半導体エピタキシャルウェハ
JP6108609B2 (ja) 2013-04-25 2017-04-05 クアーズテック株式会社 窒化物半導体基板
JP2017216257A (ja) * 2014-10-14 2017-12-07 シャープ株式会社 窒化物半導体およびそれを用いた電子デバイス
JP2017054955A (ja) * 2015-09-10 2017-03-16 株式会社東芝 半導体装置
JP2018041851A (ja) * 2016-09-08 2018-03-15 クアーズテック株式会社 窒化物半導体基板
JPWO2019151441A1 (ja) * 2018-02-01 2021-02-25 住友化学株式会社 半導体ウエハー及びその製造方法
JP7179706B2 (ja) * 2018-12-12 2022-11-29 クアーズテック株式会社 窒化物半導体基板
JP2024094561A (ja) * 2022-12-28 2024-07-10 信越半導体株式会社 エピタキシャル基板の製造方法及びエピタキシャル基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060068601A1 (en) * 2004-09-29 2006-03-30 Jeong-Sik Lee Wafer for compound semiconductor devices, and method of fabrication
US20070215905A1 (en) * 2004-05-31 2007-09-20 Kenji Kohiro Compound Semiconductor Epitaxial Substrate and Process for Producing the Same
US20080017952A1 (en) * 2006-07-24 2008-01-24 Asm America, Inc. Strained layers within semiconductor buffer structures

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3274190B2 (ja) 1992-09-26 2002-04-15 株式会社東芝 半導体エピタキシャル基板の製造方法
US5393993A (en) * 1993-12-13 1995-02-28 Cree Research, Inc. Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices
JP2003059948A (ja) 2001-08-20 2003-02-28 Sanken Electric Co Ltd 半導体装置及びその製造方法
JP4329984B2 (ja) * 2002-02-28 2009-09-09 古河電気工業株式会社 Ｉｉｉ−ｖ族窒化物半導体の層構造体、その製造方法
US6969824B2 (en) * 2003-07-16 2005-11-29 Lincoln Global, Inc. Locking device for latch assembly
JP4725763B2 (ja) * 2003-11-21 2011-07-13 サンケン電気株式会社 半導体素子形成用板状基体の製造方法
JP4332720B2 (ja) * 2003-11-28 2009-09-16 サンケン電気株式会社 半導体素子形成用板状基体の製造方法
US7247889B2 (en) 2004-12-03 2007-07-24 Nitronex Corporation III-nitride material structures including silicon substrates
JP2007059595A (ja) * 2005-08-24 2007-03-08 Toshiba Corp 窒化物半導体素子
US8853666B2 (en) * 2005-12-28 2014-10-07 Renesas Electronics Corporation Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
JP2007242853A (ja) * 2006-03-08 2007-09-20 Sanken Electric Co Ltd 半導体基体及びこれを使用した半導体装置
JP5158833B2 (ja) * 2006-03-31 2013-03-06 古河電気工業株式会社 窒化物系化合物半導体装置および窒化物系化合物半導体装置の製造方法。
JP2008034411A (ja) * 2006-07-26 2008-02-14 Toshiba Corp 窒化物半導体素子
JP5224311B2 (ja) 2007-01-05 2013-07-03 古河電気工業株式会社 半導体電子デバイス
JP5309452B2 (ja) * 2007-02-28 2013-10-09 サンケン電気株式会社 半導体ウエーハ及び半導体素子及び製造方法
JP5170859B2 (ja) * 2007-03-29 2013-03-27 古河電気工業株式会社 基板及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070215905A1 (en) * 2004-05-31 2007-09-20 Kenji Kohiro Compound Semiconductor Epitaxial Substrate and Process for Producing the Same
US20060068601A1 (en) * 2004-09-29 2006-03-30 Jeong-Sik Lee Wafer for compound semiconductor devices, and method of fabrication
US20080017952A1 (en) * 2006-07-24 2008-01-24 Asm America, Inc. Strained layers within semiconductor buffer structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Machine translation of Katou et al., JP 2008-171843 *

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8410472B2 (en) * 2008-12-15 2013-04-02 Dowa Electronics Materials Co., Ltd. Epitaxial substrate for electronic device and method of producing the same
US20110240962A1 (en) * 2008-12-15 2011-10-06 Dowa Electronics Materials Co., Ltd. Epitaxial substrate for electronic device and method of producing the same
US9401403B2 (en) * 2012-09-13 2016-07-26 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US20150171173A1 (en) * 2012-09-13 2015-06-18 Panasonic Intellectual Property Management Co., Ltd. Nitride semiconductor structure
US20150194442A1 (en) * 2012-10-12 2015-07-09 Sumitomo Electric Industries, Ltd Group iii nitride composite substrate and method for manufacturing the same, and method for manufacturing group iii nitride semiconductor device
US10600676B2 (en) * 2012-10-12 2020-03-24 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device
US9917004B2 (en) * 2012-10-12 2018-03-13 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device
US11094537B2 (en) 2012-10-12 2021-08-17 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device
US10186451B2 (en) 2013-02-08 2019-01-22 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device
US10026814B2 (en) 2013-02-15 2018-07-17 Azurspace Solar Power Gmbh P-doping of group-III-nitride buffer layer structure on a heterosubstrate
EP2767620B1 (en) * 2013-02-15 2024-10-09 AZUR SPACE Solar Power GmbH P-doping of group-III-nitride buffer layer structure on a heterosubstrate
EP3282041A1 (en) * 2013-02-15 2018-02-14 AZUR SPACE Solar Power GmbH P doping of group iii nitride buffer layer structure on a heterosubstrate
US10211296B2 (en) 2013-02-15 2019-02-19 Azurspace Solar Power Gmbh P-doping of group-III-nitride buffer layer structure on a heterosubstrate
US9923063B2 (en) 2013-02-18 2018-03-20 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same
US20160111273A1 (en) * 2013-05-31 2016-04-21 Sanken Electric Co., Ltd. Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device
US9520286B2 (en) * 2013-05-31 2016-12-13 Shanken Electric Co., Ltd. Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device
US9673052B2 (en) 2013-05-31 2017-06-06 Sanken Electric Co., Ltd. Silicon-based substrate having first and second portions
US9966259B2 (en) 2013-05-31 2018-05-08 Shanken Electric Co., Ltd. Silicon-based substrate, semiconductor device, and method for manufacturing semiconductor device
US9437726B2 (en) * 2013-07-19 2016-09-06 Sharp Kabushiki Kaisha Field effect transistor
US20160118488A1 (en) * 2013-07-19 2016-04-28 Sharp Kabushiki Kaisha Field effect transistor
US9166031B2 (en) 2013-09-05 2015-10-20 Fujitsu Limited Semiconductor device
US9196685B2 (en) 2013-09-27 2015-11-24 Fujitsu Limited Semiconductor device and manufacturing method thereof
US20160059371A1 (en) * 2014-09-01 2016-03-03 Fu Tai Hua Industry (Shenzhen) Co., Ltd. System for machining surface of workpiece and method thereof
US9608103B2 (en) 2014-10-02 2017-03-28 Toshiba Corporation High electron mobility transistor with periodically carbon doped gallium nitride
US10825895B2 (en) * 2018-12-12 2020-11-03 Coorstek Kk Nitride semiconductor substrate
US20200194545A1 (en) * 2018-12-12 2020-06-18 Coorstek Kk Nitride semiconductor substrate

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