US20090212007A1 - Surface treatment method - Google Patents

Surface treatment method Download PDF

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Publication number
US20090212007A1
US20090212007A1 US12/393,341 US39334109A US2009212007A1 US 20090212007 A1 US20090212007 A1 US 20090212007A1 US 39334109 A US39334109 A US 39334109A US 2009212007 A1 US2009212007 A1 US 2009212007A1
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Prior art keywords
metal film
etching
exposed
foreign
treatment method
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US12/393,341
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English (en)
Inventor
Yuji Usui
Goshi Imai
Shigeki Ishitobi
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IMAI, GOSHI, ISHITOBI, SHIGEKI, USUI, YUJI
Publication of US20090212007A1 publication Critical patent/US20090212007A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/04—Signs, boards or panels, illuminated from behind the insignia
    • G09F13/0413—Frames or casing structures therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/04—Signs, boards or panels, illuminated from behind the insignia
    • G09F13/0418—Constructional details
    • G09F13/0445—Frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/20—Illuminated signs; Luminous advertising with luminescent surfaces or parts
    • G09F13/22—Illuminated signs; Luminous advertising with luminescent surfaces or parts electroluminescent
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F19/00—Advertising or display means not otherwise provided for
    • G09F19/12—Advertising or display means not otherwise provided for using special optical effects
    • G09F19/16—Advertising or display means not otherwise provided for using special optical effects involving the use of mirrors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F13/00—Illuminated signs; Luminous advertising
    • G09F13/20—Illuminated signs; Luminous advertising with luminescent surfaces or parts
    • G09F13/22—Illuminated signs; Luminous advertising with luminescent surfaces or parts electroluminescent
    • G09F2013/222—Illuminated signs; Luminous advertising with luminescent surfaces or parts electroluminescent with LEDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F27/00—Combined visual and audible advertising or displaying, e.g. for public address
    • G09F2027/001—Comprising a presence or proximity detector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0736—Methods for applying liquids, e.g. spraying
    • H05K2203/075—Global treatment of printed circuits by fluid spraying, e.g. cleaning a conductive pattern using nozzles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to a surface treatment method, and relates in particular to a surface treatment method for easily removing a foreign resin substance that has been attached to the exposed surface of a metal film.
  • a pad is prepared, as shown in FIG. 5 , on one face of a printed circuit board 10 , for the formation thereon of a solder bump 18 that will serve as an external connection terminal.
  • the structure of this pad includes a metal film 12 , such as a copper film, deposited on the face of the printed circuit board 10 , a resin layer 14 , such as a solder resist layer, that covers the peripheral edges of the metal film 12 , and a protective metal layer 16 that is formed on and covers the exposed surface of the metal film 12 .
  • the portion of the exposed surface to which the foreign resin substance 20 is attached may be unaffected by the etching, as shown in FIG. 7 , leaving the foreign resin substance 20 attached to the exposed surface. Should this occur, and should electroplating or electroless plating be used to form the protective metal layer 16 , the plating process could not be successfully performed, since the protective metal layer 16 would neither be deposited on nor cover the surface portion to which the foreign resin substance 20 is attached.
  • a remedial method proposed in patent document 2 provides for the performance of a plasma treatment process to remove the foreign resin substance 20 from the exposed surface of the metal film 12 .
  • one objective of the present invention is to resolve this conventional problem, which is occasioned by the extensive damage sustained by a resin layer when the plasma treatment process is employed to completely remove, from a metal film surface exposed through the resin layer, an attached foreign resin substance, by providing a surface treatment method whereby, without substantially damaging a resin layer, a foreign resin substance and an oxide film can be removed from the surface of a metal film exposed through the resin layer.
  • the present inventors found that, substantially, the resin layer does not suffer extensive damage when the foreign resin substance is merely roughened by the plasma treatment process.
  • the present inventors found that when a nozzle is used to spray etching fluid onto a metal film, etching of the surface of the metal film occurs along the circumferential edge of the foreign resin substance that is attached, and the foreign resin substance can be easily removed. Thus, the present inventors are encouraged to initiate the process to prepare the present invention.
  • a surface treatment method including the steps of:
  • the metal film is deposited on at least one face of a printed circuit board
  • the surface of the metal film exposed through the resin layer is located on the same circuit board side as a pad on which an external connection terminal is formed.
  • a copper film is deposited, as a metal film, and
  • soft etching is performed, with using a spray etching method, so as to remove an oxide film from an exposed surface of the copper film.
  • a metal plated film is deposited with using plating as the metal film.
  • the pressure setting for the ejection, through the nozzle, of the etching fluid is from 0.1 to 0.3 MPa.
  • a surface treatment method including the steps of:
  • etching the entire exposed surface of the metal film with using a spray etching method for which an etching fluid is ejected through a nozzle to remove the scratch from the exposed surface.
  • the metal film is deposited on at least one face of a printed circuit board
  • the surface of the metal film exposed through the resin layer is located on the same circuit board side as a pad on which an external connection terminal is formed.
  • a copper film is deposited, as a metal film, and
  • soft etching is performed, with using a spray etching method, so as to remove an oxide film from an exposed surface of the copper film.
  • a metal plated film is deposited with using plating as the metal film.
  • the pressure setting for the ejection, through the nozzle, of the etching fluid is from 0.1 to 0.3 MPa.
  • the metal film is deposited on at least one face of a printed circuit board, and the metal film surface exposed through the resin layer is located on the same circuit board side as a pad on which an external connection terminal is formed.
  • a copper film is deposited, as a metal film, and soft etching is performed, using a spray etching method, to remove an oxide film from an exposed surface of the copper film.
  • a metal plated film deposited using plating, is appropriate as a metal film.
  • a plasma treatment process is performed, to roughen a foreign resin substance that is attached to the surface of a metal film exposed through a resin layer. It is considered proven that roughening of a foreign resin substance can reduce the adhesiveness evidenced by a foreign resin substance that is attached to an exposed surface of a metal film.
  • the exposed surface of the metal film to which the roughened, foreign resin substance is attached is etched using a spray etching method, according to which an etching fluid is ejected through a nozzle.
  • the etching fluid does not etch the foreign resin substance directly.
  • etching of the surface of the metal film occurs along the peripheral edge of the foreign resin substance. As a result, the foreign resin substance can be completely removed.
  • the exposed surface of the metal film is selectively etched, so that the exposed surface of the metal film can be smoothed and leveled to remove scratches, and oxide film on the exposed surface of the metal film can be removed.
  • the surface of the metal film exposed through the resin layer can be smoothed and oxide film formations can be removed, and electroplating or electroless plating can be employed to form a uniform protective metal layer on the exposed surface of the metal film.
  • FIG. 1 is a diagram for explaining the state wherein a foreign resin substance, attached to the exposed surface of a metal film, can be removed by using spray etching.
  • FIGS. 2A to 2C are diagrams for explaining the process for smoothing, using spray etching, the exposed surface of a metal film that is scratched.
  • FIGS. 3A and 3B are microscope photographs, according to one example of the present invention, of pad faces exposed on a printed circuit board before a plasma treatment is performed, and of the pad faces on the printed circuit board after the plasma treatment and spray etching processes have been performed.
  • FIGS. 4A and 4B are microscope photographs, according to a comparison example, of pad faces exposed on a printed circuit board before a plasma treatment process is performed, and of the pad faces on the printed circuit board after the plasma treatment and spray etching processes have been performed.
  • FIG. 5 is a diagram for explaining the structure of a pad face on a printed circuit board.
  • FIG. 6 is a diagram for explaining the state wherein a foreign resin substance is attached to the surface of a metal film, exposed through a resin layer, that forms a pad face.
  • FIG. 7 is a diagram for explaining the state wherein a foreign resin substance, attached to the exposed surface of the metal film, is not removed, even after the exposed surface is immersed in an etching fluid.
  • FIG. 8 is a diagram for showing processes in an apparatus for performing a spray etching.
  • the plasma treatment process is performed to roughen a foreign substance formed by a resin, such as a solder resist, that has been attached to the surface of a metal film, such as a copper film, exposed through a resin layer, such as a solder resist layer.
  • a resin such as a solder resist
  • a plasma used for the plasma treatment process employ either an O 2 , He or Ar gas and have an output of about 100 to 400 W.
  • the plasma irradiation of an object such as the surface of a metal film, deposited on a printed circuit board, that is exposed through a resin layer, be performed under a reduced pressure for a period of from 100 to 500 seconds, or more preferably, of from 200 to 300 seconds.
  • a plasma irradiation period of less than 100 seconds is used, appropriate roughening of a foreign resin substance tends to be difficult.
  • a plasma irradiation period exceeding 300 seconds is used, although a foreign resin substance can be appropriately roughened, resin layer damage tends to be increased.
  • a spray etching method is employed during which an etching fluid is ejected and sprayed on the metal film, through a nozzle, to etch the exposed surface of the metal film to which a foreign resin substance, roughened by the plasma treatment, is attached.
  • the pressure setting for the ejection, through the nozzle, of the etching fluid be from 0.1 to 0.3 MPa, so that the exposed surface of the metal film can be etched to a depth of 1 to 3 ⁇ m.
  • the etching fluid does not etch the resin layer and the foreign resin substance; however, as shown in FIG. 1 , the surface of a metal film 12 , onto which the etching fluid is ejected, is etched. That is, the surface of the metal film 12 is etched along the peripheral edge of an attached foreign resin substance 20 , and as a result, the adhesiveness exhibited by the foreign resin substance is considerably reduced.
  • the surface of the metal film 12 , to which the foreign resin substance 20 is attached is etched as the etching fluid permeates the roughened foreign resin substance 20 , the adhesiveness exhibited by the foreign resin substance 20 is further reduced.
  • the foreign resin substance 20 can be easily removed from the surface of the metal film 12 using the pressure employed to eject the etching fluid through the nozzle.
  • etching of the exposed surface of the metal film 12 may be performed, as needed, using dip etching, for which the exposed surface is immersed in an etching fluid.
  • the spray etching processes are performed by, for example, the apparatus as shown in FIG. 8 .
  • a uniform protective metal layer 16 can be deposited, using either electroplating or electroless plating, on the exposed surface of the metal film 12 that has been smoothed.
  • a plurality of pad faces 12 a are arranged on one face of a printed circuit board.
  • metal films 12 are formed, using electrolytic copper plating, that are exposed through a resin layer 14 , which is thereafter formed using a solder resist.
  • the printed circuit board is then placed in a chamber under a reduced pressure of 300 Pa, and the plasma treatment process is performed by irradiating the pad faces 12 a for 300 seconds with a plasma that employed O 2 gas and had an output of 300 W.
  • the resultant printed circuit board is observed using a microscope, it could be seen that the surface of the foreign resin substance had been roughened and had a sponge-like appearance.
  • the surface of the resin layer 14 is only slightly roughened, and on the whole, the state of the resin layer 14 is almost the same as before the plasma treatment process is performed.
  • an etching fluid for etching the copper that forms the pad faces 12 a on the printed circuit board, is ejected through a nozzle, under a pressure of 0.2 MPa, and sprayed onto the pad faces 12 a , and the surface layers of the pad faces 12 a are etched to a depth of about 2 ⁇ m.
  • a distance of about 100 mm is set between the distal end of the nozzle and the pad faces 12 a.
  • the pad faces 12 a are observed using a microscope, and it is found, as shown in FIG. 3B , that the foreign resin substance 20 , previously located within the area encircled by the white dotted line on the one pad face 12 a , had been completely removed.
  • etching of the pad faces 12 a may be performed using dip etching, for which a printed circuit board is immersed in an etching fluid.
  • a foreign resin substance originally a solder resist
  • a material a substance
  • an arbitrary foreign resin substance formed by an organic material other than solder resist can be removed by performing spray etching, after the plasma treatment process has been performed in the same manner as in the example.
  • a printed circuit board is employed in this example, whereon pad faces 12 a , 12 a . . . made of copper shown in FIG. 4A , are exposed through a resin layer 14 formed of a solder resist, and a foreign resin substance is attached to one of the pad faces 12 a at a location encircled by a white dotted line as shown in FIG. 4A .
  • the surface treatment process is performed in the same manner as in the example, except that instead of performing spray etching, the printed circuit board is immersed in an etching fluid, whereby the pad faces 12 a are etched to a depth of about 3 ⁇ m.
  • FIG. 4B is a diagram showing a microscope photograph of the pad faces 12 a on the printed circuit board obtained after the etching process had been performed. As shown in FIG. 4B , the foreign resin substance shown in FIG. 4A , which is attached to the pad face 12 a of the printed circuit board before the plasma treatment process, had not been removed from the location encircled by the white dotted line.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Marketing (AREA)
  • Accounting & Taxation (AREA)
  • Business, Economics & Management (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • ing And Chemical Polishing (AREA)
  • Wire Bonding (AREA)
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US12/393,341 2008-02-27 2009-02-26 Surface treatment method Abandoned US20090212007A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-045564 2008-02-27
JP2008045564A JP5139120B2 (ja) 2008-02-27 2008-02-27 表面処理方法

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US20090212007A1 true US20090212007A1 (en) 2009-08-27

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US20210359276A1 (en) * 2018-09-06 2021-11-18 Kaneka Corporation Method for producing partition wall, image display device and method for producing same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597988A (en) * 1983-06-06 1986-07-01 Macdermid, Incorporated Process for preparing printed circuit board thru-holes
US5077176A (en) * 1990-07-30 1991-12-31 At&T Bell Laboratories Pre-plate cleaning process
US5197889A (en) * 1992-02-03 1993-03-30 Motorola, Inc. Electrical contact for battery package or similar device
US6445969B1 (en) * 1997-01-27 2002-09-03 Circuit Image Systems Statistical process control integration systems and methods for monitoring manufacturing processes
US6489240B1 (en) * 2001-05-31 2002-12-03 Advanced Micro Devices, Inc. Method for forming copper interconnects

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637063A (ja) * 1992-07-15 1994-02-10 Yamaha Corp 半導体装置の製法
JPH06168917A (ja) * 1992-11-30 1994-06-14 Miyagi Oki Denki Kk レジスト除去方法
JPH07321027A (ja) * 1994-05-27 1995-12-08 Canon Inc レジスト層の除去方法及びそれを用いた除去装置
JPH0992960A (ja) * 1995-09-26 1997-04-04 Hitachi Chem Co Ltd レジスト膜の剥離装置
JP2002212779A (ja) * 2001-01-10 2002-07-31 Hitachi Ltd 表面処理方法およびそれを用いた薄膜磁気ヘッドの製造方法と薄膜磁気ヘッド
JP2003017436A (ja) * 2001-07-04 2003-01-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3987781B2 (ja) * 2002-09-30 2007-10-10 日本特殊陶業株式会社 配線基板の製造方法
JP4323252B2 (ja) * 2003-08-04 2009-09-02 住友精密工業株式会社 レジスト除去装置
JP4761040B2 (ja) * 2005-10-24 2011-08-31 セイコーエプソン株式会社 シリコンデバイスの製造方法及び液体噴射ヘッドの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597988A (en) * 1983-06-06 1986-07-01 Macdermid, Incorporated Process for preparing printed circuit board thru-holes
US5077176A (en) * 1990-07-30 1991-12-31 At&T Bell Laboratories Pre-plate cleaning process
US5197889A (en) * 1992-02-03 1993-03-30 Motorola, Inc. Electrical contact for battery package or similar device
US6445969B1 (en) * 1997-01-27 2002-09-03 Circuit Image Systems Statistical process control integration systems and methods for monitoring manufacturing processes
US6489240B1 (en) * 2001-05-31 2002-12-03 Advanced Micro Devices, Inc. Method for forming copper interconnects

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TW200944089A (en) 2009-10-16

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