US20080258704A1 - Method and apparatus for identifying broken pins in a test socket - Google Patents

Method and apparatus for identifying broken pins in a test socket Download PDF

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Publication number
US20080258704A1
US20080258704A1 US11/738,541 US73854107A US2008258704A1 US 20080258704 A1 US20080258704 A1 US 20080258704A1 US 73854107 A US73854107 A US 73854107A US 2008258704 A1 US2008258704 A1 US 2008258704A1
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US
United States
Prior art keywords
test socket
test
scanner
operable
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/738,541
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English (en)
Inventor
Matthew S. Ryskoski
Christopher L. Wooten
Song Han
Douglas C. Kimbrough
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/738,541 priority Critical patent/US20080258704A1/en
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RYSKOSKI, MATTHEW S, HAN, SONG, KIMBROUGH, DOUGLAS C, WOOTEN, CHRISTOPHER L
Priority to KR1020097022856A priority patent/KR20100036222A/ko
Priority to CN200880013102A priority patent/CN101861524A/zh
Priority to JP2010506217A priority patent/JP2010525365A/ja
Priority to DE112008001088T priority patent/DE112008001088T5/de
Priority to PCT/US2008/004961 priority patent/WO2008133833A1/en
Priority to TW097114442A priority patent/TW200903009A/zh
Publication of US20080258704A1 publication Critical patent/US20080258704A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. AFFIRMATION OF PATENT ASSIGNMENT Assignors: ADVANCED MICRO DEVICES, INC.
Priority to GB0918661A priority patent/GB2461454A/en
Priority to US12/946,386 priority patent/US8040140B2/en
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Abandoned legal-status Critical Current

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/95Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/3193Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70Testing of connections between components and printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/308Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation

Definitions

  • the present invention relates generally to semiconductor device testing and, more particularly, to a method and apparatus for identifying broken pins in a test socket.
  • Semiconductor die are normally formed in large quantities on wafers of semiconductor material, for example, silicon. After die are singulated from the wafers, they may be individually packaged in plastic or ceramic packages, for example.
  • a lead frame may support the die for wire bonding and packaging and provide the lead system for the completed package.
  • electrical circuitry formed on the die is coupled to bond pads on the die to facilitate interconnection of the electrical circuitry with the outside world.
  • each bond pad is electrically connected by way of wire leads to the lead frame.
  • the electrical connection includes a wire bond formed on the bond pad, a wire lead and a wire bond formed on the lead frame.
  • An encapsulating material protects and insulates the die, and the die is mounted in a package having external pins for interconnecting the electrical circuitry on the die, via the wire bonds, to the outside world.
  • Burn-in testing involves accelerated stressing of the parts by subjecting the device to stress level operating conditions for the purpose of accelerating early failures that may occur when the device is assembled in a product. Burn-in generally involves elevating the temperature of a device beyond normal operating conditions and electrically exercising the device. Of course, other types of test programs may be implemented to verify/establish performance grades and operating characteristics.
  • sockets are employed to allow testing of multiple devices in parallel or in sequence.
  • the sockets are mounted to a circuit board through which various electrical signals are provided under the direction of a test program to implement the required tests.
  • Devices under test (DUT) are inserted into the sockets by automatic handling equipment that aligns each DUT with a socket and applies an insertion force to seat the device in the socket.
  • one or more pins on the DUT may not be aligned sufficiently with the corresponding contact holes in the socket to allow the pin to be properly inserted or seated. In some cases, the pin may become bent, broken, or wedged into the socket. Depending on the particular pin damaged and the nature of the damage, the device may or may not pass the functional test.
  • a damaged pin may remain in the socket. Subsequently, when a different DUT is inserted into the socket, the corresponding pin may not be able to be inserted into the socket as the contact hole is plugged. As a result the pin on the second DUT may itself become damaged.
  • a broken pin may not be identified until a failure trend is recognized and a subsequent manual inspection is performed to verify functionality of the socket.
  • a subsequent manual inspection is performed to verify functionality of the socket.
  • multiple devices may be damaged or the test results associated with the devices may be compromised.
  • One aspect of the present invention is seen in a method that includes scanning a test socket after removal of a device under test to generate scan data.
  • the scan data is compared to reference data.
  • a presence of at least a portion of a pin in the test socket is identified based on the comparison.
  • test socket is operable to receive devices under test.
  • the scanner is operable to scan a test socket after removal of a device under test to generate scan data.
  • the control unit is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin in the test socket based on the comparison.
  • FIG. 1 is a simplified block diagram of a testing system in accordance with one illustrative embodiment of the present invention
  • FIG. 2 is a top view of a socket employed in the test system of FIG. 1 ;
  • FIG. 3 is a partial diagram of the system of FIG. 1 illustrating an optical scanner
  • FIG. 4 is a partial diagram of the system of FIG. 1 illustrating a scanner that captures an image of the test socket;
  • FIG. 5 is a partial diagram of the system of FIG. 1 illustrating an electrical scanner
  • FIGS. 6A , 6 B, and 6 C illustrate various exemplary contact arrangements that may be used in the test socket in conjunction with the electrical scanner of FIG. 5 ;
  • FIG. 7 is a simplified flow diagram for identifying a damage pin in the test socket of FIG. 2 in accordance with another illustrative embodiment of the present invention.
  • the test system 100 includes a test unit 110 including a test socket 120 and test circuitry 130 , a scanner 140 , a control unit 150 , and a database 160 .
  • the test system 100 receives a device under test 170 in the test socket 120 and performs testing operations to verify operation or determine performance characteristics of the device under test 170 .
  • test unit 110 may include multiple test sockets 120 to allow sequential or parallel testing of multiple devices under test 170 by the test circuitry 130 .
  • the particular type of testing performed by the test unit 110 is not material to the practice of the embodiments of the present invention.
  • Those of ordinary skill in the art are familiar with the testing operations that may be performed and the configuration of the test circuitry 130 required to implement the tests.
  • the scanner 140 and control unit 150 are illustrated as being distinct units, it is contemplated that they may be integrated into a single unit or one or both may be integrated into the test unit 110 .
  • the scanner 140 scans the test socket 120 (e.g., optically or electrically) between insertions of devices under test 170 to identify damaged pins that may have become separated from any device under test 170 and lodged in the test socket 120 during the insertion and removal processes.
  • the frequency of the scanning may vary depending on the particular embodiment.
  • the test socket 120 may be scanned between each insertion of a device under test 170 .
  • the scan may be completed at a fixed frequency (e.g., every five insertions).
  • the scanner 140 communicates scan results to the control unit 150 , which analyzes the scan data to identify a potential pin lodged in the test socket 120 .
  • the control unit 150 may store the scan data in the database 160 . In some embodiments, the control unit 150 may store all scan results, while in other embodiments, the control unit 150 may store only scan data associated with suspected damaged pins.
  • the test socket 120 includes a plurality of openings 200 for receiving pins of the device under test 170 .
  • a damaged pin 210 is lodged in one of the openings 200 .
  • the damaged pin 210 causes the characteristics of the test socket 120 to change as compared to a reference state.
  • the measurements conducted by the scanner 140 aid the control unit 150 in identifying the changed characteristics to identify the damaged pin 210 .
  • the particular arrangement of test socket 120 with respect to the number and arrangement of openings 200 may vary depending on the particular embodiment and the structure of the device under test 170 .
  • the scanner 140 is an optical scanner that scans the test socket 120 through illumination or by capturing an image of the test socket 120 .
  • the scanner 140 is an electrical scanner that evaluates the electrical characteristics of the test socket 120 (e.g., resistance) to identify the presence of the damaged pin 210 .
  • the scanner 140 may include a light source 300 (e.g., laser) and a detector 310 operable to measure characteristics (e.g., intensity at one or more frequencies) of light originating from the light source and reflected by the test socket 120 to the detector 310 .
  • the orientation of the light source 300 with respect to the detector 310 may vary depending on the particular embodiment. Also, the geometries of the light source 300 and detector 310 may vary from the example illustrated. In the illustrated embodiment, the light source 300 and detector 310 are arranged in a perpendicular orientation with respect to the test socket 120 .
  • the optical scan data is compared to reference data to identify a discrepancy that may indicate the presence of a pin in the test socket 120 .
  • the measured scan data may be compared to a reference intensity threshold.
  • the presence of a pin may be identified in response to the measured intensity violating the predetermined threshold, i.e., either in the positive or negative direction depending on the optical characteristics of the test socket 120 and/or the pins.
  • the scanner 140 may scan the entire test socket 120 or, alternatively, the scanner 140 may scan only a portion of the test socket 120 and report results for each partial scan to the control unit 150 .
  • the scanner 140 may capture an image 400 of the test socket 120 and compare the captured image 400 to a reference image 410 to identify the damaged pin 210 .
  • the reference image 410 may be generated in advance for the test socket 120 or the reference image 410 may generated using one or more previous scans of the test socket 120 for which it was know that no damaged pin 210 was present. By updating the reference image 410 a changing environment in the proximity of the test system 100 (e.g., ambient lighting) or changes to the test socket 120 due to usage may be accounted for, thereby reducing the potential for an errant scan result.
  • Various techniques may be used for comparing the captured image 400 to the reference image 410 . For example, pixels or groups of pixels may be compared to identify the presence of a damaged pin 210 . In an embodiment where the test socket 120 is a dark color, a metallic pin would appear as a significantly brighter group of pixels. Hence, the damaged pin 210 may be identified in response to the average color of a group of pixels in the captured image 400 differing from the expected average color from the reference image 410 . Other comparison techniques may also be used. In some embodiments, a pixel by pixel comparison may be made and various statistics may be determined, such as mean absolute error, mean squared error, root mean squared error, peak squared error, peak signal to noise ration, different pixel count, etc. One or more of the difference statistics may be compared to determine if the captured image 400 is sufficiently different than the reference image 410 to suggest the presence of one or more damaged pins 210 .
  • the scanner 140 may electrically coupled to the test socket 120 to perform an electrical scan of the test socket 120 to identify the damaged pin 210 .
  • the scanner 140 may communicate with or may be integrated into the test circuitry 130 .
  • the scanner 140 performs an electrical test on the test socket 120 to determine the presence of a damaged pin 210 .
  • An exemplary electrical test for determining the presence of a damaged pin 210 is a continuity test or a signal injection test.
  • the test socket 120 may include contacts 600 , 610 that are normally not in communication with one another.
  • the contact 600 may represent the test contact used for functional testing of the device under test 170 and the contact 610 may be a scan contact used only for the identification of the damaged pin 210 .
  • the scanner 140 may check for continuity between the test contact 600 and the scan contact 610 .
  • the scanner 140 may inject a signal at the scan contact 610 and query the test circuitry 130 to determine if the signal is present on the test contact 600 . If continuity or a response to the signal is present, it is likely that a damaged pin 210 is lodged within the opening 200 .
  • the orientation of the contacts 600 , 610 may vary depending on the particular embodiment. For example, both contacts 600 , 610 may be disposed on the sidewall of the opening 200 , as shown in FIG. 6A . In another embodiment shown in FIG. 6B , one contact 600 , 610 may be disposed on a sidewall of the opening 200 , and the other contact 600 , 610 may be located at the bottom of the opening 200 . In yet another embodiment shown in FIG. 6C , two scan contacts 610 , 620 may be provided to allow the scan to be completed independently of the test contact 600 . In such an embodiment, the scanner 140 need not communicate with the test circuitry 130 to determine if continuity or a signal response is present.
  • the scanner 140 provides the scan results to the control unit 150 , which analyzes the scan results to identify the presence of a damaged pin 210 .
  • the control unit 150 compares the scan data to reference data, for example, by comparing a measured intensity to a reference intensity or a captured image to a reference image to identify a damaged pin 210 .
  • the control unit 150 compares the measured electrical scan data to a reference data (e.g., no continuity or no signal response) to identify the potential presence of the damaged pin 210 .
  • the control unit 150 may take various corrective actions.
  • the control unit 150 may inform the test unit 110 that the test socket 120 is suspect, and the test unit 110 will prevent any additional devices under test 170 from being loaded into the test socket 120 . This action will prevent other devices under test 170 from being damaged by trying to insert a pin from a subsequent device under test 170 into an occupied opening 200 in the test socket 120 . If the test unit 110 is equipped with multiple test sockets 120 , the remaining sockets may be employed for testing devices under test 170 without interruption.
  • Another potential corrective action that the control unit 150 may implement is to send an electronic message (e.g., email) to a tool operator or activate an alarm or status indicator identifying the potential damaged pin 210 .
  • Yet another action the control unit 150 may take is to send a scheduling request to a maintenance system (not shown) in the fabrication facility. The maintenance system may automatically take the test unit 110 out of service and/or schedule a maintenance activity to inspect and repair the suspected test socket 120 .
  • the control unit 150 may also take corrective actions with respect to the device or devices under test 170 tested since the previous successful scan.
  • the last device under test 170 tested may be designated a being potentially faulty.
  • all devices under test 170 processed between scans may be identified as being potentially faulty.
  • those inserted after the faulty device under test 170 may have bent or damaged pins of their own.
  • a simplified flow diagram of a method for determining the availability of a test socket is provided.
  • a test socket is scanned between insertions of devices under test to generate scan data.
  • the scan data is compared to reference data (e.g., reference image, intensity threshold, electrical threshold, etc.).
  • reference data e.g., reference image, intensity threshold, electrical threshold, etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
US11/738,541 2007-04-23 2007-04-23 Method and apparatus for identifying broken pins in a test socket Abandoned US20080258704A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US11/738,541 US20080258704A1 (en) 2007-04-23 2007-04-23 Method and apparatus for identifying broken pins in a test socket
PCT/US2008/004961 WO2008133833A1 (en) 2007-04-23 2008-04-17 Method and apparatus for identifying broken pins in a test socket
DE112008001088T DE112008001088T5 (de) 2007-04-23 2008-04-17 Verfahren und Vorrichtung zum Erkennen gebrochener Anschlussstifte in einem Testsockel
CN200880013102A CN101861524A (zh) 2007-04-23 2008-04-17 于测试插座中识别断裂管脚之方法及设备
JP2010506217A JP2010525365A (ja) 2007-04-23 2008-04-17 試験ソケット内で破損ピンを検出するための方法および装置
KR1020097022856A KR20100036222A (ko) 2007-04-23 2008-04-17 테스트 소켓에서 부서진 핀들을 식별하는 방법 및 장치
TW097114442A TW200903009A (en) 2007-04-23 2008-04-21 Method and apparatus for identifying broken pins in a test socket
GB0918661A GB2461454A (en) 2007-04-23 2009-10-26 Method and apparatus for identifying broken pins in a test socket
US12/946,386 US8040140B2 (en) 2007-04-23 2010-11-15 Method and apparatus for identifying broken pins in a test socket

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/738,541 US20080258704A1 (en) 2007-04-23 2007-04-23 Method and apparatus for identifying broken pins in a test socket

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/946,386 Division US8040140B2 (en) 2007-04-23 2010-11-15 Method and apparatus for identifying broken pins in a test socket

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US20080258704A1 true US20080258704A1 (en) 2008-10-23

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Family Applications (2)

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US11/738,541 Abandoned US20080258704A1 (en) 2007-04-23 2007-04-23 Method and apparatus for identifying broken pins in a test socket
US12/946,386 Expired - Fee Related US8040140B2 (en) 2007-04-23 2010-11-15 Method and apparatus for identifying broken pins in a test socket

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/946,386 Expired - Fee Related US8040140B2 (en) 2007-04-23 2010-11-15 Method and apparatus for identifying broken pins in a test socket

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US (2) US20080258704A1 (ja)
JP (1) JP2010525365A (ja)
KR (1) KR20100036222A (ja)
CN (1) CN101861524A (ja)
DE (1) DE112008001088T5 (ja)
GB (1) GB2461454A (ja)
TW (1) TW200903009A (ja)
WO (1) WO2008133833A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140245445A1 (en) * 2013-02-27 2014-08-28 International Business Machines Corporation Preventing Propagation Of Hardware Viruses In A Computing System
TWI497062B (zh) * 2013-12-05 2015-08-21 Inventec Corp 中央處理器腳座的光學檢測系統及其方法
US20160132383A1 (en) * 2014-11-11 2016-05-12 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Adjusting the Use of a Chip/Socket Having a Damaged Pin
CN115266743A (zh) * 2022-05-17 2022-11-01 江苏汤谷智能科技有限公司 一种无损检测下的芯片质量的评估系统及方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2973935A1 (fr) * 2011-04-11 2012-10-12 St Microelectronics Rousset Procede pour evaluer un processus de decoupe de wafer semi-conducteur
TWI443346B (zh) * 2012-09-14 2014-07-01 Chunghwa Telecom Co Ltd 電器設備識別系統及方法
CN106249001B (zh) * 2016-05-05 2019-06-14 苏州能讯高能半导体有限公司 一种测试板
CN109827970B (zh) * 2019-02-22 2022-06-10 英特尔产品(成都)有限公司 半导体芯片测试系统和方法
US11315652B1 (en) * 2020-11-19 2022-04-26 Winbond Electronics Corp. Semiconductor chip burn-in test with mutli-channel

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4219053A (en) * 1978-10-30 1980-08-26 Tyner Clifford A Method for handling dual in-line packages
US5006842A (en) * 1987-04-13 1991-04-09 The Foxboro Company Identity insert block for electronic modules
US5073708A (en) * 1989-09-11 1991-12-17 Shibuya Kogyo Co., Ltd. Apparatus for inspecting the presence of foreign matters
US5233191A (en) * 1990-04-02 1993-08-03 Hitachi, Ltd. Method and apparatus of inspecting foreign matters during mass production start-up and mass production line in semiconductor production process
US6445201B1 (en) * 1999-08-17 2002-09-03 Nec Machinery Corporation IC package testing device and method for testing IC package using the same
US6477602B1 (en) * 1998-06-08 2002-11-05 Hewlett-Packard Company Method and circuit for detecting the presence of a connector in a socket
US20050210352A1 (en) * 2001-12-04 2005-09-22 Michael Ricchetti Method and apparatus for embedded Built-In Self-Test (BIST) of electronic circuits and systems
US6961885B2 (en) * 2001-11-26 2005-11-01 Ati Technologies, Inc. System and method for testing video devices using a test fixture
US20060083419A1 (en) * 2004-10-18 2006-04-20 Michael Carbaugh Systems and methods for isolating parts
US7471819B2 (en) * 2002-11-28 2008-12-30 Advantest Corporation Position detecting apparatus, a position detecting method and an electronic component carrying apparatus
US20090127068A1 (en) * 2005-08-11 2009-05-21 Advantest Corporation Electronic device testing apparatus
US20090136118A1 (en) * 2005-04-11 2009-05-28 Advantest Corporation Electronic Device Handling Apparatus

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01229983A (ja) 1988-03-09 1989-09-13 Fujitsu Ltd プローブ方式
JPH09325172A (ja) 1996-06-05 1997-12-16 Fujitsu Ltd バーンインボード検査装置及びバーンインボード検査方法
JP3080595B2 (ja) * 1997-02-28 2000-08-28 日本電産リード株式会社 基板検査装置および基板検査方法
US6046803A (en) * 1997-05-20 2000-04-04 Hewlett-Packard Company Two and a half dimension inspection system
TW465060B (en) * 1998-12-23 2001-11-21 Mirae Corp Wafer formed with CSP device and test socket of BGA device
US6386237B1 (en) * 1999-04-12 2002-05-14 The Goodyear Tire & Rubber Company Abrasive material transport hose with wear detecting sensors
US6746252B1 (en) * 2002-08-01 2004-06-08 Plastronics Socket Partners, L.P. High frequency compression mount receptacle with lineal contact members
JP4149395B2 (ja) 2004-03-11 2008-09-10 三井造船株式会社 粒子密度分布測定装置
US6824410B1 (en) * 2004-04-16 2004-11-30 Kingston Technology Corp. Zero-insertion-force hinged clam-shell socket for testing memory modules
US7123031B2 (en) * 2004-12-20 2006-10-17 Siemens Power Generation, Inc. System for on-line assessment of the condition of thermal coating on a turbine vane
KR100620740B1 (ko) * 2004-12-30 2006-09-13 동부일렉트로닉스 주식회사 패키지 검사용 어셈블리
US7791070B2 (en) * 2005-11-02 2010-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device fault detection system and method
US7701231B2 (en) * 2007-03-20 2010-04-20 Cummins Filtration Ip, Inc Apparatus, system, and method for detecting cracking within an aftertreatment device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4219053A (en) * 1978-10-30 1980-08-26 Tyner Clifford A Method for handling dual in-line packages
US5006842A (en) * 1987-04-13 1991-04-09 The Foxboro Company Identity insert block for electronic modules
US5073708A (en) * 1989-09-11 1991-12-17 Shibuya Kogyo Co., Ltd. Apparatus for inspecting the presence of foreign matters
US5233191A (en) * 1990-04-02 1993-08-03 Hitachi, Ltd. Method and apparatus of inspecting foreign matters during mass production start-up and mass production line in semiconductor production process
US6477602B1 (en) * 1998-06-08 2002-11-05 Hewlett-Packard Company Method and circuit for detecting the presence of a connector in a socket
US6445201B1 (en) * 1999-08-17 2002-09-03 Nec Machinery Corporation IC package testing device and method for testing IC package using the same
US6961885B2 (en) * 2001-11-26 2005-11-01 Ati Technologies, Inc. System and method for testing video devices using a test fixture
US20050210352A1 (en) * 2001-12-04 2005-09-22 Michael Ricchetti Method and apparatus for embedded Built-In Self-Test (BIST) of electronic circuits and systems
US7471819B2 (en) * 2002-11-28 2008-12-30 Advantest Corporation Position detecting apparatus, a position detecting method and an electronic component carrying apparatus
US20060083419A1 (en) * 2004-10-18 2006-04-20 Michael Carbaugh Systems and methods for isolating parts
US20090136118A1 (en) * 2005-04-11 2009-05-28 Advantest Corporation Electronic Device Handling Apparatus
US20090127068A1 (en) * 2005-08-11 2009-05-21 Advantest Corporation Electronic device testing apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140245445A1 (en) * 2013-02-27 2014-08-28 International Business Machines Corporation Preventing Propagation Of Hardware Viruses In A Computing System
US9251346B2 (en) * 2013-02-27 2016-02-02 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Preventing propagation of hardware viruses in a computing system
TWI497062B (zh) * 2013-12-05 2015-08-21 Inventec Corp 中央處理器腳座的光學檢測系統及其方法
US20160132383A1 (en) * 2014-11-11 2016-05-12 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Adjusting the Use of a Chip/Socket Having a Damaged Pin
US9703623B2 (en) * 2014-11-11 2017-07-11 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Adjusting the use of a chip/socket having a damaged pin
CN115266743A (zh) * 2022-05-17 2022-11-01 江苏汤谷智能科技有限公司 一种无损检测下的芯片质量的评估系统及方法

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US8040140B2 (en) 2011-10-18
US20110057666A1 (en) 2011-03-10
KR20100036222A (ko) 2010-04-07
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GB0918661D0 (en) 2009-12-09
TW200903009A (en) 2009-01-16

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