US20080164537A1 - Integrated complementary low voltage rf-ldmos - Google Patents

Integrated complementary low voltage rf-ldmos Download PDF

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US20080164537A1
US20080164537A1 US11/619,828 US61982807A US2008164537A1 US 20080164537 A1 US20080164537 A1 US 20080164537A1 US 61982807 A US61982807 A US 61982807A US 2008164537 A1 US2008164537 A1 US 2008164537A1
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conductivity type
set forth
region
gate electrode
buffer
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Jun Cai
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Semiconductor Components Industries LLC
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Fairchild Semiconductor Corp
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Priority to US11/619,828 priority Critical patent/US20080164537A1/en
Priority to DE112007003167T priority patent/DE112007003167T5/de
Priority to CNA2007800489213A priority patent/CN101573799A/zh
Priority to PCT/US2007/089203 priority patent/WO2008085795A1/en
Priority to TW097100448A priority patent/TW200837949A/zh
Publication of US20080164537A1 publication Critical patent/US20080164537A1/en
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION reassignment FAIRCHILD SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAI, JUN
Priority to US12/553,464 priority patent/US7888735B2/en
Priority to US13/005,593 priority patent/US8324042B2/en
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAIRCHILD SEMICONDUCTOR CORPORATION
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Definitions

  • This invention relates to power MOSFETs, and more particularly, to low power lateral complementary power MOSFETs.
  • LDMOS lateral double diffused MOSFET
  • LDMOS transistors know in the art usually use a drift region to provide the relatively high breakdown voltages required of these devices.
  • drift regions increase device resistance and take up space on a semiconductor chip thus requiring a significantly larger chip area than needed for convention MOSFETs.
  • the invention comprises, in one form thereof, a lateral double diffused metal oxide semiconductor (LDMOS) transistor comprising a gate oxide having a plurality of thicknesses under a gate electrode, a lateral spacer of a second conductivity type lying between a first edge of the gate electrode and a source tap region of a first conductivity type, the second conductivity type being opposite to the first conductivity type, and a drain region of the second conductivity type having a at least one buffer region which at least partially surrounds the drain region and which extends under a second edge of the gate electrode.
  • LDMOS lateral double diffused metal oxide semiconductor
  • the invention includes a method for making a LDMOS transistor.
  • the method comprises the steps of growing an epi layer on a substrate, forming a gate electrode on a split gate oxide formed on the epi layer, forming a body of a first conductivity type using a first side of the gate electrode as a mask, forming a shallow source spacer region of a second conductivity type using the first edge of the gate electrode as a mask, the second conductivity type being opposite to the first conductivity type, forming at least one buffer layer of the second conductivity type using a second edge of the gate electrode as a mask, forming first and second side wall oxides on the first and second edges, respectively, of the gate electrode, and forming a source tap layer of the first conductivity type using the first side wall oxide as a mask such that the source tap layer and the body overlap in a region spaced away from the first edge of the gate electrode, the source spacer region extending from the source tap layer to at least the first edge of the gate electrode.
  • FIG. 1A is a diagrammatic view of an n channel integrated low voltage RF-LDMOS transistor according to an embodiment of the present invention
  • FIG. 1B is a diagrammatic view of a complementary p channel version of the integrated low voltage RF-LDMOS transistor shown in FIG. 1A ;
  • FIG. 2A is a diagrammatic view of an early stage in the fabrication of the transistor shown in FIG. 1A ;
  • FIG. 2B is a diagrammatic view of an early stage in the fabrication of the transistor shown in FIG. 1B ;
  • FIG. 3A is a diagrammatic view of al intermediate stage in the fabrication of the transistor shown in FIG. 1A ;
  • FIG, 3 B is a diagrammatic view of an intermediate stage in the fabrication of the transistor shown in FIG. 1B ;
  • FIG. 4A is a diagrammatic view of a later intermediate stage in the fabrication of the transistor shown in FIG. 1A ;
  • FIG. 4B is a diagrammatic view of a later intermediate stage in the fabrication of the transistor shown in FIG. 1B ;
  • FIG. 5A is a diagrammatic view of an n channel integrated low voltage RF-LDMOS transistor according to another embodiment of the present invention.
  • FIG. 5B is a diagrammatic view of a complementary p channel version of the integrated low voltage RF-LDMOS transistor shown in FIG. 5A ;
  • FIG. 6A is a diagrammatic view of an n channel integrated low voltage RF-LDMOS transistor according to yet another embodiment of the present invention.
  • FIG. 6B is a diagrammatic view of a complementary p channel version of the integrated low voltage R(F-LDMOS transistor shown in FIG. 6A ;
  • FIG. 7A is a diagrammatic view of an n channel integrated low voltage RF-LDMOS transistor according to still another embodiment of the present invention.
  • FIG. 7B is a diagrammatic view of a complementary p channel version of the integrated low voltage RF-LDMOS transistor shown in FIG. 7A ;
  • FIG. 8A is a graph of the drain characteristics versus drain voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.35 micron;
  • FIG. 8B is a graph of the drain characteristics versus drain voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.50 micron,
  • FIG. 5C is a graph of the drain characteristics versus drain voltage simulation of a prior art transistor
  • FIG. 9A is a graph of the frequency transition versus gate voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.35 micron;
  • FIG. 9B is a graph of the frequency transition versus gate voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.50 micron;
  • FIG. 9C is a graph of the frequency transition versus gate voltage simulation of a prior art transistor
  • FIG. 10A is a graph of the transconductance versus gate voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.35 micron;
  • FIG. 10B is a graph of the transconductance versus gate voltage simulation of the transistor shown in FIG. 1A with a gate length of 0.50 micron;
  • FIG. 10C is a graph of the transconductance versus gate voltage simulation of a prior art transistor.
  • FIG. 1A is a diagrammatic view of an n channel integrated complementary low voltage RF-LDMOS transistor 10 according to an embodiment of the present invention.
  • the transistor 10 has a source connection 12 , a gate connection 14 , and a drain connection 16 .
  • the gate connection 14 is electrically connected to a gate suicide 18 formed in a gate polysilicon 20 .
  • the gate polysilicon 20 has a stepped bottom layer lying over a split gate oxide 22 with a thin section 24 of length 26 , and a thick section 28 of length 30 .
  • a sidewall oxide 32 is shown on the left side of the gate silicide 18 , the gate polysilicon 20 , and the thin section 24 of the split gate oxide 22 .
  • a sidewall oxide 34 is shown on the right side of the gate polysilicon 20 and the thick section 28 of the split gate oxide 22 .
  • the source connection 12 is electrically connected to a source silicide 36 under which is a source P+ tap 38 .
  • a shallow and short N+ source spacer 40 extends laterally from the right edge of the source silicide 36 and top right of the P+ tap 38 to slightly under the left side of the gate polysilicon 20 .
  • the length of the N+ source spacer 40 in one embodiment of the invention is approximately 0.08 microns, and can be between 0.04 and 0.3 microns.
  • a P body 42 extends from the approximately the bottom center of the P+ tap 38 to the substrate surface 44 and lies under most of the thin section 24 of the split gate oxide 22 .
  • a P ⁇ well 46 extends from the top of an optional P ⁇ buried layer 48 from approximately the downward projection of the middle of the bottom of the P+ tap 38 to the bottom of the P body 42 at a point approximately below the left edge of the gate polysilicon 20 .
  • the drain connection 16 is electrically connected to a drain silicide 50 .
  • a N+ drain 52 lies under and extends to the left of the drain silicide 50 .
  • the left end of the N ⁇ drain is spaced laterally apart from the gate polysilicon 20 .
  • a N buffer layer 54 lies under the N+ drain 52 and extends latterly to about the middle of the thick section 28 of the split gate oxide 22 .
  • a N ⁇ buffer layer 56 lies under the N buffer layer 54 and extends to under all of the thick section 28 of the split gate oxide 22 near the transition of the thin section 24 to the thick section 28 of the split gate oxide 22 .
  • the source silicide 36 and the drain silicide 50 , and the doped regions described above all lie in an epi layer 58 which in turn is atop a P+ substrate 60 .
  • the RF-LDMOS transistor 10 has a minimum device geometry for power LDMOS transistors and is made by utilizing self-aligned architecture design for high speed requirements.
  • the self-aligned architecture will be explained in more detail below with reference to FIGS. 2A through 4B .
  • the transistor 10 has a zero drift length which helps to minimize the device geometry.
  • the transistor 10 has several characteristics arising from the geometry of the device which provide important operating parameters.
  • the shallow N+ source spacer 40 with the P body 42 underneath and the P+ tap provide a large Safe Operating Area (SOA), a small input capacitance, and little junction leakage (which is important in battery powered hand-held applications).
  • SOA Safe Operating Area
  • the combination of the P body 42 , the P ⁇ well 46 , the P ⁇ buried layer 48 , and the P+ substrate 60 provide reduced substrate self-heating which minimizes the substrate loss.
  • the split gate oxide 22 provides a lessened Miller feedback capacitance since the gate-drain overlap is located at the thick section 28 of the split gate oxide 22 thereby lowering the Crss.
  • the split gate oxide also provides a large transconductance and lower Vt since the effective channel is located at the thin oxide section 24 having all effective channel length shorter that the width of the gate polysilicon 20 .
  • the thick gate oxide section 28 on the drain side lowers the E-field to thereby increase the breakdown voltage of the transistor 10 .
  • the N buffer layer 54 and the N ⁇ buffer layer 56 step drain buffers together with the P ⁇ epi provide a large depletion width which lowers the drain to source capacitance C ds .
  • the step drain buffers lessen the degradation of R on , g m and I Dsat since the N ⁇ buffer layer 56 with significant overlap with the thick gate oxide section 28 allows the channel electrons to spread out deep away from the gate oxide 22 resulting in fewer filled traps in the gate oxide 22 .
  • the lessening of the degradation of R on , g m and I Dsat therefore increases the reliability of the transistor 10 .
  • the zero drift length combined with the relatively highly doped N buffer layer 54 , which extends underneath the sidewall spacer 34 , provides a low R on and low conduction loss.
  • FIG. 1B is a diagrammatic view of a complementary p channel version 70 of the integrated low voltage RF-LDMOS transistor shown in FIG. 1A .
  • Transistor 70 has a source connection 72 , a gate connection 74 , and a drain connection 76 .
  • the gate connection 74 is electrically connected to a gate silicide 78 formed in a gate polysilicon 80 .
  • the gate polysilicon 80 has a stepped bottom layer lying over a split gate oxide 82 with a thin section 84 and a thick section 88 .
  • a sidewall oxide 92 is shown on the left side of the gate silicide 78 , the gate polysilicon 80 , and the thin section 84 of the split gate oxide 82 .
  • a sidewall oxide 94 is shown on the right side of the gate polysilicon 80 and the thick section 88 of the split gate oxide 82 .
  • the source connection 72 is electrically connected to a source silicide 96 under which is a source N+ tap 98 , a shallow and short P+ source spacer 100 extends laterally from the right edge of the source silicide 96 and top right of the N+ tap 98 to slightly under the left side of the gate polysilicon 80 .
  • a N body 102 extends from the approximately the bottom center of the N+ tap 88 to the substrate surface 104 and lies under most of the thin section 84 of the split gate oxide 82 .
  • a N ⁇ well 106 extends from the top of an optional N ⁇ buried layer 108 from approximately the downward projection of the middle of the bottom of the N+ tap 98 to the bottom of the N body 102 at a point approximately below the left edge of the gate polysilicon 80 .
  • the drain connection 76 is electrically connected to a drain silicide 110 .
  • a P+ drain 112 lies under and extends to the left of the drain silicide 110 . The left end of the P+ drain is spaced laterally apart from the gate polysilicon 80 .
  • a P buffer layer 114 lies under the P+ drain 112 and extends latterly to about the middle of the thick section 88 of the split gate oxide 82 .
  • a P ⁇ buffer layer 116 lies under the P buffer layer 114 and extends latterly to under all of the thick section 88 of the split gate oxide 82 near the transition of the thin section 84 to the thick section 88 of the split gate oxide 82 .
  • the source silicide 96 and the drain silicide 10 , and the doped regions described above all lie in a high voltage N ⁇ well 18 which in turn is partially atop the N ⁇ buried layer 108 , which are in turn atop a P ⁇ epi 120 which is atop a P+ substrate 122 .
  • the characteristics described above for the N channel transistor 10 also apply to the P channel transistor 70 .
  • FIGS. 2A and 2B are diagrammatic views of an early stage in the fabrication of the transistors 10 and 70 , respectively.
  • a starting P ⁇ epi 130 is formed on the P+ substrate 60 .
  • a P ⁇ buried layer 132 is formed in the P ⁇ epi 130 .
  • the starting P ⁇ epi 120 is formed on the P+ substrate 122 , and a buried layer 134 is formed in the P ⁇ epi 120 .
  • FIGS. 3A and 3B are diagrammatic views of an intermediate stage in the fabrication of the transistors 10 and 70 , respectively.
  • an additional in-line P ⁇ epi is grown on the P ⁇ buried layer 132 and P ⁇ epi 130 of FIG. 2A to form the P ⁇ epi 58 shown in FIG. 1A .
  • the P ⁇ well 46 is implanted.
  • the P-buried layer 132 of FIG. 2A diffuses upward to form the P ⁇ buried layer 48
  • the P-well 46 diffuses downwardly and laterally.
  • the split gate oxide 22 is formed on the top of the P ⁇ epi 58 and the gate polysilicon 20 is placed across the junction of the thick gate oxide 28 and the thin gate oxide 24 .
  • FIG. 3A an additional in-line P ⁇ epi is grown on the P ⁇ buried layer 132 and P ⁇ epi 130 of FIG. 2A to form the P ⁇ epi 58 shown in FIG. 1A .
  • the P ⁇ well 46 is implanted.
  • the P-buried layer 132 of FIG. 2A diffuses
  • the high voltage N ⁇ well 118 is implanted and diffused in an additional in-line P ⁇ epi 118 .
  • the N ⁇ well 106 is formed in the same manner as the P ⁇ well 46 shown in FIG, 3 A.
  • the N ⁇ buried layer 134 is diffused upward to form the N ⁇ buried layer 108 , and the N ⁇ well 106 diffuses downwardly and laterally at the same time.
  • the split gate oxide 82 and the gate polysilicon 80 are formed in the same manner as in the n channel transistor shown in FIG. 3A .
  • FIGS. 4A and 4B are diagrammatic views of a later intermediate stage in the fabrication of the transistors 10 and 70 , respectively.
  • the P body 42 and the N+ source spacer 40 are implanted using the same mask and are self-aligned to the left side of the gate polysilicon 20 .
  • the step drain buffers consisting of the N ⁇ buffer layer 56 and the N buffer layer 52 are implanted using the same mask and are self-aligned to the right side of the gate polysilicon 20 .
  • the same operations are performed for the p channel transistor shown in FIG. 4B with complementary dopant types, After bodies 42 , 102 and source spacers 40 , 100 are formed, the sidewall oxide 32 , 34 , 92 , and 94 are made using a standard oxide spacer process.
  • the transistor 10 shown in FIG. 1A is completed by implanting the P+ body tap 38 , which is self-aligned to the left side wall oxide, forming the source silicide 36 using the left side wall oxide 32 as a mask, implanting the N+ drain 52 , which is self-aligned to the right side wall oxide, and forming the drain silicide 50 using the right side wall oxide 34 as a mask.
  • the transistor 70 show in FIG. 1B is completed in the same manner using complementary dopant types.
  • FIGS. 5A and 5B are diagrammatic views of integrated low voltage RF-LDMOS transistors 130 and 132 , respectively, according to another embodiment of the present invention.
  • Transistor I 30 is transistor 10 with an enlarged N buffer layer 135 instead of the N buffer layer 54 , and a P ⁇ buffer layer 136 instead of the N ⁇ buffer layer 56 ; and transistor 132 is transistor 70 with an enlarged P buffer layer 137 instead of the P buffer layer 114 , and a N ⁇ buffer layer 138 instead of the P ⁇ buffer layer 116 .
  • the N buffer 132 extends latterly to under the thick section 28 of the split gate oxide 22 near the transition of the thin section 24 to the thick section 28 of the split gate oxide 22
  • the P ⁇ buffer 134 extends latterly and deeply under all of the thick section 28 and part of the thin section 24 to overlap the P body 42 .
  • the transistor 132 shown in FIG. 5B is formed in the same manner using complementary dopant types. The change from N ⁇ buffer to P ⁇ buffer in transistor 130 or from P ⁇ buffer to N ⁇ buffer in transistor 132 is to increase the device drain to source punch-through voltage which can be a problem with very short channel devices.
  • FIGS. 6A and 6B are diagrammatic views of integrated low voltage RF-LDMOS transistors 140 and 142 , respectively, according to yet another embodiment of the present invention.
  • Transistor 140 is transistor 10 without the N buffer layer 54
  • transistor 142 is transistor 70 without the P buffer layer 114 .
  • the removal of these layers 54 , 114 allows a higher voltage rating for transistors shown in FIGS. 6A and 6B compared with the transistors shown in FIGS. 1A and 1B .
  • FIGS. 7A and 7B are diagrammatic views of integrated low voltage RF-LDMOS transistors 150 and 152 , respectively, according to still another embodiment of the present invention in which the transistors 150 and 152 are surrounded by N isolation rings for isolated architectures.
  • an N ring 154 has an isolation connection 156 .
  • the N ring 154 is connected by an N bridge 158 to a N ⁇ buried layer 160 which extends across the width of the transistor 150 .
  • a P ⁇ buried layer 162 which also extends across the width of the transistor 50 , sits on top of the N ⁇ buried layer 160 .
  • an N ring 164 has an isolation connection 166 .
  • the N ring 164 is connected by an N bridge 168 to a N ⁇ buried layer 170 which extends across the width of the transistor 152 .
  • a P ⁇ buried layer 172 is built atop the N ⁇ buried layer 170 and connected to the P ⁇ well 46 as indicated schematically by connection 174 from the N ⁇ buried layer 172 to the source connection 72 which, in turn, provides a connection through the source silicide 96 , and the source N+ tap 98 to the N ⁇ well 106 .
  • FIGS. 8A-10C show 2-D simulated Si level operational characteristics of the transistor 10 and a prior art power NMOS transistor.
  • FIGS. 8A , 9 A, and 10 A are simulations of transistor 10 with a thin gate width 26 of 0.20 ⁇ m.
  • FIGS. 8B , 9 B, and 10 B are simulations of transistor 10 with a thin gate width 26 of 0.35 ⁇ m. The simulations which generated the A and B graphs were for the same thick gate width 30 of approximately 0.15 ⁇ m.
  • FIGS. 8C , 9 C, and 10 C are simulations of the prior art power NMOS transistor.
  • FIGS. 8A , 8 B, and 8 C show the calculated drain characteristics for the respective transistors using a 2-D model.
  • transistor 10 with a 0.35 ⁇ m gate poly length has higher drain current densities than the 0.50 ⁇ m gate poly length transistor 10 , which, in turn has higher drain current densities than the prior art lateral transistor.
  • FIGS. 9A , 9 B, and 9 C show the calculated frequency transitions (Ft) for the respective transistors.
  • the peak Ft in FIG. 9A is 67 GHz, while the peak Ft in FIG. 9B is 36 GHz, and the peak Ft in FIG. 9C is 23 GHz.
  • FIGS. 10A , 10 B, and 10 C are the calculated transconductance Gm for the respective transistors.
  • the peak Gm in FIG. 10A is 3 ⁇ 10 ⁇ 4 siemens, while the peak Gm in FIG. 10B is 2.5 ⁇ 10 ⁇ 4 siemens, and the peak Gm in FIG. 10C is 1.3 ⁇ 10 ⁇ 4 siemens.

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US11/619,828 US20080164537A1 (en) 2007-01-04 2007-01-04 Integrated complementary low voltage rf-ldmos
DE112007003167T DE112007003167T5 (de) 2007-01-04 2007-12-31 Integriertes komplementäres Niederspannungs-HF-LDMOS
CNA2007800489213A CN101573799A (zh) 2007-01-04 2007-12-31 集成互补低电压射频横向双扩散金属氧化物半导体
PCT/US2007/089203 WO2008085795A1 (en) 2007-01-04 2007-12-31 Integrated complementary low voltage rf-ldmos
TW097100448A TW200837949A (en) 2007-01-04 2008-01-04 Integrated complementary low voltage RF-LDMOS
US12/553,464 US7888735B2 (en) 2004-07-15 2009-09-03 Integrated complementary low voltage RF-LDMOS
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Publication number Priority date Publication date Assignee Title
US20080246080A1 (en) * 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
US20100295125A1 (en) * 2009-05-22 2010-11-25 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
US20110057271A1 (en) * 2006-07-28 2011-03-10 Broadcom Corporation Semiconductor Device with Increased Breakdown Voltage
US20120018804A1 (en) * 2010-07-23 2012-01-26 Khemka Vishnu K Guard Ring Integrated LDMOS
CN102412153A (zh) * 2010-09-26 2012-04-11 上海华虹Nec电子有限公司 降低射频ldmos器件中栅电阻的方法
US8274114B2 (en) 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
US20140231917A1 (en) * 2012-12-06 2014-08-21 Institute of Microelectronics, Chinese Academy of Sciences Finfet and method for manufacturing the same
US20150001637A1 (en) * 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric and method of making the same
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US9123807B2 (en) 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
WO2015134909A1 (en) * 2014-03-06 2015-09-11 Texas Instruments Incorporated Ldmos transistor and method of forming the ldmos transistor with improved rds*cgd
US20160027899A1 (en) * 2014-07-24 2016-01-28 Dongbu Hitek Co., Ltd. Semiconductor Device and Method of Manufacturing the Same
US20170018622A1 (en) * 2015-07-17 2017-01-19 Broadcom Corporation UTBB FDSOI Split Gate Devices
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US20170243971A1 (en) * 2016-02-18 2017-08-24 Kabushiki Kaisha Toshiba Semiconductor device
US20170250259A1 (en) * 2016-02-25 2017-08-31 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device
US20170294431A1 (en) * 2015-03-13 2017-10-12 Magnachip Semiconductor, Ltd. Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip
US20220130964A1 (en) * 2020-10-28 2022-04-28 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US11322611B2 (en) * 2019-11-06 2022-05-03 Silicet, LLC Methods for LDMOS and other MOS transistors with hybrid contact
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source
US11658481B1 (en) 2019-05-30 2023-05-23 Amplexia, Llc Source and drain enabled conduction triggers and immunity tolerance for integrated circuits

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101175228B1 (ko) * 2009-12-04 2012-08-21 매그나칩 반도체 유한회사 반도체 장치
US20110241112A1 (en) * 2010-03-31 2011-10-06 Zuniga Marco A LDMOS Device with P-Body for Reduced Capacitance
US8357579B2 (en) * 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
TWI449176B (zh) * 2010-12-10 2014-08-11 Macronix Int Co Ltd 具有分離閘極和超級連接結構之半導體元件
US20120319202A1 (en) * 2011-06-15 2012-12-20 Richtek Technology Corporation, R.O. C. High Voltage Device and Manufacturing Method Thereof
KR101228369B1 (ko) * 2011-10-13 2013-02-01 주식회사 동부하이텍 Ｌｄｍｏｓ 소자와 그 제조 방법
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CN106206735B (zh) * 2016-07-19 2019-12-10 上海华虹宏力半导体制造有限公司 Mosfet及其制造方法
US20180138307A1 (en) * 2016-11-17 2018-05-17 Globalfoundries Inc. Tunnel finfet with self-aligned gate
CN107275333B (zh) * 2017-06-30 2020-04-10 上海华虹宏力半导体制造有限公司 Sonos非挥发性存储器工艺中的dmos器件及制造方法
US10529804B2 (en) 2017-08-21 2020-01-07 Texas Instruments Incorporated Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method
US10608108B2 (en) * 2018-06-20 2020-03-31 Globalfoundries Singapore Pte. Ltd. Extended drain MOSFETs (EDMOS)
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US11114140B1 (en) 2020-04-23 2021-09-07 HeFeChip Corporation Limited One time programmable (OTP) bits for physically unclonable functions
US11437082B2 (en) 2020-05-17 2022-09-06 HeFeChip Corporation Limited Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage
US11482543B2 (en) 2020-05-29 2022-10-25 metaMOS Solutions Inc. Radio frequency (RF) amplifier device on silicon-on-insulator (SOI) and method for fabricating thereof
US11502193B2 (en) 2020-09-14 2022-11-15 Globalfoundries Singapore Pte. Ltd. Extended-drain metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer
CN112216745B (zh) * 2020-12-10 2021-03-09 北京芯可鉴科技有限公司 高压非对称结构ldmos器件及其制备方法
TWI818371B (zh) * 2021-01-12 2023-10-11 立錡科技股份有限公司 高壓元件及其製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994904A (en) * 1988-05-25 1991-02-19 Kabushiki Kaisha Toshiba MOSFET having drain voltage detection function
US5366915A (en) * 1992-08-28 1994-11-22 Nec Corporation Process of fabricating floating gate type field effect transistor having drain region gently varied in impurity profile
US6593621B2 (en) * 2001-08-23 2003-07-15 Micrel, Inc. LDMOS field effect transistor with improved ruggedness in narrow curved areas
US6888205B2 (en) * 2001-12-20 2005-05-03 Stmicroelectronics S.R.L. Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods
US7125777B2 (en) * 2004-07-15 2006-10-24 Fairchild Semiconductor Corporation Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5264719A (en) 1986-01-07 1993-11-23 Harris Corporation High voltage lateral semiconductor device
US5146298A (en) 1991-08-16 1992-09-08 Eklund Klas H Device which functions as a lateral double-diffused insulated gate field effect transistor or as a bipolar transistor
US5314834A (en) 1991-08-26 1994-05-24 Motorola, Inc. Field effect transistor having a gate dielectric with variable thickness
EP0537684B1 (en) * 1991-10-15 1998-05-20 Texas Instruments Incorporated Improved performance lateral double-diffused MOS transistor and method of fabrication thereof
JPH05283710A (ja) 1991-12-06 1993-10-29 Intel Corp 高電圧ｍｏｓトランジスタ及びその製造方法
DE69413960T2 (de) * 1994-07-18 1999-04-01 St Microelectronics Srl Nicht-flüchtiger EPROM und Flash-EEPROM-Speicher und Verfahren zu seiner Herstellung
US6372586B1 (en) 1995-10-04 2002-04-16 Texas Instruments Incorporated Method for LDMOS transistor with thick copper interconnect
US6700157B2 (en) 1996-01-22 2004-03-02 Fuji Electric Co., Ltd. Semiconductor device
US5741737A (en) 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
EP0880183A3 (en) 1997-05-23 1999-07-28 Texas Instruments Incorporated LDMOS power device
US6110783A (en) 1997-06-27 2000-08-29 Sun Microsystems, Inc. Method for forming a notched gate oxide asymmetric MOS device
US6307233B1 (en) 1998-07-31 2001-10-23 Texas Instruments Incorporated Electrically isolated double gated transistor
JP3473460B2 (ja) * 1998-11-20 2003-12-02 富士電機株式会社 横型半導体装置
US6441431B1 (en) * 1998-12-04 2002-08-27 Texas Instruments Incorporated Lateral double diffused metal oxide semiconductor device
DE19918943A1 (de) 1999-04-27 2000-11-02 Nexpress Solutions Llc Druckvorrichtung
US20020063263A1 (en) * 2000-11-30 2002-05-30 Scott David B. Metal oxide semiconductor transistor with self-aligned channel implant
US6365932B1 (en) * 1999-08-20 2002-04-02 Denso Corporation Power MOS transistor
US6168999B1 (en) 1999-09-07 2001-01-02 Advanced Micro Devices, Inc. Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain
US6297108B1 (en) 2000-03-10 2001-10-02 United Microelectronics Corp. Method of forming a high voltage MOS transistor on a semiconductor wafer
JP2002237591A (ja) * 2000-12-31 2002-08-23 Texas Instruments Inc Ｄｍｏｓトランジスタ・ソース構造とその製法
US6489203B2 (en) 2001-05-07 2002-12-03 Institute Of Microelectronics Stacked LDD high frequency LDMOSFET
US6620656B2 (en) 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device
US6504226B1 (en) 2001-12-20 2003-01-07 Stmicroelectronics, Inc. Thin-film transistor used as heating element for microreaction chamber
JP2003332578A (ja) 2002-05-09 2003-11-21 Sharp Corp 薄膜トランジスタ及びその製造方法並びにこれを用いた液晶表示装置
US6770935B2 (en) 2002-06-11 2004-08-03 Texas Instruments Incorporated Array of transistors with low voltage collector protection
KR100958421B1 (ko) * 2002-09-14 2010-05-18 페어차일드코리아반도체 주식회사 전력 소자 및 그 제조방법
US6717850B1 (en) 2002-12-05 2004-04-06 Advanced Micro Devices, Inc. Efficient method to detect process induced defects in the gate stack of flash memory devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994904A (en) * 1988-05-25 1991-02-19 Kabushiki Kaisha Toshiba MOSFET having drain voltage detection function
US5366915A (en) * 1992-08-28 1994-11-22 Nec Corporation Process of fabricating floating gate type field effect transistor having drain region gently varied in impurity profile
US6593621B2 (en) * 2001-08-23 2003-07-15 Micrel, Inc. LDMOS field effect transistor with improved ruggedness in narrow curved areas
US6888205B2 (en) * 2001-12-20 2005-05-03 Stmicroelectronics S.R.L. Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods
US7125777B2 (en) * 2004-07-15 2006-10-24 Fairchild Semiconductor Corporation Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110057271A1 (en) * 2006-07-28 2011-03-10 Broadcom Corporation Semiconductor Device with Increased Breakdown Voltage
US20080246080A1 (en) * 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
US8598670B2 (en) 2006-07-28 2013-12-03 Broadcom Corporation Semiconductor device with increased breakdown voltage
US20100295125A1 (en) * 2009-05-22 2010-11-25 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
US8203188B2 (en) * 2009-05-22 2012-06-19 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
US8274114B2 (en) 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
US8765544B2 (en) 2010-06-14 2014-07-01 Broadcom Corporation Fabrication of a semiconductor device having an enhanced well region
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
US20120018804A1 (en) * 2010-07-23 2012-01-26 Khemka Vishnu K Guard Ring Integrated LDMOS
US8278710B2 (en) * 2010-07-23 2012-10-02 Freescale Semiconductor, Inc. Guard ring integrated LDMOS
CN102412153A (zh) * 2010-09-26 2012-04-11 上海华虹Nec电子有限公司 降低射频ldmos器件中栅电阻的方法
US9123807B2 (en) 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
US20140231917A1 (en) * 2012-12-06 2014-08-21 Institute of Microelectronics, Chinese Academy of Sciences Finfet and method for manufacturing the same
US9142677B2 (en) * 2012-12-06 2015-09-22 Institute of Microelectronics, Chinese Academy of Sciences FinFET having gate in place of sacrificial spacer source/drain mask
US20150001637A1 (en) * 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric and method of making the same
US11769812B2 (en) * 2013-06-27 2023-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple wells and method of making
US20210202708A1 (en) * 2013-06-27 2021-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple wells and method of making
US10957772B2 (en) 2013-06-27 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple wells
US9917168B2 (en) * 2013-06-27 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric
JP2017507502A (ja) * 2014-03-06 2017-03-16 日本テキサス・インスツルメンツ株式会社 Ｒｄｓ×ｃｇｄが改善されたｌｄｍｏｓトランジスタ、及びｒｄｓ×ｃｇｄが改善されたｌｄｍｏｓトランジスタを形成する方法
US10461156B2 (en) 2014-03-06 2019-10-29 Texas Instruments Incorporated LDMOS transistor and method of forming the LDMOS transistor with improved RDS*CGD
US11610968B2 (en) 2014-03-06 2023-03-21 Texas Instruments Incorporated LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd
WO2015134909A1 (en) * 2014-03-06 2015-09-11 Texas Instruments Incorporated Ldmos transistor and method of forming the ldmos transistor with improved rds*cgd
CN106030820A (zh) * 2014-03-06 2016-10-12 德州仪器公司 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法
US20160027899A1 (en) * 2014-07-24 2016-01-28 Dongbu Hitek Co., Ltd. Semiconductor Device and Method of Manufacturing the Same
CN106663699A (zh) * 2014-08-07 2017-05-10 德州仪器公司 用于具有经级联resurf植入部及双缓冲器的ldmos装置的方法及设备
EP3178116A4 (en) * 2014-08-07 2018-08-15 Texas Instruments Incorporated Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers
CN104465404A (zh) * 2014-12-24 2015-03-25 上海华虹宏力半导体制造有限公司 射频ldmos器件的制造方法
US10068892B2 (en) * 2015-03-13 2018-09-04 Magnachip Semiconductor, Ltd. Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip
US20170294431A1 (en) * 2015-03-13 2017-10-12 Magnachip Semiconductor, Ltd. Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip
US11043483B2 (en) 2015-03-13 2021-06-22 Magnachip Semiconductor, Ltd. Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip
US20170018622A1 (en) * 2015-07-17 2017-01-19 Broadcom Corporation UTBB FDSOI Split Gate Devices
US9978848B2 (en) * 2015-07-17 2018-05-22 Avago Technologies General Ip (Singapore) Pte. Ltd. UTBB FDSOI split gate devices
US20170243971A1 (en) * 2016-02-18 2017-08-24 Kabushiki Kaisha Toshiba Semiconductor device
US20190334001A1 (en) * 2016-02-25 2019-10-31 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device
US10388741B2 (en) * 2016-02-25 2019-08-20 Renesas Electronics Corporation Semiconductor device with arrangement of semiconductor regions for improving breakdown voltages
US20170250259A1 (en) * 2016-02-25 2017-08-31 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device
US11658481B1 (en) 2019-05-30 2023-05-23 Amplexia, Llc Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US11646371B2 (en) 2019-11-06 2023-05-09 Amplexia, Llc MOSFET transistors with hybrid contact
US11322611B2 (en) * 2019-11-06 2022-05-03 Silicet, LLC Methods for LDMOS and other MOS transistors with hybrid contact
US20220130964A1 (en) * 2020-10-28 2022-04-28 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US20230054381A1 (en) * 2020-12-04 2023-02-23 Amplexia, Llc Ldmos with self-aligned body and hybrid source
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source

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US7888735B2 (en) 2011-02-15
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WO2008085795A1 (en) 2008-07-17
CN101573799A (zh) 2009-11-04
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US20100013012A1 (en) 2010-01-21
US20110104861A1 (en) 2011-05-05

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