CN106030820A - 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 - Google Patents
具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 Download PDFInfo
- Publication number
- CN106030820A CN106030820A CN201580010177.2A CN201580010177A CN106030820A CN 106030820 A CN106030820 A CN 106030820A CN 201580010177 A CN201580010177 A CN 201580010177A CN 106030820 A CN106030820 A CN 106030820A
- Authority
- CN
- China
- Prior art keywords
- depth
- degree
- region
- dopant
- conducting material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 37
- 239000002019 doping agent Substances 0.000 claims abstract description 130
- 239000004065 semiconductor Substances 0.000 claims abstract description 79
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims description 8
- 239000003795 chemical substances by application Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 29
- 239000007800 oxidant agent Substances 0.000 description 27
- 230000001590 oxidative effect Effects 0.000 description 27
- 239000000758 substrate Substances 0.000 description 21
- 108091006146 Channels Proteins 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
在所描述实例中,通过以下方式来改进横向扩散金属氧化物半导体LDMOS晶体管(100)的Rds*Cgd优值FOM:形成在若干深度(D1/D2)处具有若干掺杂剂植入物的漏极漂移区域(112),及形成在若干深度(D3/D4/D5)处具有若干掺杂剂植入物的阶梯状背栅极区域(128)以毗连所述漏极漂移区域(112)。
Description
本发明一般来说涉及LDMOS晶体管,且更明确地说,涉及具有经改进Rds*Cgd的LDMOS晶体管及形成所述LDMOS晶体管的方法。
背景技术
金属氧化物半导体(MOS)晶体管是众所周知的半导体装置,其具有:源极;漏极;主体,其沟道区域位于源极与漏极之间且触及源极及漏极;及栅极,其位于沟道区域上方且通过栅极电介质层而与沟道区域隔离。MOS晶体管的两种类型为:NMOS晶体管,其具有拥有p型沟道区域的n+源极及漏极区域;及PMOS晶体管,其具有拥有n型沟道区域的p+源极及漏极区域。
在操作中,当源极及主体接地时,将正电压置于漏极上以设置漏极到源极电场,且将大于阈值电压的电压置于栅极上,从而使电流从漏极流到源极。当置栅极于上的电压小于阈值电压时,例如,当将栅极拉低到接地时,无电流流动。
当代MOS晶体管通常用于低电压环境(例如介于从1.2V到5V的范围内的环境)中。相比之下,高电压MOS晶体管是(举例来说)以介于10V到400V范围内的电压操作的晶体管。为处理较高电压,高电压MOS晶体管比低电压MOS晶体管大。
一种类型的高电压MOS晶体管已知为横向扩散MOS(LDMOS)晶体管。LDMOS晶体管是还具有漏极漂移区域的MOS晶体管。漏极漂移区域具有与漏极相同的导电类型,但具有比漏极低的掺杂剂浓度,所述漏极漂移区域触及漏极及沟道区域且位于漏极与沟道区域之间。在操作中,漏极漂移区域减小漏极到源极电场的量值。
高电流(例如,10A及10A以上)及高频率(1MHz到10MHz及10MHz以上)LDMOS晶体管的新优值(FOM)为Rds*Cgd,Rds*Cgd是漏极到源极电阻(Rds)与栅极到漏极电容(Cgd)的乘积。为改进此FOM,减小Rds值、Cgd值或所述值两者是合意的。
用以减小Cgd的一种方法是使用多个分离式栅极或阶梯式栅极来代替一个栅极。在至少一个实例中,对于阶梯式栅极或分离式栅极,使用一主栅极及两个逐渐变薄的栅极,因此当栅极位于较靠近于漏极区域时,下伏栅极电介质层变得较厚。然而,此方法的一个缺点是分离式栅极或阶梯式栅极是难以制作且造价昂贵的。此外,分离式栅极或阶梯式栅极可需要较长漏极漂移区域,较长漏极漂移区域因增加的Rds而使装置在高速移动应用中受限。
发明内容
在所描述实例中,一种LDMOS晶体管提供经改进Rds*Cgd。所述LDMOS晶体管包含半导体材料及位于所述半导体材料内的漏极漂移区域。所述漏极漂移区域具有第一导电类型、第一深度处的第一水平掺杂剂浓度峰值及第二深度处的第二水平掺杂剂浓度峰值。所述第一深度是从所述半导体材料的顶部表面向下测量的一距离。所述第二深度是从所述第一深度向下测量的一距离。所述LDMOS晶体管还包含位于所述半导体材料内以触及所述漏极漂移区域的背栅极区域。所述背栅极区域具有第二导电类型、第三深度处的第三水平掺杂剂浓度峰值、第四深度处的第四水平掺杂剂浓度峰值及第五深度处的第五水平掺杂剂浓度峰值。所述第三深度是从所述半导体材料的所述顶部表面向下测量的一距离。所述第四深度是从所述第三深度向下测量的一距离。所述第五深度是从所述第四深度向下测量的一距离。此外,所述LDMOS晶体管包含:栅极电介质层,其触及所述半导体材料的所述顶部表面;及栅极,其触及所述栅极电介质层且位于所述栅极电介质层上方在所述漏极漂移区域及所述背栅极区域正上方。
在一种形成提供经改进Rds*Cgd的LDMOS晶体管的方法中,所述方法包含在半导体材料内形成漏极漂移区域。所述漏极漂移区域具有第一导电类型、第一深度处的第一水平掺杂剂浓度峰值及第二深度处的第二水平掺杂剂浓度峰值。所述第一深度是从所述半导体材料的顶部表面向下测量的一距离。所述第二深度是从所述第一深度向下测量的一距离。所述方法还包含在半导体材料内形成背栅极区域以触及所述漏极漂移区域。所述背栅极区域具有第二导电类型、第三深度处的第三水平掺杂剂浓度峰值、第四深度处的第四水平掺杂剂浓度峰值及第五深度处的第五水平掺杂剂浓度峰值。所述第三深度是从所述半导体材料的所述顶部表面向下测量的一距离。所述第四深度是从所述第三深度向下测量的一距离。所述第五深度是从所述第四深度向下测量的一距离。所述方法进一步包含:形成触及所述半导体材料的所述顶部表面的栅极电介质层,及形成触及所述栅极电介质层且位于所述栅极电介质层上方在所述漏极漂移区域及所述背栅极区域正上方的栅极。
附图说明
图1是根据实例性实施例的LDMOS晶体管100的实例的横截面图。
图2A到2G是根据实例性实施例的形成LDMOS晶体管结构的方法200的实例的横截面图。
具体实施方式
图1展示根据实例性实施例的LDMOS晶体管100的实例的横截面图。如下文更详细描述,LDMOS晶体管100通过在漏极漂移区域及毗连的阶梯状背栅极区域两者中使用多种植入物而改进Rds*Cgd。
如图1中所展示,LDMOS晶体管100包含半导体材料110(例如衬底或外延层)及位于半导体材料110内的漏极漂移区域112。漏极漂移区域112具有第一导电类型及两个水平掺杂剂浓度峰值,所述两个水平掺杂剂浓度峰值为:深度D1处的第一峰值,深度D1是从半导体材料110的顶部表面114向下测量的一距离;及深度D2处的第二峰值,深度D2是从深度D1向下测量的一距离。在此实例中,漏极漂移区域112具有n导电类型。
深度D1界定漂移顶部区段120,漂移顶部区段120从半导体材料110的顶部表面114向下延伸到深度D1。漂移顶部区段120具有其中掺杂剂浓度随深度增加而增加的掺杂剂浓度分布曲线。在此实例中,漂移顶部区段120从半导体材料110的顶部表面114处的低掺杂剂浓度持续地增加到深度D1处的高掺杂剂浓度。此外,漂移顶部区段120内的最大掺杂剂浓度在深度D1处。
深度D1及深度D2界定漂移中间区段124,漂移中间区段124从深度D1向下延伸到深度D2。漂移中间区段124具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。
在此实例中,漂移中间区段124从深度D1处的高掺杂剂浓度持续地减小到深度D1与D2之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D2处的较高掺杂剂浓度。此外,漂移中间区段124内的两个最大掺杂剂浓度在深度D1及D2处。
深度D2还界定漂移底部区段126,漂移底部区段126从深度D2向下延伸一距离。漂移底部区段126具有其中掺杂剂浓度从深度D2处随深度增加而减小的掺杂剂浓度分布曲线。在此实例中,漂移底部区段126从深度D2处的高掺杂剂浓度持续地减小到较低掺杂剂浓度。此外,漂移底部区段126内的最大掺杂剂浓度在深度D2处。
如图1中进一步所展示,LDMOS晶体管100还包含位于半导体材料110内以触及漏极漂移区域112的背栅极区域128。背栅极区域128具有第二导电类型及阶梯形状,所述阶梯形状与相同导电类型的三个水平掺杂剂浓度峰值对应:深度D3处的峰值,深度D3是从半导体材料110的顶部表面114向下测量的一距离;深度D4处的峰值,深度D4是从深度D3向下测量的一距离;及深度D5处的峰值,深度D5是从深度D4向下测量的一距离。在此实例中,背栅极区域128具有p导电类型。
深度D3界定背栅极顶部区段130,背栅极顶部区段130从半导体材料110的顶部表面114向下延伸到深度D3。背栅极顶部区段130具有其中掺杂剂浓度随深度增加而增加的掺杂剂浓度分布曲线。在此实例中,背栅极顶部区段130从半导体材料110的顶部表面114处的低掺杂剂浓度持续地增加到深度D3处的高掺杂剂浓度。此外,背栅极顶部区段130内的最大掺杂剂浓度在深度D3处。
深度D3及D4还界定背栅极中间区段134,背栅极中间区段134从深度D3向下延伸到深度D4。背栅极中间区段134具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。
在此实例中,背栅极中间区段134从深度D3处的高掺杂剂浓度持续地减小到深度D3与D4之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D4处的较高掺杂剂浓度。此外,背栅极中间区段134内的两个最大掺杂剂浓度在深度D3及D4处。
深度D4及深度D5界定背栅极中间区段136,背栅极中间区段136从深度D4向下延伸到深度D5。背栅极中间区段136具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。
在此实例中,背栅极中间区段136从深度D4处的高掺杂剂浓度持续地减小到深度D4与D5之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D5处的较高掺杂剂浓度。此外,背栅极中间区段136内的两个最大掺杂剂浓度在深度D4及D5处。
深度D5进一步界定背栅极底部区段138,背栅极底部区段138从深度D5向下延伸一距离。背栅极底部区段138具有其中掺杂剂浓度从深度D5处随深度增加而减小的掺杂剂浓度分布曲线。在此实例中,背栅极底部区段138从深度D5处的高掺杂剂浓度持续地减小到较低掺杂剂浓度。如所展示,深度D3位于深度D1与深度D2之间。此外,深度D4位于深度D2以下。此外,背栅极区域128的背栅极中间区段136及背栅极底部区段138的一部分位于漏极漂移区域112正下方。
如图1中进一步所展示,LDMOS晶体管100包含位于半导体材料110内的一对浅沟槽隔离(STI)区域140。STI区域140具有位于深度D1以下的下部表面142。在此实例中,STI区域140还具有基本上与半导体材料110的顶部表面114位于相同平面中的顶部表面。
LDMOS晶体管100进一步包含各自位于半导体材料110内的漏极区域150、源极区域152及表面区域154。具有第一导电类型的漏极区域150位于STI区域140之间以触及漏极漂移区域112。漏极区域150具有基本上大于漏极漂移区域112的最高掺杂剂浓度的掺杂剂浓度。在此实例中,漏极区域150实施为n+区域。
也具有第一导电类型的源极区域152触及背栅极区域128。源极区域152具有基本上等于漏极区域150的掺杂剂浓度的掺杂剂浓度。在此实例中,源极区域152实施为n+区域。
进一步具有第一导电类型的表面区域154触及半导体材料110的顶部表面114、背栅极区域128及源极区域152,且位于背栅极区域128的一部分正上方。表面区域154具有基本上大于漏极漂移区域112的最高掺杂剂浓度的掺杂剂浓度。在此实例中,表面区域154实施为n+区域。(任选地可省略表面区域154。)
LDMOS晶体管100另外包含主体接触区域156,主体接触区域156位于半导体材料110内以触及背栅极区域128。主体接触区域156具有第二导电类型及基本上大于背栅极区域128的最高掺杂剂浓度的掺杂剂浓度。在此实例中,主体接触区域156实施为p+区域。
还如图1中所展示,LDMOS晶体管100包含:栅极电介质层160,其触及半导体材料110的顶部表面114;栅极162,其触及栅极电介质层160且位于栅极电介质层160上方;及侧壁间隔件164,其触及栅极162且横向环绕栅极162。背栅极区域128包含沟道区域166,沟道区域166位于漏极漂移区域112与源极区域152之间且触及漏极漂移区域112及源极区域152。栅极162又位于漏极漂移区域112及背栅极区域128的沟道区域166正上方。
在操作中,当源极区域152及主体接触区域156接地时,将正电压(例如16V)置于漏极区域150上以设置漏极到源极电场,且将大于阈值电压的电压置于栅极162上,从而使电流从漏极区域150流到源极区域152。当置于栅极162上的电压小于阈值电压时,例如当将栅极162拉低到接地时,无电流流动。
实例性实施例的若干优点中的一个优点是漂移顶部区段120在半导体材料110的顶部表面114处且直接在顶部表面114下方的区域具有随深度而增加的轻掺杂剂浓度。通过在半导体材料110的顶部表面114处且接近顶部表面114使用轻掺杂剂浓度区域,可减小栅极到漏极电容Cgd,此继而又改进Rds*Cgd。实例性实施例的另一优点是深度D1 及D2处的较高掺杂剂浓度减小漏极到源极电阻Rds,此进一步改进Rds*Cgd。
此外,由于在漂移顶部区段120及漂移中间区段124内存在较低掺杂剂浓度区域,因此漏极漂移区域112继续减小漏极到源极电场的量值。还通过使用漂移底部区段126与背栅极中间区段136之间的相互作用而实现漏极到源极电阻Rds对漏极到源极击穿电压(BV)的最佳折衷以平衡深度D2处的高掺杂剂浓度水平区域处的电荷。
实例性实施例的另一优点是深度D1处的位于栅极162下方的高掺杂剂浓度水平区域相对较大,此继而又减小沟道电阻及JFET电阻。JFET电阻是与邻近于沟道166的亚表面区域相关联的电阻,其中耗尽区域的宽度随漏极150及栅极162上的电压而变化。
此外,深度D1及D2处的高掺杂剂浓度水平区域处的表面易于被耗尽以减小Cgd。此外,在增大的漏极电压下,深度D3及D4处的高掺杂剂浓度水平区域的阶梯形状区可屏蔽深度D1及D2处的位于栅极162下方的高掺杂剂浓度水平区域处的增大电场。此现象与漏极漂移区域112与背栅极区域128之间的电荷平衡一起作用以增大装置漏极到源极击穿电压,或在目标装置漏极到源极击穿电压下,可减小漏极漂移区域112的长度(STI区域140的下部表面142下方的漂移区域)以减小Rds,此继而又改进总Rds*Cgd。因此,实例性实施例通过减小Rds值及Cgd值两者而改进Rds*Cgd。
图2A到2G展示根据实例性实施例的形成LDMOS晶体管结构的方法200的实例的一系列横截面图。方法200使用常规形成的半导体材料210,例如衬底或外延层。
方法200通过在半导体材料210内形成漏极漂移区域212而开始。漏极漂移区域212具有第一导电类型及两个水平掺杂剂浓度峰值:深度D1处的第一峰值,深度D1是从半导体材料210的顶部表面214向下测量的一距离;及深度D2处的第二峰值,深度D2是从深度D1向下测量的一距离。在此实例中,漏极漂移区域212经形成以具有n导电类型。
漏极漂移区域212可通过首先在半导体材料210上形成经图案化光致抗蚀剂层216而形成。经图案化光致抗蚀剂层216是以常规方式形成的,所述常规方式包含:沉积光致抗蚀剂层、穿过已知为掩模的经图案化黑色/透明玻璃板而投射光以在光致抗蚀剂层上形成经图案化图像及移除经成像光致抗蚀剂区域,所述经成像光致抗蚀剂区域因暴露于光而被软化。
在已形成经图案化光致抗蚀剂层216之后,经由经图案化光致抗蚀剂层216而将掺杂剂植入到半导体材料210中以形成上部区域220。上部区域220在深度D1处具有水平掺杂剂浓度峰值。在此实例中,植入砷以形成n型上部区域220。砷掺杂剂可经植入具有(举例来说)4×1012到8×1012的剂量及200keV到350keV的能量。
在经图案化光致抗蚀剂层216仍在原处的情况下,再次经由经图案化光致抗蚀剂层216将掺杂剂植入到半导体材料210中,这次将形成下部区域222。下部区域222在深度D2处具有水平掺杂剂浓度峰值。在此实例中,植入磷以形成n型下部区域222。磷掺杂剂可经植入具有(举例来说)8×1012到2×1013的剂量及100keV到400keV的能量。
在已形成下部区域222之后,以常规方式(例如,运用灰化工艺)移除经图案化光致抗蚀剂层216。在此之后,热驱动工艺使掺杂剂扩散并激活掺杂剂以完成漏极漂移区域212的形成。热驱动工艺可包含长达90分钟的1100℃热处理或等效条件的热处理,举例来说,长达50分钟的1125℃热处理、或长达270分钟的1050℃热处理。
深度D1界定漂移顶部区段224,漂移顶部区段224从半导体材料210的顶部表面214向下延伸到深度D1。漂移顶部区段224的部分在热驱动工艺期间被掺杂,热驱动工艺致使掺杂剂从上部区域220向上外扩到漂移顶部区段224中。
漂移顶部区段224具有其中掺杂剂浓度随深度增加而增加的掺杂剂浓度分布曲线。在此实例中,漂移顶部区段224从半导体材料210的顶部表面214处的低掺杂剂浓度持续地增加到深度D1处的高掺杂剂浓度。此外,漂移顶部区段224内的最大掺杂剂浓度在深度D1处。
深度D1及深度D2界定漂移中间区段226,漂移中间区段226从深度D1向下延伸到深度D2。漂移中间区段226的部分在热驱动工艺期间被掺杂,热驱动工艺致使掺杂剂从上部区域220向下外扩到漂移中间区段226中及从下部区域222的部分向上外扩到漂移中间区段226中。
漂移中间区段226具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。在此实例中,漂移中间区段226从深度D1处的高掺杂剂浓度持续地减小到深度D1与D2之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D2处的较高掺杂剂浓度。此外,漂移中间区段226内的两个最大掺杂剂浓度在深度D1及D2处。
深度D2还界定漂移底部区段228,漂移底部区段228从深度D2向下延伸一距离。漂移底部区段228在热驱动工艺期间被掺杂,热驱动工艺致使掺杂剂从下部区域222向下外扩到底部区段228中。(替代地,可颠倒形成上部区域220及下部区域222的次序。)
漂移底部区段228具有其中掺杂剂浓度从深度D2处随深度增加而减小的掺杂剂浓度分布曲线。在此实例中,漂移底部区段228从深度D2处的高掺杂剂浓度持续地减小到较低掺杂剂浓度。此外,漂移底部区段228内的最大掺杂剂浓度在深度D2处。
如图2B中所展示,在已形成漏极漂移区域212之后,在半导体材料210中形成一对浅沟槽隔离(STI)区域230以触及漏极漂移区域212。STI区域230可以常规方式形成。举例来说,可在半导体材料210上方形成硬掩模。在已形成硬掩模之后,穿过所述硬掩模而蚀刻半导体材料210以在半导体材料210中形成若干沟槽。接下来,移除硬掩模,且在半导体材料210的顶部表面上沉积非导电材料以填充沟槽。接着(例如)运用化学机械平面化(CMP)工艺而移除半导体材料210的顶部表面上的非导电材料,以留下沟槽中的STI区域230。
如图2B中进一步所展示,在已形成STI区域230之后,接下来在半导体材料210内形成经掺杂区域232。经掺杂区域232具有第二导电类型的背栅极区域234及第一导电类型的表面区域236,表面区域236触及背栅极区域234。
背栅极区域234经形成以具有与三个掺杂剂浓度峰值对应的阶梯形状:从半导体材料210的顶部表面向下的深度D3处的峰值、较低深度D4处的峰值、及更低深度D5处的峰值。在此实例中,背栅极区域234具有p导电类型,且表面区域236具有n导电类型。
背栅极区域234可通过以下方式形成:首先将掺杂剂毯覆式植入到半导体材料210中以形成触及漏极漂移区域212的底部区段228且位于底部区段228以下的埋入区域240。埋入区域240在深度D5处具有掺杂剂浓度峰值。在此实例中,植入硼以形成p型埋入区域234。硼掺杂剂可经植入具有(举例来说)1×1012到9×1013的剂量及400keV到900keV的能量。
如图2C中所展示,在已形成埋入区域240之后,常规地在半导体材料210上形成经图案化光致抗蚀剂层242。在已形成经图案化光致抗蚀剂层242之后,经由经图案化光致抗蚀剂层242将掺杂剂成角度植入到半导体材料210中以形成中间区域244。中间区域244在深度D4处具有掺杂剂浓度峰值。在此实例中,植入硼以形成中间区域244。硼掺杂剂可经植入具有(举例来说)2×1013到4×1013的剂量及300keV到600keV的能量。
在经图案化光致抗蚀剂层242仍在原处的情况下,再次经由经图案化光致抗蚀剂层242将掺杂剂植入到半导体材料210中以形成主体区域246。主体区域246在深度D3处具有掺杂剂浓度峰值。在此实例中,植入硼以形成主体区域246。硼掺杂剂可经植入具有(举例来说)5×1013到3×1014的剂量及70keV到300keV的能量。
在已形成主体区域246之后,又再次经由经图案化光致抗蚀剂层242将掺杂剂植入到半导体材料210中以减小背栅极区域234的大小且形成表面区域236。表面区域236触及半导体材料210的顶部表面214且位于主体区域246上方。在此实例中,植入砷以形成表面区域236。砷掺杂剂可经植入具有(举例来说)5×1013到1×1015的剂量及30keV到160keV的能量。(任选地可省略表面区域236的形成。)
在植入之后,以常规方式移除经图案化光致抗蚀剂层242。在此之后,执行热驱动工艺以使掺杂剂扩散并激活掺杂剂,且完成经掺杂区域232、背栅极区域234及表面区域236的形成。在此实例中,表面区域236及直接环绕区在热驱动之后具有n型导电性,而背栅极区域234在热驱动之后具有p型导电性。(替代地,可颠倒形成漏极漂移区域212及经掺杂区域232的次序。)
深度D3界定衬底顶部区段250,衬底顶部区段250从半导体材料110的顶部表面114向下延伸到深度D3。衬底顶部区段250在表面区域236以下且邻近于表面区域236具有其中掺杂剂浓度随深度增加而增加的掺杂剂浓度分布曲线。在此实例中,衬底顶部区段250从在表面区域236以下且邻近于表面区域236的低掺杂剂浓度持续地增加到深度D3处的高掺杂剂浓度。此外,衬底顶部区段250内的最大掺杂剂浓度在深度D3处。
深度D3及深度D4界定衬底中间区段252,衬底中间区段252从深度D3向下延伸到深度D4。衬底中间区段252具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。
在此实例中,衬底中间区段252从深度D3处的高掺杂剂浓度持续地减小到深度D3与D4之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D4处的较高掺杂剂浓度。此外,衬底中间区段252内的两个最大掺杂剂浓度在深度D3及D4处。
深度D4及深度D5界定衬底中间区段254,衬底中间区段254从深度D4向下延伸到深度D5。衬底中间区段254具有其中掺杂剂浓度首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度分布曲线。
在此实例中,衬底中间区段254从深度D4处的高掺杂剂浓度持续地减小到深度D4与D5之间的一点处的较低掺杂剂浓度,且接着持续地增加到深度D5处的较高掺杂剂浓度。此外,衬底中间区段254内的两个最大掺杂剂浓度在深度D4及D5处。
深度D5还界定衬底底部区段256,衬底底部区段256从深度D5向下延伸一距离。衬底底部区段256具有其中掺杂剂浓度从深度D5处随深度增加而减小的掺杂剂浓度分布曲线。在此实例中,衬底底部区段256从深度D5处的高掺杂剂浓度减小到较低掺杂剂浓度。如所展示,深度D3位于深度D1与深度D2之间。此外,深度D4位于深度D2以下。此外,第二(p)导电类型的背栅极区域234的一部分位于漏极漂移区域112正下方。
如图2D中所展示,一旦已形成经掺杂区域232,方法200接下来便在半导体材料210的顶部表面214上形成栅极电介质层260。在形成栅极电介质层260之前,可执行(举例来说)使用稀氢氟酸的湿法蚀刻的清除蚀刻以移除半导体材料210的顶部表面上的任何不希望氧化物。
栅极电介质层260可以热生长的二氧化硅而实施且具有根据将使用的电压而变化的厚度。举例来说,栅极电介质层260可具有12nm到15nm的热生长的二氧化硅以支持5V栅极操作。栅极电介质层260可包含额外多层其它电介质材料(例如氮氧化硅或氧化铪)。
在此之后,在栅极电介质层260上沉积栅极材料层262。栅极材料层262可包含100nm到200nm的多晶硅及可能地在多晶硅上包含金属硅化物层,例如100nm到200nm的硅化钨。可用于实施栅极材料层262的其它材料属于此实例的范围内。接下来,常规地在栅极材料层262上方形成经图案化光致抗蚀剂层264。
如图2E中所展示,在已形成经图案化光致抗蚀剂层264之后,以常规方式蚀刻栅极材料层262的所暴露区域以暴露栅极电介质层260且形成栅极270。在蚀刻之后,以常规方式移除经图案化光致抗蚀剂层264。
如图2F中所展示,在已移除经图案化光致抗蚀剂层264之后,常规地在栅极270的横向表面上形成栅极侧壁间隔件272。栅极侧壁间隔件272可通过以下方式而形成:在半导体装置的顶部表面上方形成50nm到150nm厚的二氧化硅保形层,且接着使用各向异性蚀刻工艺(例如反应离子蚀刻(RIE)工艺)而将二氧化硅从水平表面移除。
如图2F中进一步所展示,接下来常规地在栅极电介质层260及栅极270上形成经图案化光致抗蚀剂层274。在此之后,经由经图案化光致抗蚀剂层274而植入具有与漏极漂移区域212相同的导电类型的掺杂剂以形成源极区域280及漏极区域282。源极区域280减小背栅极区域234及表面区域236的大小。漏极区域282减小漏极漂移区域212的大小。
经重掺杂的源极区域280触及背栅极区域234及表面区域236。也经重掺杂的漏极区域282形成于STI区域230之间以触及漏极漂移区域212。在植入之后,以常规方式移除经图案化光致抗蚀剂层274。在此实例中,源极区域280及漏极区域282是n+区域。所述植入物可具有8×1014到1×1016的剂量及20keV到70keV的能量。
如图2G中所展示,在已移除经图案化光致抗蚀剂层274之后,接下来常规地在栅极电介质层260及栅极270上形成经图案化光致抗蚀剂层284。在此之后,经由经图案化光致抗蚀剂层284而植入具有与背栅极区域234相同的导电类型的掺杂剂以形成主体接触区域286。
经重掺杂的主体接触区域286触及主体区域246。在植入之后,以常规方式移除经图案化光致抗蚀剂层284以完成LDMOS晶体管结构290的形成。在此实例中,主体接触区域276是p+区域。所述植入物可具有8×1014到1×1016的剂量及20keV到70keV的能量。
在权利要求书的范围内,在所描述实施例中可做出若干修改,且其它实施例是可能的。
Claims (20)
1.一种横向扩散金属氧化物半导体LDMOS晶体管,其包括:
半导体材料;
漏极漂移区域,其位于所述半导体材料内,所述漏极漂移区域具有第一导电类型、第一深度处的第一水平掺杂剂浓度峰值及第二深度处的第二水平掺杂剂浓度峰值,所述第一深度是从所述半导体材料的顶部表面向下测量的一距离,所述第二深度是从所述第一深度向下测量的一距离;
背栅极区域,其位于所述半导体材料内以触及所述漏极漂移区域,所述背栅极区域具有第二导电类型、第三深度处的第三水平掺杂剂浓度峰值、第四深度处的第四水平掺杂剂浓度峰值及第五深度处的第五水平掺杂剂浓度峰值,所述第三深度是从所述半导体材料的所述顶部表面向下测量的一距离,所述第四深度是从所述第三深度向下测量的一距离,且所述第五深度是从所述第四深度向下测量的一距离;
栅极电介质层,其触及所述半导体材料的所述顶部表面;及
栅极,其触及所述栅极电介质层且位于所述栅极电介质层上方在所述漏极漂移区域及所述背栅极区域正上方。
2.根据权利要求1所述的晶体管,其中所述第三深度位于所述第一深度与所述第二深度之间。
3.根据权利要求2所述的晶体管,其中所述第四深度位于所述第二深度以下。
4.根据权利要求3所述的晶体管,其中所述背栅极区域的一部分位于所述漏极漂移区域正下方。
5.根据权利要求4所述的晶体管,其中:
所述第一深度界定漂移顶部区段,所述漂移顶部区段从所述半导体材料的所述顶部表面向下延伸到所述第一深度,所述漂移顶部区段具有随深度增加而增加的掺杂剂浓度;且
所述第一深度及第二深度界定漂移中间区段,所述漂移中间区段从所述第一深度延伸到所述第二深度,所述漂移中间区段具有首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度。
6.根据权利要求5所述的晶体管,且其进一步包括位于所述半导体材料内的一对浅沟槽隔离STI区域,所述STI区域具有位于所述第一深度以下的下部表面。
7.根据权利要求6所述的晶体管,且其进一步包括具有所述第一导电类型的漏极区域,所述漏极区域位于所述半导体材料内在所述STI区域之间以触及所述漏极漂移区域,所述漏极区域具有基本上大于所述漏极漂移区域的最高掺杂剂浓度的掺杂剂浓度。
8.根据权利要求7所述的晶体管,且其进一步包括具有所述第一导电类型的源极区域,所述源极区域位于所述半导体材料内以触及所述背栅极区域,所述源极区域具有基本上大于所述漏极漂移区域的所述最高掺杂剂浓度的掺杂剂浓度。
9.根据权利要求8所述的晶体管,且其进一步包括具有所述第二导电类型的主体接触区域,所述主体接触区域位于所述半导体材料内以触及所述背栅极区域,所述主体接触区域具有基本上大于所述背栅极区域的最高掺杂剂浓度的掺杂剂浓度。
10.根据权利要求9所述的晶体管,其中所述背栅极区域的沟道区域位于所述源极区域与所述漏极区域之间,所述栅极位于所述沟道区域正上方。
11.一种形成横向扩散金属氧化物半导体LDMOS晶体管的方法,所述方法包括:
在半导体材料内形成漏极漂移区域,所述漏极漂移区域具有第一导电类型、第一深度处的第一水平掺杂剂浓度峰值及第二深度处的第二水平掺杂剂浓度峰值,所述第一深度是从所述半导体材料的顶部表面向下测量的一距离,所述第二深度是从所述第一深度向下测量的一距离;
在所述半导体材料内形成背栅极区域以触及所述漏极漂移区域,所述背栅极区域具有第二导电类型、第三深度处的第三水平掺杂剂浓度峰值、第四深度处的第四水平掺杂剂浓度峰值及第五深度处的第五水平掺杂剂浓度峰值,所述第三深度是从所述半导体材料的所述顶部表面向下测量的一距离,所述第四深度是从所述第三深度向下测量的一距离,且所述第五深度是从所述第四深度向下测量的一距离;
形成触及所述半导体材料的所述顶部表面的栅极电介质层;及
形成触及所述栅极电介质层且位于所述栅极电介质层上方在所述漏极漂移区域及所述背栅极区域正上方的栅极。
12.根据权利要求11所述的方法,其中所述第三深度位于所述第一深度与所述第二深度之间。
13.根据权利要求12所述的方法,其中所述第四深度位于所述第二深度以下。
14.根据权利要求13所述的方法,其中所述背栅极区域的一部分位于所述漏极漂移区域正下方。
15.根据权利要求14所述的方法,其中:
所述第一深度界定漂移顶部区段,所述漂移顶部区段从所述半导体材料的所述顶部表面向下延伸到所述第一深度,所述漂移顶部区段具有随深度增加而增加的掺杂剂浓度;且
所述第一深度及第二深度界定漂移中间区段,所述漂移中间区段从所述第一深度延伸到所述第二深度,所述漂移中间区段具有首先随深度增加而减小且接着随深度增加而增加的掺杂剂浓度。
16.根据权利要求15所述的方法,且其进一步包括在所述半导体材料内形成一对浅沟槽隔离STI区域,所述STI区域具有位于所述第一深度以下的下部表面。
17.根据权利要求16所述的方法,且其进一步包括在所述半导体材料内在所述STI区域之间形成具有所述第一导电类型的漏极区域以触及所述漏极漂移区域,所述漏极区域具有基本上大于所述漏极漂移区域的最高掺杂剂浓度的掺杂剂浓度。
18.根据权利要求17所述的方法,且其进一步包括在所述半导体材料内形成具有所述第一导电类型的源极区域以触及所述背栅极区域,所述源极区域具有基本上大于所述漏极漂移区域的所述最高掺杂剂浓度的掺杂剂浓度。
19.根据权利要求18所述的方法,且其进一步包括在所述半导体材料内形成具有所述第二导电类型的主体接触区域以触及所述背栅极区域,所述主体接触区域具有基本上大于所述背栅极区域的最高掺杂剂浓度的掺杂剂浓度。
20.根据权利要求12所述的方法,其中形成所述背栅极区域包含:
将所述第二导电类型的多种掺杂剂毯覆式植入到所述半导体材料中以形成位于所述第二深度以下的埋入区域,所述埋入区域在所述第五深度处具有水平掺杂剂浓度峰值;
经由经图案化层将所述第二导电类型的多种掺杂剂植入到所述半导体材料中以形成位于所述第二深度以下且位于所述第五深度以上的中间区域,所述中间区域在所述第四深度处具有水平掺杂剂浓度峰值;及
经由所述经图案化层将所述第二导电类型的多种掺杂剂植入到所述半导体材料中以形成位于所述第一深度与所述第二深度之间的主体区域,所述主体区域在所述第三深度处具有水平掺杂剂浓度峰值。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910792601.3A CN110649100B (zh) | 2014-03-06 | 2015-03-06 | 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461948853P | 2014-03-06 | 2014-03-06 | |
US61/948,853 | 2014-03-06 | ||
US14/556,185 | 2014-11-30 | ||
US14/556,185 US9455332B2 (en) | 2014-03-06 | 2014-11-30 | LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd |
PCT/US2015/019258 WO2015134909A1 (en) | 2014-03-06 | 2015-03-06 | Ldmos transistor and method of forming the ldmos transistor with improved rds*cgd |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910792601.3A Division CN110649100B (zh) | 2014-03-06 | 2015-03-06 | 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106030820A true CN106030820A (zh) | 2016-10-12 |
CN106030820B CN106030820B (zh) | 2019-09-24 |
Family
ID=54018218
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910792601.3A Active CN110649100B (zh) | 2014-03-06 | 2015-03-06 | 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 |
CN201580010177.2A Active CN106030820B (zh) | 2014-03-06 | 2015-03-06 | 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910792601.3A Active CN110649100B (zh) | 2014-03-06 | 2015-03-06 | 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法 |
Country Status (4)
Country | Link |
---|---|
US (4) | US9455332B2 (zh) |
JP (1) | JP6574792B2 (zh) |
CN (2) | CN110649100B (zh) |
WO (1) | WO2015134909A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110998842A (zh) * | 2017-08-21 | 2020-04-10 | 德克萨斯仪器股份有限公司 | 具有梯形jfet、底栅及镇流漂移的集成电路、ldmos和制造方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104701372B (zh) * | 2013-12-06 | 2017-10-27 | 无锡华润上华科技有限公司 | 横向扩散金属氧化物半导体器件及其制造方法 |
US20160035822A1 (en) * | 2014-07-30 | 2016-02-04 | Freescale Semiconductor, Inc. | High Voltage Semiconductor Devices and Methods for their Fabrication |
US9893146B1 (en) * | 2016-10-04 | 2018-02-13 | Monolithic Power Systems, Inc. | Lateral DMOS and the method for forming thereof |
US9865729B1 (en) | 2016-12-20 | 2018-01-09 | Texas Instruments Incorporated | Laterally diffused metal oxide semiconductor with segmented gate oxide |
US10103258B2 (en) | 2016-12-29 | 2018-10-16 | Texas Instruments Incorporated | Laterally diffused metal oxide semiconductor with gate poly contact within source window |
US10103233B1 (en) | 2017-09-29 | 2018-10-16 | Nxp Usa, Inc. | Transistor die with drain via arrangement, and methods of manufacture thereof |
CN116759455A (zh) * | 2018-05-25 | 2023-09-15 | 矽力杰半导体技术(杭州)有限公司 | 横向扩散金属氧化物半导体器件和其制造方法 |
US10672903B2 (en) * | 2018-07-25 | 2020-06-02 | Nxp Usa, Inc. | Semiconductor device with drain active area |
CN114256131A (zh) * | 2020-09-23 | 2022-03-29 | 无锡华润上华科技有限公司 | 半导体结构的制备方法及半导体结构 |
US11658240B2 (en) | 2020-10-04 | 2023-05-23 | Globalfoundries Singapore Pte. Ltd. | Semiconductor transistors on multi-layered substrates |
CN114122113B (zh) * | 2022-01-27 | 2022-05-03 | 江苏游隼微电子有限公司 | 一种高可靠的mosfet功率半导体器件结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164537A1 (en) * | 2007-01-04 | 2008-07-10 | Jun Cai | Integrated complementary low voltage rf-ldmos |
US20080258215A1 (en) * | 2007-04-23 | 2008-10-23 | Olof Tornblad | LDMOS Device |
US20110014766A1 (en) * | 2009-03-17 | 2011-01-20 | Alpha And Omega Semiconductor Incorporated | Bottom-drain ldmos power mosfet structure having a top drain strap |
US20130207186A1 (en) * | 2009-12-02 | 2013-08-15 | Fairchild Semiconductor Corporation | Stepped-source ldmos architecture |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386136A (en) * | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
US6168983B1 (en) * | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
US6768171B2 (en) * | 2000-11-27 | 2004-07-27 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
KR100948139B1 (ko) * | 2003-04-09 | 2010-03-18 | 페어차일드코리아반도체 주식회사 | 높은 브레이크다운 전압 및 낮은 온 저항을 위한 다중전류 이동 경로를 갖는 수평형 이중-확산 모스 트랜지스터 |
US7439584B2 (en) * | 2005-05-19 | 2008-10-21 | Freescale Semiconductor, Inc. | Structure and method for RESURF LDMOSFET with a current diverter |
WO2007052196A1 (en) * | 2005-11-02 | 2007-05-10 | Nxp B.V. | Method of manufacturing a semiconductor device |
JP2007258283A (ja) * | 2006-03-21 | 2007-10-04 | Toyota Motor Corp | 絶縁ゲート型半導体装置 |
US8304835B2 (en) * | 2009-03-27 | 2012-11-06 | National Semiconductor Corporation | Configuration and fabrication of semiconductor structure using empty and filled wells |
JP2011100847A (ja) * | 2009-11-05 | 2011-05-19 | Sharp Corp | 半導体装置及びその製造方法 |
KR101681494B1 (ko) * | 2010-03-03 | 2016-12-01 | 삼성전자 주식회사 | 반도체 장치 |
KR101800371B1 (ko) * | 2011-05-27 | 2017-11-23 | 삼성전자주식회사 | 반도체 장치 |
CN103035717B (zh) * | 2012-07-27 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | 阶梯形漂移区的ldmos器件及其制造方法 |
JP2015141996A (ja) * | 2014-01-28 | 2015-08-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
-
2014
- 2014-11-30 US US14/556,185 patent/US9455332B2/en active Active
-
2015
- 2015-03-06 CN CN201910792601.3A patent/CN110649100B/zh active Active
- 2015-03-06 JP JP2016573708A patent/JP6574792B2/ja active Active
- 2015-03-06 CN CN201580010177.2A patent/CN106030820B/zh active Active
- 2015-03-06 WO PCT/US2015/019258 patent/WO2015134909A1/en active Application Filing
-
2016
- 2016-08-23 US US15/244,616 patent/US10461156B2/en active Active
-
2019
- 2019-10-29 US US16/666,587 patent/US11610968B2/en active Active
-
2023
- 2023-03-13 US US18/120,650 patent/US20230215918A1/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164537A1 (en) * | 2007-01-04 | 2008-07-10 | Jun Cai | Integrated complementary low voltage rf-ldmos |
US20080258215A1 (en) * | 2007-04-23 | 2008-10-23 | Olof Tornblad | LDMOS Device |
US20110014766A1 (en) * | 2009-03-17 | 2011-01-20 | Alpha And Omega Semiconductor Incorporated | Bottom-drain ldmos power mosfet structure having a top drain strap |
US20130207186A1 (en) * | 2009-12-02 | 2013-08-15 | Fairchild Semiconductor Corporation | Stepped-source ldmos architecture |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110998842A (zh) * | 2017-08-21 | 2020-04-10 | 德克萨斯仪器股份有限公司 | 具有梯形jfet、底栅及镇流漂移的集成电路、ldmos和制造方法 |
CN110998842B (zh) * | 2017-08-21 | 2023-12-19 | 德克萨斯仪器股份有限公司 | 具有梯形jfet、底栅及镇流漂移的集成电路、ldmos和制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2017507502A (ja) | 2017-03-16 |
US20150255596A1 (en) | 2015-09-10 |
US20230215918A1 (en) | 2023-07-06 |
US9455332B2 (en) | 2016-09-27 |
US10461156B2 (en) | 2019-10-29 |
CN110649100A (zh) | 2020-01-03 |
CN106030820B (zh) | 2019-09-24 |
US20160365412A1 (en) | 2016-12-15 |
CN110649100B (zh) | 2024-05-10 |
US20200066842A1 (en) | 2020-02-27 |
WO2015134909A1 (en) | 2015-09-11 |
US11610968B2 (en) | 2023-03-21 |
JP6574792B2 (ja) | 2019-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20230215918A1 (en) | Ldmos transistor and method of forming the ldmos transistor with improved rds*cgd | |
US7928508B2 (en) | Disconnected DPW structures for improving on-state performance of MOS devices | |
US7816744B2 (en) | Gate electrodes of HVMOS devices having non-uniform doping concentrations | |
CN101290936B (zh) | 半导体器件及其制造方法 | |
CN111108593B (zh) | 窄深沟槽的沉降物至掩埋层连接区域 | |
US20160087083A1 (en) | Semiconductor device and method of fabricating same | |
CN101889327A (zh) | 具有带易于浮岛形成的台阶式沟槽的电压维持层的功率半导体器件的制造方法 | |
JP5807597B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
KR100558041B1 (ko) | 반도체 소자의 트랜지스터 및 그 제조 방법 | |
JP2003060204A (ja) | Dmosトランジスタの製造方法 | |
US8524548B2 (en) | DMOS Transistor with a cavity that lies below the drift region | |
CN107785367B (zh) | 集成有耗尽型结型场效应晶体管的器件及其制造方法 | |
TWI525817B (zh) | Semiconductor device and method for manufacturing semiconductor device | |
CN103915498A (zh) | 隆起源极/漏极mos晶体管及借助植入间隔件及外延间隔件形成所述晶体管的方法 | |
CN107546276A (zh) | 带有注入式背栅的集成jfet结构 | |
CN103839998B (zh) | Ldmos器件及其制造方法 | |
CN112531026B (zh) | 横向扩散金属氧化物半导体器件及其制造方法 | |
CN108574014A (zh) | Ldmos器件及其制造方法 | |
CN108231682A (zh) | 半导体器件及其形成方法 | |
CN106024900A (zh) | 改善栅极诱导漏极漏电的方法以及非均匀沟道掺杂器件 | |
JP2017034006A (ja) | 半導体装置及び半導体装置の製造方法 | |
CN104701365B (zh) | 半导体器件及其形成方法 | |
CN104659076B (zh) | Demos器件及制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |