CN114122113B - 一种高可靠的mosfet功率半导体器件结构 - Google Patents

一种高可靠的mosfet功率半导体器件结构 Download PDF

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CN114122113B
CN114122113B CN202210097804.2A CN202210097804A CN114122113B CN 114122113 B CN114122113 B CN 114122113B CN 202210097804 A CN202210097804 A CN 202210097804A CN 114122113 B CN114122113 B CN 114122113B
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程晨
王彬
徐凯
吴李瑞
张永生
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Abstract

本发明公开了一种高可靠的MOSFET功率半导体器件结构，将现有MOSFET功率半导体器件结构中呈条状并排的源区和接触区改成沿器件横向延伸方向呈交替分布的N+型和P+型离子注入区域。交替分布的N+型和P+型离子注入区域相互之间形成了电荷平衡，可以有效防止寄生BJT开启，大大降低了雪崩击穿的发生，扩大了器件安全工作区，提高了器件的可靠性。

Description

一种高可靠的MOSFET功率半导体器件结构
技术领域
本发明涉及一种功率半导体器件，尤其涉及一种MOSFET功率半导体器件。
背景技术
功率MOSFET因其开关速度快、损耗小、输入阻抗高、驱动功率小、频率特性好等优点，在功率变换领域起到重要作用。不断提高的系统性能要求功率MOSFET在具有更低功率损耗的同时，在高电应力下也应具有更高的可靠性。当系统回路中存在非箝位电感负载时，导通状态下存储在电感中的能量会在关断时全部由MOSFET释放，高电压和大电流将同时施加在功率MOSFET上，极易造成器件失效。因此，非箝位感性负载下的开关过程(UnclampedInductive Switching，UIS)通常被认为是功率MOSFET在应用中所能面临的最极端的电应力情况。因此器件的抗UIS失效能力常被用于评定MOSFET功率半导体的可靠性，而UIS耐量是衡量MOSFET功率半导体的抗UIS失效能力的重要参数。
中国专利CN201810990451.2公开了一种超结MOS型功率半导体器件，该器件主要通过引入三维超结结构克服厚漂移区和深沟槽所带来漂移区无法完全耗尽的问题，在提高器件耐压性能的同时能够降低其导通电阻，并且无需将栅极结构延伸到氧埋层以提供电场调节作用，从而能够降低栅电容，提高器件开关速度。但该器件会存在寄生BJT(BipolarJunction Transistor，双极型晶体管)开启的可能，而寄生BJT的开启是引起UIS失效的重要原因之一。UIS的失效通常被认为是器件“主动”模式，这是由于寄生BJT在UIS雪崩时的导通，导通后流过体内的大电流将使器件迅速升温，损坏器件。该器件的N+源区作为寄生BJT的发射区，N型漂移区构成寄生BJT的集电极区，而P型体区作为基区，当器件发生雪崩击穿时，雪崩电流经由N+源区下方的P型体区到达N型漂移区，而雪崩电流流经寄生BJT的基区时，由于P型体区本身存在电阻必然会产生正向压降，当压降大于寄生BJT的正向导通压降时，寄生BJT的发射极正偏，进入正向放大工作区，放大雪崩电流，造成器件的发热烧毁。
发明内容
发明目的：针对上述现有技术，提出一种高可靠的MOSFET功率半导体器件结构，降低MOSFET功率器件寄生晶体管的开启几率，从而有效防止器件雪崩击穿的发生。
技术方案：一种高可靠的MOSFET功率半导体器件结构，其元胞结构纵向自下而上包括衬底电极、A导电类型衬底、埋氧层、B导电类型缓冲层，B导电类型缓冲层的表面设有三维超结结构，三维超结构由沿横向延伸方向交替相接的B导电类型漂移区和A导电类型柱区构成，其中B导电类型漂移区和A导电类型柱区的上、下表面平齐；
三维超结构的表面一侧具有沟槽栅结构，沟槽栅结构包括沟槽栅电极以及其侧面和底面的沟槽栅介质；三维超结构的表面另一侧具有B+导电类型漏区，B+导电类型漏区的表面具有金属化漏极；沟槽栅结构与B+导电类型漏区之间的三维超结构中具有深介质沟槽，深介质沟槽与沟槽栅结构之间的三维超结构顶层具有A导电类型体区，A导电类型体区中具有相互独立的源区和接触区，源区和A导电类型体区通过侧面的沟槽栅介质与沟槽栅电极接触，接触区与深介质沟槽直接接触；源区和接触区的上表面具有金属化源极；金属化源极和沟槽栅电极通过沟槽栅介质相隔离；
源区沿横向延伸方向由A+导电类型和B+导电类型依次交替离子注入，接触区沿横向延伸方向由B+导电类型和A+导电类型依次交替离子注入，源区和接触区相正对的各段注入的离子导电类型不同。
进一步的，导电类型A为P型，导电类型B为N型；或者，导电类型A为N型，导电类型B为P型。
进一步的，深介质沟槽纵向深度大于其宽度，即深介质沟槽的横纵比小于1。
进一步的，A导电类型体区的结深小于沟槽栅电极的深度，而沟槽栅电极的纵向深度小于深介质沟槽的纵向深度。
进一步的，源区和接触区沿横向延伸方向依次交替离子注入的段数大于等于4。
有益效果：本发明将现有MOSFET功率半导体器件结构中呈条状并排的源区和接触区改成沿器件横向延伸方向呈交替分布的N+型和P+型离子注入区域。交替分布的N+型和P+型离子注入区域即在源区内部之间形成了电荷平衡，无法作为寄生BJT的发射区，从而可以有效避免现有技术中寄生BJT开启几率，大大降低了雪崩击穿的发生，扩大了器件安全工作区，提高了器件的可靠性。
附图说明
图1为本发明器件的结构示意图；
图2是图1中沿AB的平面示意图；
图3是图1中沿CD的平面示意图；
图4是图1中沿EF的平面示意图；
图5是图1中沿GH的平面示意图。
具体实施方式
下面结合附图对本发明做更进一步的解释。
如图1至图5所示，一种高可靠的MOSFET功率半导体器件结构，其元胞结构纵向自下而上包括衬底电极215、A导电类型衬底214、埋氧层213、B导电类型缓冲层212，B导电类型缓冲层212的表面设有三维超结结构，三维超结构由沿横向延伸方向交替相接的B导电类型漂移区210和A导电类型柱区211构成，其中B导电类型漂移区210和A导电类型柱区211的上、下表面平齐。
三维超结构的表面一侧具有沟槽栅结构，沟槽栅结构包括沟槽栅电极201以及其侧面和底面的沟槽栅介质202。三维超结构的表面另一侧具有B+导电类型漏区209，B+导电类型漏区209的表面具有金属化漏极205。沟槽栅结构与B+导电类型漏区209之间的三维超结构中具有深介质沟槽204，深介质沟槽204与沟槽栅结构之间的三维超结构顶层具有A导电类型体区208，A导电类型体区208中具有相互独立的源区206和接触区207，源区206和A导电类型体区208通过侧面的沟槽栅介质202与沟槽栅电极201接触，接触区207与深介质沟槽204直接接触。源区206和接触区207的上表面具有金属化源极203，金属化源极203和沟槽栅电极201通过沟槽栅介质202相隔离。
源区206沿横向延伸方向由A+导电类型和B+导电类型依次交替离子注入，具体的，在B导电类型漂移区210区域正上方形成N段离子注入区域，即206-1段~206-N段，在A导电类型柱区211正上方形成N段离子注入区域，即206-N+1段~206-N+N段。接触区207沿横向延伸方向由B+导电类型和A+导电类型依次交替离子注入，具体的，在B导电类型漂移区210区域正上方形成N段离子注入区域，即207-1段~207-N段，在A导电类型柱区211正上方形成N段离子注入区域，即207-N+1段~207-N+N段。上述结构中，N取大于等于2。源区206和接触区207相正对的各段注入的离子导电类型不同，如下表所示，且相正对各段的长度一致。
Figure DEST_PATH_IMAGE002
上述结构中，导电类型A为P型，导电类型B为N型；或者，导电类型A为N型，导电类型B为P型。深介质沟槽204纵向深度大于其宽度，即深介质沟槽204的横纵比小于1。A导电类型体区208的结深小于沟槽栅电极201的深度，而沟槽栅电极201的纵向深度小于深介质沟槽204的纵向深度。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (5)

1.一种高可靠的MOSFET功率半导体器件结构，其特征在于，其元胞结构纵向自下而上包括衬底电极（215）、A导电类型衬底（214）、埋氧层（213）、B导电类型缓冲层（212），B导电类型缓冲层（212）的表面设有三维超结结构，三维超结构由沿横向延伸方向交替相接的B导电类型漂移区（210）和A导电类型柱区（211）构成，其中B导电类型漂移区（210）和A导电类型柱区（211）的上、下表面平齐；
三维超结构的表面一侧具有沟槽栅结构，沟槽栅结构包括沟槽栅电极（201）以及其侧面和底面的沟槽栅介质（202）；三维超结构的表面另一侧具有B+导电类型漏区（209），B+导电类型漏区（209）的表面具有金属化漏极（205）；沟槽栅结构与B+导电类型漏区（209）之间的三维超结构中具有深介质沟槽（204），深介质沟槽（204）与沟槽栅结构之间的三维超结构顶层具有A导电类型体区（208），A导电类型体区（208）中具有相互独立的源区（206）和接触区（207），源区（206）和A导电类型体区（208）通过侧面的沟槽栅介质（202）与沟槽栅电极（201）接触，接触区（207）与深介质沟槽（204）直接接触；源区（206）和接触区（207）的上表面具有金属化源极（203）；金属化源极（203）和沟槽栅电极（201）通过沟槽栅介质（202）相隔离；
源区（206）沿横向延伸方向由A+导电类型和B+导电类型依次交替离子注入，接触区（207）沿横向延伸方向由B+导电类型和A+导电类型依次交替离子注入，源区（206）和接触区（207）相正对的各段注入的离子导电类型不同。
2.根据权利要求1所述的高可靠的MOSFET功率半导体器件结构，其特征在于，导电类型A为P型，导电类型B为N型；或者，导电类型A为N型，导电类型B为P型。
3.根据权利要求1所述的高可靠的MOSFET功率半导体器件结构，其特征在于，深介质沟槽（204）纵向深度大于其宽度，即深介质沟槽（204）的横纵比小于1。
4.根据权利要求1所述的高可靠的MOSFET功率半导体器件结构，其特征在于，A导电类型体区（208）的结深小于沟槽栅电极（201）的深度，而沟槽栅电极（201）的纵向深度小于深介质沟槽（204）的纵向深度。
5.根据权利要求1所述的高可靠的MOSFET功率半导体器件结构，其特征在于，源区（206）和接触区（207）沿横向延伸方向依次交替离子注入的段数大于等于4。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003214585A1 (en) * 2002-04-18 2003-10-27 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices
CN101162697A (zh) * 2006-10-13 2008-04-16 台湾积体电路制造股份有限公司 半导体元件的制造方法
CN109065626A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种具有介质阻挡层的槽栅dmos器件

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994871A (en) * 1988-12-02 1991-02-19 General Electric Company Insulated gate bipolar transistor with improved latch-up current level and safe operating area
GB0225812D0 (en) * 2002-11-06 2002-12-11 Koninkl Philips Electronics Nv Semiconductor devices and methods of manufacturing thereof
JP4225177B2 (ja) * 2002-12-18 2009-02-18 株式会社デンソー 半導体装置およびその製造方法
JP4470454B2 (ja) * 2003-11-04 2010-06-02 株式会社豊田中央研究所 半導体装置とその製造方法
DE102005014744B4 (de) * 2005-03-31 2009-06-18 Infineon Technologies Ag Trenchtransistor mit erhöhter Avalanchefestigkeit und Herstellungsverfahren
CN101916780A (zh) * 2010-07-22 2010-12-15 中国科学院上海微系统与信息技术研究所 一种具有多层超结结构的ldmos器件
JP2012142334A (ja) * 2010-12-28 2012-07-26 Renesas Electronics Corp 半導体装置
CN102110716B (zh) * 2010-12-29 2014-03-05 电子科技大学 槽型半导体功率器件
CN102130012B (zh) * 2010-12-31 2012-06-27 中国科学院上海微系统与信息技术研究所 Soi超结ldmos器件的ldd、lds及缓冲层一体化制作方法
CN102222620A (zh) * 2011-06-23 2011-10-19 上海集成电路研发中心有限公司 一种有效收集衬底电流的ldmos制备方法
CN102832249A (zh) * 2012-09-11 2012-12-19 电子科技大学 一种mos型功率半导体器件
WO2014174741A1 (ja) * 2013-04-26 2014-10-30 パナソニックＩｐマネジメント株式会社 半導体装置
US9455332B2 (en) * 2014-03-06 2016-09-27 Texas Instruments Incorporated LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd
CN105097914B (zh) * 2014-05-04 2018-02-06 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制造方法
CN105118861B (zh) * 2015-08-21 2018-01-12 西南交通大学 一种横向finfet器件
CN109473476B (zh) * 2017-09-07 2020-12-25 无锡华润上华科技有限公司 一种横向双扩散金属氧化物半导体器件及其制作方法
CN108346701B (zh) * 2018-04-12 2020-05-26 电子科技大学 一种屏蔽栅功率dmos器件
CN109119461B (zh) * 2018-08-28 2020-09-29 电子科技大学 一种超结mos型功率半导体器件及其制备方法
US11894457B2 (en) * 2020-05-09 2024-02-06 Joulwatt Technology Co., Ltd. Semiconductor device and manufacturing method thereof
CN113787788B (zh) * 2021-09-13 2023-08-15 广州大学 一种石墨烯/金属复合材料及其制备方法和应用

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003214585A1 (en) * 2002-04-18 2003-10-27 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices
CN101162697A (zh) * 2006-10-13 2008-04-16 台湾积体电路制造股份有限公司 半导体元件的制造方法
CN109065626A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种具有介质阻挡层的槽栅dmos器件

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