CN105895705B - 一种射频ldmos的“γ”型栅结构及其制备方法 - Google Patents
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Abstract
本发明是一种射频LDMOS的晶体管的“Γ”型栅及其制备方法,其特征在于,对于亚微米栅的射频LDMOS器件,其栅为“Γ”形状,“Γ”型栅的下端为掺杂多晶硅,控制栅的特征长度,“Γ”型栅的表端为多晶硅硅化物,控制栅的电阻大小;通过“Γ”型栅的下端与表端相结合,实现LDMOS最小化的栅特征尺寸与最小化栅阻的相结合。有益效果是:实现了深亚微米栅的形成;消除了深亚微米细线条光刻的套刻偏差;栅多晶硅的表面合金,降低了栅极电阻;“Γ”型栅结构可以重复垒加,进一步大幅降低栅阻大小;“Γ”型结构栅,实现与场板自然隔离,提高场板保护性能;该“Γ”型栅结构有效解决了亚微米细栅线条与栅阻之间的矛盾。
Description
技术领域
本发明是涉及的是一种射频LDMOS的“Γ”型栅结构及其制备方法,属于半导体微电子设计制造技术领域。
背景技术
在微波技术领域,射频LDMOS器件越来越广泛的应用于通讯基站、广播电视以及现代雷达系统上。为了不断提高LDMOS的频率性能,设计上包括以下几个技术措施:1)不断减薄栅氧化层的厚度,2)采用越来越小多晶硅栅的特征尺寸,3)进一步减小多晶硅/硅化物的栅阻。LDMOS栅氧化层由于可靠性要求,其厚度已经接近应用极限,因此频率性能的提高主要手段是措施2和3,由于随着多晶硅栅特征尺寸的减小,即使采用低阻硅化物材料的单位栅宽的栅阻也会偏大,于是第2和第3项措施在进一步提高LDMOS频率性能时遇到的瓶颈,需要设计时折中考虑,这严重限制了LDMOS进一步向更高频发展的空间。
发明内容
本发明提出的是一种射频LDMOS的“Γ”型栅结构及其制备方法,其目的旨在克服现有栅结构技术瓶颈,即栅特征尺减小与栅阻变大的矛盾。采用“Γ”型栅结构时,下端控制栅长,表端降低栅阻;自对准工艺形成了的栅,在后续工艺中进行自对准掺杂注入,消除了细线条光刻的套刻偏差;同时自对准形成了场板大幅度提高了保护效果也降低了寄生栅与场板电容。
本发明的技术解决技术方案:一种射频LDMOS的“Γ”型栅结构,其特征在于,对于亚微米栅的射频LDMOS器件,其栅为“Γ”形状,“Γ”型栅的下端为掺杂多晶硅,控制栅的特征长度,“Γ”型栅的表端为多晶硅硅化物,控制栅的电阻大小;通过 “Γ”型栅的下端与表端相结合,实现LDMOS最小化的栅特征尺寸与最小化栅阻的相结合。
本发明的有益效果是,通过一个或多个叠加“Γ”型栅,使得栅特征尺寸可以降低到0.1微米甚至更小,而栅阻值不受到栅特征尺寸降低的影响,通过“Γ”型栅表端硅化物或叠加栅将使得栅阻降低达一个数量级以上;另外,场板多晶硅通过与“Γ”型栅多晶硅自然隔离,提高了场板保护效果,同时与栅同步形成的阶梯型场板在纵向随高度与“Γ”型栅逐步展开平面距离,有效降低栅源电容;这些特征和优点都大幅度提高了射频LDMOS的微波性能。
附图说明
附图1是在P-/P+的硅衬底上,通过光刻、注入、推进等形成p+、pm、n-等LDMOS掺杂区域,用LPCVD工艺在硅片表面淀积1000Å~1500Å SiO2 介质层, 淀积1000Å~1500ÅPolySi(掺磷)层的结构示意图。
附图2是光刻、刻蚀多晶硅,淀积4000Å~6000Å SiO2 介质层的结构示意图。
附图3是光刻、刻蚀SiO2和PolySi,终止于硅表面,形成多晶硅场板,表面薄氧化,自对准Vt调整注入的结构示意图。
附图4是经栅氧化SiO2厚度100Å~200Å,并淀积1000Å~1500Å PolySi(掺磷)层的结构示意图。
附图5是回刻PolySi,形成侧墙PolySi栅,漏区开孔,终止于硅表面的结构示意图。
附图6是光刻、注入硼,退火推进形成P沟道区,光刻、注入砷,退火激活形成源漏区,LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层的结构示意图。
附图7是CMP抛光掉9000Å~11000Å SiO2至露出侧墙多晶硅,控制侧墙栅高度控制在5000Å~6000Å的结构示意图。
附图8是光刻、刻蚀场板孔,终止于场板多晶硅表面的结构示意图。
附图9是淀积1000Å~1500Å PolySi(掺磷)层的结构示意图。
附图10是光刻、刻蚀“Γ”型栅表端区、场板区连接区的结构示意图。
附图11是光刻、刻蚀源漏区,在表面淀积一层待硅化合金的金属,进行相应条件的高温退火,并选择性地去除表面残余的未合金金属的结构示意图。
附图12是LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层的结构示意图。
附图13是CMP抛光SiO2去掉8000Å~10000Å的结构示意图。
附图14是光刻、刻蚀源漏区、栅区、场板区,终止于硅化物,淀积W塞,蒸发布线金属,光刻、腐蚀形成一次金属电极的结构示意图。
图中的1是硅衬底、2是SiO2介质层、3是掺磷场板多晶硅、4是掺磷栅多晶硅、5是硅化物、6是源金属、7是栅金属、8是场板金属、9是漏金属。
具体实施方式
一种射频LDMOS的“Γ”型栅结构,对于亚微米栅的射频LDMOS器件,其栅为“Γ”形状,“Γ”型栅的下端为掺杂多晶硅,控制栅的特征长度,“Γ”型栅的表端为多晶硅硅化物,控制栅的电阻大小;通过 “Γ”型栅的下端与表端相结合,实现LDMOS最小化的栅特征尺寸与最小化栅阻的相结合。
所述“Γ”型栅的结构,等同于半“T”型栅结构,其“Γ”表端垂直于下端,表端向源端方向扩展,而向漏端方向扩展为零或很少,降低与场板之间的寄生电容,同时留下更大场板的制作空间。
所述“Γ”型栅的结构,采用一个“Γ”型栅单独使用或采用多个“Γ”型栅叠加使用,当采用多个“Γ”时,叠加的“Γ”型栅采用金属结构,进一步降低电阻。
所述“Γ”型栅的结构,与之对应的场板采用阶梯型结构,其与“Γ”型栅在纵向方向上逐渐展开距离,有效降低了场板与栅之间的寄生电容。
所述场板多晶硅在栅多晶硅之前制作形成,在制作栅氧化时,场板多晶硅侧壁氧化形成的SiO2与栅多晶硅的自然隔离,提高场板保护效果。
下面结合附图进一步描述本发明的技术方案。
如附图1所示,在P-/P+的硅衬底上,通过光刻、注入、推进等形成p+、pm、n-等LDMOS通用掺杂区域,用LPCVD工艺在硅片表面淀积1000Å~1500Å SiO2 介质层, 淀积1000Å~1500Å PolySi(掺磷)层。
如附图2所示,光刻、刻蚀多晶硅,然后,淀积4000Å~6000Å SiO2 介质层。
如附图3所示,光刻、刻蚀侧墙,终止于硅表面,形成多晶硅场板,牺牲氧化,自对准Vt调整注入。
如附图4所示,栅氧化SiO2厚度100Å~200Å,淀积1000Å~1500Å PolySi(掺磷)层。
如附图5所示,大面积回刻PolySi,形成侧墙PolySi,漏区开孔,终止于硅表面。
如附图6所示,光刻沟道,注入硼(60KeV/6E13),退火推进,光刻源漏,注入砷(80KeV/3E15),退火激活,LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层。
如附图7所示,CMP抛光SiO2至露出侧墙多晶硅,控制侧墙栅高度控制在6000 ~7000Å。
如附图8所示,光刻场板孔,刻蚀终止于场板多晶硅。
如附图9所示,淀积1000Å~1500Å PolySi(掺磷)层。
如附图10所示,光刻、刻蚀栅表端区与场板区连接区。
如附图11所示,光刻、刻蚀源漏区,在表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,并选择性地去除表面残余的未合金金属,至此,单个 “Γ”型栅结构形成。
如附图12所示,LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层;
如附图13所示,CMP抛光SiO2去掉6000Å~7000Å。
如附图14所示,光刻和刻蚀源、栅、场板、漏孔至硅化物,淀积W塞,蒸发布线金属等,并光刻、腐蚀形成一次金属电极,至此,两个 “Γ”型栅叠加结构形成,后续工艺按照LDMOS常规布线进行多层金属互连。
“Γ”型栅结构的制备方法,包括如下工艺步骤:
1)在P-/P+的硅衬底上,通过光刻、注入、推进等形成p+、pm、n-等LDMOS通用掺杂区域,用LPCVD工艺在硅片表面淀积1000Å~1500Å SiO2 介质层, 淀积1000Å~1500Å PolySi(掺磷)层(图1);
2)光刻、刻蚀多晶硅后,淀积4000Å~6000Å SiO2 介质层(图2);
3)光刻、刻蚀SiO2/PolySi/SiO2,终止于硅表面,形成多晶硅场板,牺牲氧化SiO2厚度200Å~400Å,自对准Vt调整注入(图3);
4)去除牺牲氧化层,栅氧化SiO2厚度100Å~200Å,淀积1000Å~1500Å PolySi(掺磷)层(图4);
5)回刻PolySi,形成侧墙PolySi,光刻、刻蚀漏区开孔,终止于硅表面(图5);
6)光刻、注入硼,退火推进形成P沟道区,光刻、注入砷,退火激活形成源漏区,LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层(图6);
7)CMP抛光掉9000Å~11000Å SiO2至露出侧墙多晶硅,控制侧墙栅高度控制在5000 ~6000Å(图7);
8)光刻、刻蚀场板孔,终止于场板多晶硅表面(图8);
9)淀积1000Å~1500Å PolySi(掺磷)层(图9);
10)光刻、刻蚀“Γ”型栅表端区、场板区连接区(图10);
11)光刻、刻蚀源漏区,在表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,并选择性地去除表面残余的未合金金属,至此, “Γ”型栅结构形成(图11);
12)LPCVD工艺在硅片表面淀积12000Å~15000Å SiO2 介质层(图12);
13)CMP抛光去掉8000Å~10000Å SiO2介质层(图13);
14)光刻、刻蚀源漏区、栅区、场板区,终止于硅化物,淀积W塞,蒸发布线金属,光刻、腐蚀形成一次金属电极,至此,两个 “Γ”型栅叠加结构形成(图14)。
具体实例如下:
1)在P-/P+的硅衬底上,通过光刻、注入、推进等形成p+、pm、n-等LDMOS通用掺杂区域,用LPCVD工艺在硅片表面淀积1000Å SiO2 介质层, 淀积1000Å PolySi(掺磷)层;
2)光刻、刻蚀多晶硅,然后,淀积5000Å SiO2 介质层;
3)光刻、刻蚀侧墙,终止于硅表面,形成多晶硅场板,牺牲氧化,自对准Vt调整注入;
4)栅氧化SiO2厚度150Å,淀积1000Å PolySi(掺磷)层;
5)大面积回刻PolySi,形成侧墙PolySi,漏区开孔,终止于硅表面;
6)光刻沟道,注入硼(60KeV/6E13),退火推进,光刻源漏,注入砷(80KeV/3E15),退火激活,LPCVD工艺在硅片表面淀积8000Å SiO2 介质层;
7)CMP抛光SiO2至露出侧墙多晶硅,控制侧墙栅高度控制在6000Å;
8)光刻场板孔,刻蚀终止于场板多晶硅;
9)淀积1000Å PolySi(掺磷)层;
10)光刻、刻蚀栅表端区与场板区连接区;
11)光刻、刻蚀源漏区,在表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,并选择性地去除表面残余的未合金金属;
12)LPCVD工艺在硅片表面淀积10000Å SiO2 介质层;
13)CMP抛光SiO2去掉7000Å;
14)光刻和刻蚀源、栅、场板、漏孔至硅化物,淀积W塞,蒸发布线金属等,并光刻、腐蚀形成一次金属电极。
Claims (2)
1.一种射频LDMOS的“Γ”型栅结构,其特征在于,对于亚微米栅的射频LDMOS器件,其栅为“Γ”形状,“Γ”型栅的下端为掺杂多晶硅,控制栅的特征长度,“Γ”型栅的表端为多晶硅硅化物,控制栅的电阻大小;通过 “Γ”型栅的下端与表端相结合,实现LDMOS最小化的栅特征尺寸与最小化栅阻的相结合;
所述“Γ”型栅的结构,等同于半“T”型栅结构,其“Γ”表端垂直于下端,表端向源端方向扩展,而向漏端方向扩展为零或很少,降低与场板之间的寄生电容,同时留下更大场板的制作空间;
所述“Γ”型栅的结构,采用一个“Γ”型栅单独使用或采用多个“Γ”型栅叠加使用,当采用多个“Γ”时,叠加的“Γ”型栅采用金属结构,进一步降低电阻;
所述“Γ”型栅的结构,与之对应的场板采用阶梯型结构,其与“Γ”型栅在纵向方向上逐渐展开距离,有效降低了场板与栅之间的寄生电容;
所述场板多晶硅在栅多晶硅之前制作形成,在制作栅氧化时,场板多晶硅侧壁氧化形成的SiO2与栅多晶硅的自然隔离,提高场板保护效果。
2.如权利要求1所述的“Γ”型栅结构的制备方法,其特征是该方法包括如下工艺步骤:
1)在P-/P+的硅衬底上,通过光刻、注入、推进形成p+、pm、n- LDMOS通用掺杂区域,用LPCVD工艺在硅片表面淀积1000Å~1500Å SiO2 介质层, 淀积1000Å~1500Å PolySi掺磷层;
2)光刻、刻蚀多晶硅后,淀积4000Å~6000Å SiO2 介质层;
3)光刻、刻蚀SiO2/PolySi/SiO2,终止于硅表面,形成多晶硅场板,牺牲氧化SiO2厚度200Å~400Å,自对准Vt调整注入;
4)去除牺牲氧化层,栅氧化SiO2厚度100Å~200Å,淀积1000Å~1500Å PolySi掺磷层;
5)回刻PolySi,形成侧墙PolySi,光刻、刻蚀漏区开孔,终止于硅表面;
6)光刻、注入硼,退火推进形成P沟道区,光刻、注入砷,退火激活形成源漏区,LPCVD工艺在硅片表面淀积8000Å~10000Å SiO2 介质层;
7)CMP抛光掉9000Å~11000Å SiO2至露出侧墙多晶硅,控制侧墙栅高度控制在5000 ~6000Å;
8)光刻、刻蚀场板孔,终止于场板多晶硅表面;
9)淀积1000Å~1500Å PolySi掺磷层;
10)光刻、刻蚀“Γ”型栅表端区、场板区连接区;
11)光刻、刻蚀源漏区,在表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,并选择性地去除表面残余的未合金金属,至此, “Γ”型栅结构形成;
12)LPCVD工艺在硅片表面淀积12000Å~15000Å SiO2 介质层;
13)CMP抛光去掉8000Å~10000Å SiO2介质层;
14)光刻、刻蚀源漏区、栅区、场板区,终止于硅化物,淀积W塞,蒸发布线金属,光刻、腐蚀形成一次金属电极,至此,两个 “Γ”型栅叠加结构形成。
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