US20060038255A1 - MOS electric fuse, its programming method, and semiconductor device using the same - Google Patents

MOS electric fuse, its programming method, and semiconductor device using the same Download PDF

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Publication number
US20060038255A1
US20060038255A1 US10/973,412 US97341204A US2006038255A1 US 20060038255 A1 US20060038255 A1 US 20060038255A1 US 97341204 A US97341204 A US 97341204A US 2006038255 A1 US2006038255 A1 US 2006038255A1
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Prior art keywords
impurity region
well
voltage
gate electrode
dielectric film
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US10/973,412
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Keiichi Kushida
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Toshiba Corp
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Individual
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUSHIDA, KEIICHI
Publication of US20060038255A1 publication Critical patent/US20060038255A1/en
Priority to US11/776,839 priority Critical patent/US7573118B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an electric fuse, and more particularly to a MOS electric fuse which is configured to short-circuit a gate dielectric film and which is suitably applied to a MOS semiconductor device.
  • a semiconductor memory enabling electric data writing which uses a fuse element as a storage element.
  • the semiconductor memory of such a type is classified into a fuse ROM which fuses the fuse element to store information, and a fuse ROM which stores information making an insulator to a conductor by dielectric breakdown (may be referred to as antifuse).
  • the fuse ROM that breaks down the insulator to store the information is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication. No. 7-176703.
  • a fuse of a 3-layer structure that sandwiches a silicon layer by refractory metal layers is disposed on a semiconductor substrate, and the silicon layer is converted into a silicide compound of low resistance by supplying a large current to the fuse, and the refractory metal layers are short-circuited from each other.
  • an electric fuse which electrically connects a source/drain of a MOS transistor to its substrate, applies a high voltage between the source/drain and a gate electrode to break down a gate dielectric film, and uses a resistance change therebetween.
  • the breakdown of the fuse element to set a conductive state is called programming.
  • a gate of a PMOSFET is grounded, and a high program voltage is applied to the source, the drain and the substrate. In this case, a channel is formed in the PMOSFET.
  • the applied voltage becomes higher, a withstand limit of the gate dielectric film is exceeded to break down the insulator, thereby making the gate film conductive. In this way, the electric fuse is programmed.
  • a fuse is used to store defective addresses.
  • a fuse of this type there has been known a method which fuses a polysilicon wiring or a transistor.
  • the programming of the MOS transistor type fuse is classified into two cases, that is, a case in which dielectric breakdown of the gate dielectric film occurs on the source (drain) and a case in which dielectric breakdown occurs on the channel. Not only electric characteristics are different between the aforementioned two cases, but also resistance values between the terminals are different depending on a position of the broken down dielectric film. When such a variance occurs in fuse electric characteristics after the breakdown of the dielectric film, a voltage margin is reduced at the reading time of the fuse element to cause a reduction in yield or reliability.
  • a programming method of a MOS electric fuse which comprises:
  • a MOS transistor which comprises a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region;
  • an electric fuse which comprises:
  • substantially binary states of conduction and nonconduction are independently set between the first impurity region and the gate electrode and between the second impurity region and the gate electrode.
  • a semiconductor substrate which comprises:
  • each of the plurality of semiconductor structures comprising
  • FIGS. 1A and 1B are a connection diagram and a sectional view of a conventional MOS electric fuse
  • FIG. 2 is a schematic sectional view illustrating a problem of the conventional MOS electric fuse
  • FIG. 3 is a characteristic view illustrating a cause of a variance in electric characteristics of the conventional MOS electric fuse
  • FIGS. 4A and 4B are a connection diagram and a sectional view during programming of an electric fuse (PMOS) according to a first embodiment
  • FIGS. 5A and 5B are a connection diagram and a sectional view during reading of the electric fuse according to the first embodiment
  • FIGS. 6A and 6B are a connection diagram and a sectional view when the electric fuse of the first embodiment comprises an NMOS;
  • FIGS. 7A and 7B are a connection diagram and a sectional view during source programming of an electric fuse according to a second embodiment
  • FIGS. 8A and 8B are a connection diagram and a sectional view during drain programming of the electric fuse according to the second embodiment
  • FIGS. 9A and 9B are a connection diagram and a sectional view during reading of the electric fuse according to the second embodiment
  • FIG. 10 is a block diagram of an application circuit of the electric fuse according to the second embodiment.
  • FIG. 11 is a circuit diagram showing a specific example of the application circuit of FIG. 10 ;
  • FIGS. 12A to 12 C are connection diagrams for programming and reading, and a sectional view during programming of an electric fuse according to a third embodiment.
  • FIG. 13 is a block diagram showing an application circuit of a conventional MOS electric fuse.
  • the fuse of FIG. 1A is referred to as an inversion type which connects a source/drain/substrate of a PMOS to a program voltage (VBP) terminal, and a gate electrode to a ground (VSS).
  • the fuse of FIG. 1B is referred to as an accumulation type, in which connections to a VBP terminal and a VSS terminal are reverse to those of FIG. 1A .
  • the gate electrode of the PMOS is grounded, and a high program voltage VBP is applied to the source, the drain and the substrate. At this time, a channel is formed between the source and the drain of the PMOS.
  • VBP program voltage
  • a withstand limit of a gate dielectric film is exceeded to break down a dielectric film, and a conductive state is set between the gate and the drain/source. In this way, the electric fuse is programmed.
  • breakdown places are classified into two cases: a case of breakdown on the source (or drain) (path A in FIG. 2 ), and a case of breakdown of the dielectric film on the channel (path B in FIG. 2 ).
  • Electric characteristics are different between the two cases because positions of conductive points are different. That is, in the former case, the gate electrode and the source (or drain) are directly connected to each other through a breakdown portion in the case of the breakdown on the source or the drain, and in the latter case, resistance values of a dielectric film horizontal direction are different depending on positions of the broken down dielectric films in the case of the breakdown on the channel, and current values supplied between the VPP and VSS terminals are different as shown in FIG. 3 .
  • a variance occurs in electric characteristics of the fuse after the dielectric film breakdown. Consequently, a voltage margin is deteriorated during reading of a fuse element to reduce yield or reliability.
  • a configuration of a MOS electric fuse, a programming method, and the like are provided to solve the aforementioned problems. That is, a gate dielectric film breakdown mode of the MOS electric fuse is limited to breakdown between a gate and a source (or drain), or breakdown substantially on a center between the soured and the drain, and electric characteristics of the electric fuse are made uniform. Additionally, since programs can be independently executed in the case of the breakdown between the gate and the source, between the gate and the drain, a dielectric film between the gate and the source or between the gate and the drain is selectively used to enable storage of information equivalent to the conventional two elements by one fuse element. Thus, a quaternary (4-value) or ternary (3-value) memory can be formed by one element.
  • FIG. 4A is a connection view of a PMOS electric fuse according to a first embodiment
  • FIG. 4B is a sectional view of the electric fuse schematically showing a voltage applied state during programming.
  • a source region (p-type impurity region) 3 and a drain region (p-type impurity region) 4 are formed to face with each other.
  • a gate electrode 6 is formed through a gate dielectric film 5 on an upper surface of a portion of the well 2 sandwiched between the source region 3 and the drain region 4 .
  • a material, dimensions and the like of the MOS structure can be similar to those of a MOS structure of a MOS device on which a fused is mounted, for example, by a 90-nm process. No special materials or dimensions need be employed for the electric fuse.
  • a similar program voltage VBP is applied to all of the gate electrode 6 , the drain region 4 , and the well 2 .
  • the voltage VBP′ applied to the drain region 6 , the well 2 is not necessarily the program voltage VBP, but the voltage may be power supply voltage VDD.
  • the voltage applied to the drain region 6 , and the well region 2 may be different.
  • a voltage applied to the gate electrode 6 can be 2 to 5 V, and a voltage applied to the source region 3 (or drain region 4 ) or the well can be 0 to 3 V.
  • the gate dielectric film is short-circuited to lower resistance.
  • a conductive/nonconductive ratio larger by 1000 times than a current ratio can be obtained.
  • FIGS. 5A and 5B shows an example of a reading operation.
  • the source region 3 , the drain region 4 , and the gate electrode 6 are precharged once to VSS, and subsequently a normal power supply voltage VDD is applied to the gate electrode 6 after the source region 3 and the drain region 4 are set in floating states.
  • a voltage of a programmed region e.g., source region 3
  • a nonprogrammed region e.g., drain region 4
  • This voltage difference is amplified by a sense amplifier, and fuse data is written into a flip-flop or the like. Accordingly, it is possible to read fuse information.
  • FIGS. 6A and 6B are a connection diagram and a sectional view when an NMOS is used. Similar portions are denoted by similar numerals, and duplicated explanation will be omitted.
  • VSS′ may be VSS (e.g., ground potential), or different from VSS. Additionally, voltages of the well 2 and the drain 4 may be different.
  • VBP is a positive potential.
  • the gate dielectric film breakdown mode of the MOS electric fuse is limited to the breakdown between the gate and the source (or drain), it is possible to make electric characteristics of the electric fuse uniform.
  • the high voltage is applied between the source and the gate to execute the programming.
  • programming can subsequently be executed between the drain and the gate.
  • whether the gate dielectric film between the gate and the source has been broken down or not has no influence at all on the breakdown operation between the gate and the drain.
  • the gate dielectric film between the gate and the source and the gate dielectric film between the gate and the drain can be independently broken down.
  • Such an example will be described in a second embodiment.
  • FIGS. 7A and 7B , and FIGS. 8A and 8B are schematic sectional views of an electric fuse illustrating a programming method of the MOS electric fuse according to a second embodiment.
  • FIGS. 7A and 7B show voltage applied states when a gate dielectric film on a source region is broken down (during source programming), which are similar to those of the first embodiment of FIGS. 4A and 4B except for application of VBP′ to a drain region.
  • the VBP′ may be equal to VBP, or VDD.
  • VBP′ applied to a well 2 and VBP′ applied to a drain region 4 may be different.
  • the voltage should form no channel between the source and the drain. By such voltage application, a source side is programmed.
  • FIGS. 8A and 8B show voltage applied states when a drain side is programmed.
  • the programming is similarly executed only by replacing the source and the drain by each other in FIGS. 7A and 7B .
  • dielectric film short-circuiting portions 7 are formed on both of the source and drain regions 3 and 4 .
  • FIGS. 9A and 9B are views showing an example of a reading operation when the drain side alone is programmed.
  • the source region 3 , the drain region 4 , and a gate electrode 6 are precharged to VSS.
  • a normal power supply voltage VDD is applied to the gate electrode 6 after the source region 3 and the drain region 4 are set in floating states.
  • a voltage of a programmed region (drain region 4 ) is quickly set to VDD, while a nonprogrammed region (source region 3 ) maintains a VSS state for a while.
  • This voltage difference is amplified by a sense amplifier, and fuse data is written into a flip-flop or the like. Accordingly, it is possible to read fuse information.
  • FIG. 10 is a block diagram of a semiconductor device on which an electric fuse and a functional circuit are mounted.
  • an electric fuse element 71 the source region 3 and the drain region 4 are output terminals.
  • the output terminals are connected to a data processing circuit 74 , which includes a sense amplifier, a flip-flop for storing electric fuse data, or the like, through control circuits 72 and 73 as functional circuits.
  • a gate electrode of one electric fuse element is connected to one control circuit 63 , and this control circuit 63 is connected to a data processing circuit 64 (see FIG. 13 ).
  • an information amount of 2 channels i.e., a maximum of 2 bits
  • the number of electric fuse elements necessary for holding the same information amount can be halved from that of the conventional case.
  • FIG. 11 is a circuit diagram showing an example of the control circuit, the data processing circuit of one channel of FIG. 10 .
  • a gate voltage of the electric fuse element 71 is set to VBP
  • VDD is applied to a gate of a driving transistor 81 in the control circuit 72
  • a high-level Prog signal is applied to a gate of a driving transistor 82 .
  • a gate signal Prech of a driving transistor 83 in the data processing circuit 71 is set to a high level, and the drain region 4 of the electric fuse element 71 is precharged to VSS.
  • a gate of the electric fuse 71 is also set to VSS.
  • a gate voltage of the electric fuse 71 is set to VDD, VDD is applied to the gate of the driving transistor 81 in the control circuit 72 , a Prog signal is set to a low level, and a voltage appearing in the drain region 4 of the electric fuse 71 is compared with a reference voltage Ref and amplified by a sense amplifier 84 , and then stored in a flip-flop 85 .
  • a one-time PROM can be configured.
  • an information amount of a maximum of 4 values (1, 1), (1, 0), (0, 1), and (0, 0) can be stored by one element, where “1” indicates conduction, and “0” indicates nonconduction.
  • a ternary (3-value) memory which uses three values of (0, 0), (1, 0), and (0, 1).
  • the data processing circuit 74 when the data processing circuit 74 is replaced by a spare decoder or a memory cell matrix, it can be applied to a redundancy circuit of a memory.
  • the second embodiment has been described by taking the example of the PMOS.
  • the electric fuse can include an NMOS.
  • FIGS. 12A to 12 C are connection and sectional views of an electric fuse according to a third embodiment.
  • the electric fuse is of an inversion type, and employs a 2-terminal configuration in which a source region 3 and a drain region 4 are connected to form one terminal, and a gate electrode 6 is an output terminal.
  • VSS is applied to each of the source region 3 , the drain region 4 and the gate electrode 6
  • a program voltage VBP is applied to a substrate (well) 2 .
  • the electric fuse comprises a PMOSFET
  • the VBP is a positive potential
  • a depletion layer spreads from the source region 3 and the drain region 4 , and dielectric breakdown can be generated limitedly in a gate dielectric film 5 on a substantial center between the source and the drain.
  • the well 2 , the source region 3 , the drain region 4 , and the gate electrode 6 are precharged to, e.g., VSS. Subsequently, the well 2 , the source region 2 , and the drain region 4 are set to, e.g., VDD, and a potential change of the output terminal gate electrode 6 is detected. The potential of the gate electrode 6 is changed to VDD if the gate dielectric film is short-circuited, and maintained at VSS if it is not short-circuited.
  • the electric fuse of the third embodiment since the short-circuiting place of the gate dielectric film is limited to the substantial center between the source and the drain while the one-element and one-channel scheme is employed, it is possible to realize an electric fuse of a small characteristic variance.
  • the third embodiment has been described by taking the example of the PMOS.
  • the electric fuse can include an NMOS.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
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  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
US10/973,412 2004-08-18 2004-10-27 MOS electric fuse, its programming method, and semiconductor device using the same Abandoned US20060038255A1 (en)

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JP2004238537A JP4383987B2 (ja) 2004-08-18 2004-08-18 Ｍｏｓ型電気ヒューズとそのプログラム方法
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Cited By (3)

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US9373412B2 (en) 2013-02-05 2016-06-21 Qualcomm Incorporated System and method of programming a memory cell
JP2017073192A (ja) * 2013-02-05 2017-04-13 クアルコム，インコーポレイテッド メモリセルをプログラムするシステムおよび方法
JP2017139046A (ja) * 2016-01-19 2017-08-10 力旺電子股▲分▼有限公司 アンチヒューズ型ワンタイムプログラマブルメモリセルをプログラムするための方法

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TWI325165B (en) * 2006-04-20 2010-05-21 Ememory Technology Inc Method for operating a single-poly single-transistor non-volatile memory cell
US8400813B2 (en) * 2009-02-10 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. One-time programmable fuse with ultra low programming current
US8471296B2 (en) 2011-01-21 2013-06-25 International Business Machines Corporation FinFET fuse with enhanced current crowding
JP2012174863A (ja) * 2011-02-21 2012-09-10 Sony Corp 半導体装置およびその動作方法
US8630108B2 (en) 2011-03-31 2014-01-14 International Business Machines Corporation MOSFET fuse and array element
US20140293673A1 (en) * 2013-03-28 2014-10-02 Ememory Technology Inc. Nonvolatile memory cell structure and method for programming and reading the same
CN104240762B (zh) * 2013-06-09 2018-06-01 中芯国际集成电路制造(上海)有限公司 反熔丝结构及编程方法
CN104347629B (zh) * 2013-07-24 2017-04-19 中芯国际集成电路制造(上海)有限公司 一种栅控二极管反熔丝单元结构及其制作方法
JP2018006525A (ja) 2016-06-30 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置
WO2020042078A1 (zh) * 2018-08-30 2020-03-05 深圳市为通博科技有限责任公司 存储单元、存储器件以及存储单元的操作方法
JP2020155727A (ja) * 2019-03-22 2020-09-24 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びこれを備えた電子機器

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Publication number Priority date Publication date Assignee Title
US9373412B2 (en) 2013-02-05 2016-06-21 Qualcomm Incorporated System and method of programming a memory cell
JP2017073192A (ja) * 2013-02-05 2017-04-13 クアルコム，インコーポレイテッド メモリセルをプログラムするシステムおよび方法
JP2017139046A (ja) * 2016-01-19 2017-08-10 力旺電子股▲分▼有限公司 アンチヒューズ型ワンタイムプログラマブルメモリセルをプログラムするための方法

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KR20060050421A (ko) 2006-05-19
CN100388416C (zh) 2008-05-14
TW200610008A (en) 2006-03-16
US20070258311A1 (en) 2007-11-08
KR100777858B1 (ko) 2007-11-21
CN1737993A (zh) 2006-02-22
JP4383987B2 (ja) 2009-12-16
US7573118B2 (en) 2009-08-11
JP2006059919A (ja) 2006-03-02

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