US20040232974A1 - Voltage generating circuit - Google Patents

Voltage generating circuit Download PDF

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Publication number
US20040232974A1
US20040232974A1 US10/822,826 US82282604A US2004232974A1 US 20040232974 A1 US20040232974 A1 US 20040232974A1 US 82282604 A US82282604 A US 82282604A US 2004232974 A1 US2004232974 A1 US 2004232974A1
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voltage
node
control signal
level
vcc
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Youichi Tobita
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TOBITA, YOUICHI
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

Definitions

  • the present invention relates to a voltage generating circuit for generating an internal voltage at a desired voltage level, and particularly to a structure of a voltage generating circuit efficiently generating an internal voltage by utilizing a charge pump operation of a capacitance element.
  • Semiconductor device are configured to use internal voltages at various voltage levels in many cases.
  • a negative voltage is used for biasing a substrate region of a memory cell array at a constant voltage, and a high positive voltage higher than a power supply voltage is supplied to a selected word line.
  • a nonvolatile memory negative and positive voltages are used for rewriting data.
  • semiconductor devices are generally configured to generate internally the voltages at required levels.
  • An example of the circuit generating such an internal voltage is disclosed in Reference 1 (Japanese Patent Laying-Open No. 4-372792).
  • An internal voltage generating circuit disclosed in Reference 1 generates a negative voltage by utilizing a charge pump operation of a capacitance element.
  • electric charges are accumulated in a charge-accumulation node through charge pump operation of a charging capacitance element.
  • a discharge control transistor is turned on through capacitance coupling of a controlling capacitance element to discharge the charge-accumulation node to a ground voltage level.
  • the charging capacitance element performs the charge pump operation to pull out the charges from the charge-accumulation node, to drive that node to a negative voltage level.
  • the charge-accumulation node is changed with an amplitude of the power supply voltage. Negative charges of this charge-accumulation node are supplied to an output node through an output transistor so that a negative voltage at a level of ⁇ VCC is supplied, where VCC represents the power supply voltage.
  • a gate potential of the output transistor changes between a ground voltage GND and a negative voltage ⁇ VCC under control of an output control transistor having a gate connected to the charge-accumulation node.
  • Reference 1 intends to generate a negative voltage at an adequate voltage level even under a low power supply voltage by changing the charge-accumulation node with an amplitude of VCC.
  • the charge-accumulation node in order to change the voltage level of the charge-accumulation node with an amplitude of ⁇ VCC, the charge-accumulation node is precharged to the ground voltage level by the discharge control transistor, and then is discharged to the voltage level of ⁇ VCC through the charge pump operation of the charging capacitance element.
  • a second control transistor is provided to be made conductive to connect the charge-accumulation node to the gate of the discharge control transistor.
  • the second control transistor is made conductive to connect electrically the gate of the discharging control transistor to the charge-accumulation node when the voltage on the charge-accumulation node lowers to or below ⁇ Vth, where Vth denotes a threshold voltage of the second control transistor.
  • the capacitance element receiving a control signal is connected to the discharge control transistor for turning on it. Therefore, the gate potential of this discharge control transistor changes at a time constant, which is determined by an on-resistance of the second control transistor and a capacitance existing at the gate of the discharge control transistor. Therefore, a certain time is required until the discharge control transistor is turned off. Accordingly, the discharge control transistor maintains the on-state for a certain time period while the charge-accumulation node is at the voltage level of ⁇ VCC, and a current flows to the charge-accumulation node from the ground node. This impedes the operation of extracting the charges through the charge pump of the charging capacitance element, and an ineffective current is consumed.
  • An object of the invention is to provide a voltage generating circuit, which can efficiently utilizes the charges, to generate a voltage at an intended level.
  • a voltage generating circuit includes a first transistor of a first conductivity type connected between a reference voltage node supplied with a predetermined voltage and a first internal node, and having a control electrode connected to a second internal node; a second transistor of the first conductivity type connected between the reference voltage node and the second internal node, and having a control electrode connected to the first internal node; a first capacitance element connected between a first input node receiving a first control signal for precharging and the first internal node; a second capacitance element connected between a second input node receiving a second control signal for charge accumulation and the second internal node; a third transistor of a second conductivity type connected between the second internal node and an output node, and having a control electrode connected to a third internal node; a third capacitance element connected between the third internal node and a third input node receiving a third control signal for charge transfer; and a fourth transistor of the second conductivity type connected between the
  • a voltage generating circuit includes a first transistor connected between a precharge voltage supply node supplying a precharge voltage and a first internal node, and having a control electrode connected to a second internal node; a first capacitance element connected between a first input node receiving a first control signal for precharging and a second internal node; a second transistor connected between the first and second internal nodes, and having a control electrode connected to a second input node receiving a second control signal for charge accumulation; a third transistor connected between the first internal node and an output node, and having a control electrode connected to a third internal node; a fourth transistor connected between the output node and the third internal node, and having a control electrode connected to the first internal node; a second capacitance element connected between a third input node receiving a third control signal for second charge precharging and the first internal node; and a third capacitance element connected between a fourth input node receiving a fourth control signal for charge
  • the voltage generating circuit through cross-coupling of the first and second transistors, and the first and second transistors can be turned on/off at optimal timing to change the voltages at the first and second internal nodes at high speed, to held at the changed voltage levels. Therefore, the second transistor is made off during the change in voltage on the second internal node serving as the charge-accumulation node, and then the charge pump operation is effected on the second internal node, so that unnecessary current can be prevented from flowing into the second internal node.
  • the first internal node is precharged with the precharging voltage, and is coupled with the third control signal via the second capacitance element. Further, the first internal node is connected to the control electrode of the fourth transistor. Therefore, the on/off state of the respective transistors can be individually controlled by the charge pump operation through the capacitance elements, and flow of an ineffective current can be suppressed so that the charges can be efficiently used to produce the internal voltage at the intended level.
  • FIG. 1 shows a construction of a voltage generating circuit according to a first embodiment of the invention.
  • FIG. 2 is a signal waveform diagram illustrating an operation of the voltage generating circuit shown in FIG. 1.
  • FIG. 3 shows a structure of a voltage generating circuit according to a second embodiment of the invention.
  • FIG. 4 is a signal waveform diagram illustrating an operation of the circuit shown in FIG. 3.
  • FIG. 5 schematically shows a construction of an internal voltage generating circuit according to a third embodiment of the invention.
  • FIG. 6 schematically shows a structure of a control signal generating circuit shown in FIG. 5.
  • FIG. 7 is a timing chart illustrating an operation of the circuit shown in FIG. 6.
  • FIG. 8 shows a construction of a voltage generating circuit according to a fourth embodiment of the invention.
  • FIG. 9 is a signal waveform diagram illustrating an operation of the circuit shown in FIG. 8.
  • FIG. 10A shows a construction of a voltage generating circuit according to a fifth embodiment of the invention
  • FIG. 10B shows a structure of a charge transfer stage shown in FIG. 10A.
  • FIG. 11 is a signal waveform diagram illustrating an operation of the circuits shown in FIGS. 10A and 10B.
  • FIG. 12 schematically shows a structure of a circuit generating a control signal shown in FIG. 10A.
  • FIG. 13 is a signal waveform diagram illustrating an operation of a circuit shown in FIG. 12.
  • FIG. 14 shows a construction of a voltage generating circuit according to a sixth embodiment of the invention.
  • FIG. 15 is a signal waveform diagram illustrating an operation of a circuit shown in FIG. 14.
  • FIG. 16 shows a structure of a voltage generating circuit according to a seventh embodiment of the invention.
  • FIG. 17 is a signal waveform diagram illustrating an operation of the circuit shown in FIG. 16.
  • FIG. 18 shows a structure of a voltage generating circuit according to an eighth embodiment of the invention.
  • FIG. 19 is a timing chart illustrating an operation of the voltage generating circuit shown in FIG. 18.
  • FIG. 20 shows a structure of a voltage generating circuit according to a ninth embodiment of the invention.
  • FIG. 21 is a timing chart representing an operation of the voltage generating circuit shown in FIG. 20.
  • FIGS. 22, 23 and 24 show constructions of voltage generating circuits according to tenth, eleventh and twelfth embodiments of the invention, respectively.
  • FIG. 25 shows a construction of a voltage generating circuit according to a modification of the twelfth embodiment of the invention.
  • FIG. 26 shows a construction of a voltage generating circuit according to a thirteenth embodiment of the invention.
  • FIG. 27 shows a structure of a voltage generating circuit according to a modification of the thirteenth embodiment of the invention.
  • FIG. 1 shows a structure of a voltage generating circuit according to a first embodiment of the invention.
  • the voltage generating circuit shown in FIG. 1 generates a negative voltage lower than a reference potential.
  • a ground potential GND is used as the reference potential, and a signal for controlling a charge pump operation changes between a ground voltage and a power supply voltage VCC so that a negative voltage of ⁇ VCC is produced.
  • the voltage generating circuit includes a P-channel MOS transistor (insulated gate field-effect transistor) PQ 1 connected between an internal node ND 1 and a reference potential node (referred to as a “ground node” hereinafter) GC and having a gate connected to an internal node ND 2 , a P-channel MOS transistor PQ 2 connected between internal node ND 2 and ground node GG and having a gate connected to internal node ND 1 , a capacitance element C 1 connected between a control signal input node S 1 receiving a precharging control signal ⁇ P and internal node ND 1 , and a capacitance element C 2 connected between a control signal input node S 2 receiving a control signal ⁇ CP for charge accumulation and internal node ND 2 .
  • a P-channel MOS transistor insulated gate field-effect transistor
  • MOS transistors PQ 1 and PQ 2 correspond to the first and second transistors, respectively, and capacitance elements C 1 and C 2 correspond to the first and second capacitance elements, respectively.
  • Control signals ⁇ P and ⁇ CP correspond to the first and second control signals, respectively.
  • Internal nodes ND 1 and ND 2 correspond to the first and second internal nodes, respectively.
  • the voltage generating circuit further includes an N-channel MOS transistor NQ 1 connected between internal node ND 2 and an output node OD 1 and having a gate connected to an internal node ND 3 , an N-channel MOS transistor NQ 2 connected between internal node ND 3 and output node OD 1 and having a gate connected to internal node ND 2 , and a capacitance element C 3 connected between a control signal input node S 3 receiving a control signal ⁇ CT for charge transference and internal node ND 3 .
  • MOS transistors NQ 1 and NQ 2 correspond to the third and fourth transistors, respectively, capacitance element C 3 corresponds to the third capacitance element, and control signal ⁇ CT corresponds to the third control signal.
  • a capacitance element C 4 is connected between output node OD 1 and the ground node. This capacitance element C 4 serves to stabilize an output voltage of ⁇ VCC against variation of an output load, and may be eliminated if the variation in output load is small and therefore, the variation in output voltage of ⁇ VCC is small.
  • a voltage on output node OD 1 is applied to internal circuitry, not shown.
  • Each of control signals ⁇ P, ⁇ CP and ⁇ CT changes between ground voltage GND and power supply voltage VCC.
  • FIG. 2 is a timing chart illustrating an operation of the voltage generating circuit shown in FIG. 1.
  • FIG. 2 shows operation waveforms for the case when the voltage on output node OD 1 is at the predetermined voltage level of ⁇ VCC.
  • FIG. 2 an operation of the voltage generating circuit shown in FIG. 1 will now be described.
  • Control signals ⁇ P, ⁇ CP and ⁇ CT change at a cycle of T.
  • FIG. 2 illustrates signal waveforms over a time period of 2 ⁇ T.
  • control signals ⁇ P, ⁇ CP and ⁇ CT are at the levels of ground voltage GND, power supply voltage VCC and ground voltage GND, respectively.
  • node ND 1 is at the voltage level of ⁇ VCC
  • node ND 2 is at the voltage level of ground voltage GND.
  • node ND 1 serves as a drain node
  • ground node GG serves as a source node.
  • P-channel MOS transistor PQ 1 is of an enhancement type, and has a threshold voltage of a predetermined magnitude. Therefore, P-channel MOS transistor PQ 1 maintains the non-conductive state due to equal potentials at its gate and source, and no current flows between node ND 1 and ground node GG.
  • MOS transistor PQ 2 receives a negative potential ⁇ VCC at its gate, and equal potentials at its drain (node ND 2 ) and source (ground node) so that no current flows between the drain and source of MOS transistor PQ 2 .
  • N-channel MOS transistor NQ 1 As for N-channel MOS transistor NQ 1 , node ND 2 is at the level of ground voltage GND, output node OD 1 is at the level of negative voltage ⁇ VCC and node ND 3 is at the level of negative voltage ⁇ VCC.
  • N-channel MOS transistor NQ 1 is of an enhancement type, has a threshold voltage of a constant magnitude, and maintains the non-conductive state when the gate potential is equal to the source potential.
  • N-channel MOS transistor NQ 2 has a gate potential at the level of the voltage on node ND 2 or the level of ground voltage GND, and has the drain and source at the equal potential because node ND 3 and output node OD 1 are at equal potential levels. Thus, no current flows between the drain and source of MOS transistor NQ 2 .
  • MOS transistor PQ 2 is made conductive to precharge node ND 2 to the ground voltage level. In an initial stage of the charge pumping operation, the precharge voltage level of node ND 2 is lowered toward the ground voltage.
  • node ND 1 is at the voltage level not lower than ground voltage GND, and node ND 1 and the ground node serve as the source and drain of MOS transistor PQ 1 , respectively.
  • the voltage level of node ND 2 is high in this state.
  • MOS transistor PQ 1 is of the enhancement type, receives the gate to source voltage not higher than an absolute value of the threshold voltage, and maintains the non-conductive state. Thus, no current flows between the drain and the source of MOS transistor PQ 1 .
  • MOS transistor PQ 2 Since node ND 2 is at the level of ground voltage GND, MOS transistor PQ 2 has the drain and the source at equal potentials, and no current flows between the drain and source of MOS transistor PQ 2 even when the voltage level of node ND 1 rises from negative voltage ⁇ VCC to the ground voltage GND. By raising control signal ⁇ P, MOS transistor PQ 2 is made non-conductive for preparing for the next charge pump operation on node ND 2 .
  • Node ND 2 holds the level of ground voltage GND, and node ND 3 is at the negative voltage level.
  • MOS transistor NQ 2 is conductive, and electrically connects output node OD 1 to internal node ND 3 , so that internal node ND 3 becomes equal in voltage level to output node OD 1 .
  • MOS transistor NQ 1 reliably maintains the non-conductive state.
  • the gate to source voltage of MOS transistor NQ 1 is maintained at or below the threshold voltage to prevent MOS transistor NQ 1 of the enhancement type from turning on before transferring charges, even when internal node ND 2 is driven to the negative voltage level and internal node ND 2 serves as the source of MOS transistor NQ 1 .
  • MOS transistor NQ 1 may be rendered conductive. In this case, however, negative charges are merely transferred to output node OD 1 before generation of control signal ⁇ CT, and the charges are utilized for lowering the output voltage. Thus, the charges are effectively utilized.
  • control signal ⁇ CP lowers from the level of power supply voltage VCC to the level of ground voltage GND, and the charge pumping by capacitance element C 2 lowers the voltage level of node ND 2 .
  • the voltage level of node ND 2 changes from ground voltage GND to a negative voltage, both the drain and source of MOS transistor PQ 1 is at the level of ground voltage GND, and no current flows between its drain and source.
  • MOS transistor PQ 2 Since MOS transistor PQ 2 has node ND 2 serving as the drain, the gate and source (ground node) are both at the level of ground voltage. MOS transistor PQ 2 is of the enhancement type, and has the gate-source voltage smaller than the absolute value of its threshold voltage so that MOS transistor PQ 2 maintains the non-conductive state. Accordingly, node ND 2 lowers to the level of negative voltage ⁇ VCC through the charge pump operation of capacitance element C 2 . In this state, node ND 3 is at the level of negative voltage ⁇ VCC, and MOS transistor NQ 1 has output node OD 1 serving as the source, has the gate and source at the equal potentials, and maintains the non-conductive state.
  • MOS transistor NQ 1 is of the enhancement type, and has the gate-source voltage smaller than the threshold voltage during the transition and stable stages, and maintains the non-conductive state so that node ND 2 can be accurately driven to the negative voltage level.
  • MOS transistor PQ 1 When node ND 2 is driven to the negative voltage level in the transition time period, MOS transistor PQ 1 is made conductive to lower the voltage level of node ND 1 if the voltage level of node ND 1 is higher than the ground voltage.
  • MOS transistor NQ 2 the drain and source are at the same level of negative voltage ⁇ VCC, so that no current flows between the drain and source.
  • control signal ⁇ CT rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • control signal ⁇ P is at the level of power supply voltage VCC
  • control signal ⁇ CP is at the level of ground voltage GND.
  • the charge pumping by capacitance element C 3 raises the voltage level of node ND 3 from negative voltage ⁇ VCC to the level of ground voltage GND. Since node ND 2 is at the level of negative voltage ⁇ VCC, MOS transistor NQ 1 is rendered conductive to couple node ND 2 to output node OD 1 .
  • output node OD 1 If the voltage level of output node OD 1 is higher than negative voltage ⁇ VCC, negative electric charges move from output node OD 1 to node ND 2 , so that output node OD 1 and node ND 2 attain the equal voltage level. Specifically, in the stable state, output node OD 1 is at the voltage level of ⁇ VCC. In this case, MOS transistor NQ 2 has the gate and source at the equal potentials, and therefore maintains the non-conductive state so that no current flows between the drain and source of MOS transistor NQ 2 .
  • MOS transistor NQ 2 In a transition period such as a start of the charge pumping, MOS transistor NQ 2 has internal node ND 3 serving as the drain, has the gate in potential lower than the source upon start of charge transfer start, and maintains the non-conductive state. Even if the gate and source are made equal in potential to each other through charge transfer, MOS transistor NQ 2 maintains the non-conductive state due to its threshold voltage, and does not adversely affect the charge transfer operation.
  • node ND 3 is driven to the power supply voltage level in accordance with control signal ⁇ CT, and negative charges can be efficiently supplied to output node OD 1 to produce negative voltage ⁇ VCC of the intended voltage level.
  • control signal ⁇ CT falls from the level of power supply voltage VCC to the level of ground voltage GND, and the voltage level of node ND 3 lowers from ground voltage GND to negative voltage ⁇ VCC.
  • the lowest possible potential of the source node (node ND 2 ) of MOS transistor NQ 1 is the negative voltage ⁇ VCC, and MOS transistor NQ 1 is reliably made non-conductive.
  • MOS transistor NQ 2 has the drain and source at the levels of negative voltage ⁇ VCC, and causes no current flow therethrough.
  • node ND 3 In the transition period at the start of the charge pumping, when nodes ND 2 and OD 1 are at the voltage levels higher than negative voltage ⁇ VCC, node ND 3 merely returns to the voltage level of output node OD 1 in the preceding cycle, and MOS transistor NQ 2 has output node OD 1 serving as the source, and has the gate and source equal in potential, and maintains the non-conductive state. Even when MOS transistor NQ 1 is turned on, output node OD 1 and internal node ND 2 , which serve as the source and drain of MOS transistor NQ 1 , respectively, are at the same voltage level, and no current flow through MOS transistor NQ 1 . In the transition period, the voltage level, to which node ND 3 returns, is the voltage level at which MOS transistor NQ 1 is set non-conductive, and no charge is wasted.
  • control signal ⁇ CP rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • control signal ⁇ P is at the level of power supply voltage VCC.
  • Control signal ⁇ CT is at the level of ground voltage GND.
  • MOS transistor PQ 1 has both the drain and source kept at the level of ground voltage GND, and turns non-conductive in accordance with the rising of its gate potential. Thus, no current flows through MOS transistor PQ 1 .
  • MOS transistor PQ 2 the voltage level of node ND 2 merely rises from negative voltage ⁇ VCC to ground voltage GND, and does not exceed the ground voltage GND, so that the ground node serves as the source of MOS transistor PQ 2 , which in turn maintains the non-conductive state.
  • node ND 2 When node ND 2 is raised in potential, node ND 2 may be held at a voltage level higher than ground voltage GND (node ND 2 serves as a source) in the transition period such as a start period of the charge pumping operation. In this case, control signal ⁇ P is lowered to render MOS transistor PQ 2 conductive so that node ND 2 is reliably discharged toward the ground voltage level. Therefore, a particular problem does not occur.
  • node ND 3 is at the level of negative voltage ⁇ VCC so that MOS transistor NQ 1 maintains the non-conductive state.
  • internal node ND 3 is at the voltage level of output node OD 1 , i.e., the level of negative voltage ⁇ VCC so that MOS transistor NQ 2 has the gate and the source at the equal voltages, and thus maintains the non-conductive state. Therefore, no current flows between the drain and source of MOS transistor NQ 2 .
  • control signal ⁇ P falls to the level of ground voltage GND. Accordingly, capacitance element C 1 lowers the voltage level of node ND 1 from ground voltage GND to negative voltage ⁇ VCC. In accordance with this voltage lowering of node ND 1 , MOS transistor PQ 2 turns conductive, and node ND 2 is reliably set to the level of ground voltage GND.
  • node ND 2 Even in the case where node ND 2 is driven to a high voltage level higher than ground voltage GND in the transition period, the voltage level of node ND 2 can be reliably lowered. In the next cycle, the voltage level of node ND 2 can be further lowered in accordance with control signal ⁇ CP, and the output voltage level can be lowered.
  • MOS transistor PQ 1 In the potential lowering of node ND 2 , MOS transistor PQ 1 has the ground node serving as its source, and accordingly has the gate and the source at the same voltage level, so that MOS transistor PQ 1 maintains the non-conductive state.
  • MOS transistors PQ 1 and PQ 2 are cross-coupled, and the gate potentials thereof are individually set by the charge pump operations of the capacitance elements. After these MOS transistors PQ 1 and PQ 2 are made non-conductive, the voltage levels of nodes ND 1 and ND 2 can be reliably and rapidly changed in accordance with the control signals.
  • Control signal ⁇ CP determining the voltage amplitude of internal node ND 2 is changed between power supply voltage VCC and ground voltage GND.
  • the reference voltage being a voltage Vr instead of ground voltage GND
  • control signal ⁇ CP having a voltage amplitude V ⁇ an output voltage VOUT of output node OD 1 can be expressed by the following relation (1):
  • reference voltage Vr is equal to ground voltage GND or 0 V
  • control signal ⁇ CP is produced from a circuit using power supply voltage VCC and ground voltage GND as operation power supply voltages. Therefore, assuming that voltage amplitude V ⁇ is equal to power supply voltage VCC, the above relation (1) can be modified into the following relation (2);
  • control signals ⁇ P, ⁇ CP and ⁇ CT change between power supply voltage VCC and ground voltage GND, and are the same voltage levels in the high level and in the low level.
  • the high levels of these control signals ⁇ P, ⁇ CP and ⁇ CT may be different in voltage level from each other, and the low levels thereof may be different in voltage level from each other, provided that MOS transistors PQ 1 , PQ 2 , NQ 1 and NQ 2 are made non-conductive to prevent current flow in a direction reverse to that of voltage change upon the voltage change on internal nodes ND 1 , ND 2 and ND 3 .
  • the cross-coupled P-channel MOS transistors are used, and the gate node potentials thereof are determined by the charge pump operations of the capacitance elements.
  • the conduction/non-conduction states of the output transistor are set by the control signal.
  • FIG. 3 shows a structure of a voltage generating circuit according to a second embodiment of the invention.
  • the voltage generating circuit shown in FIG. 3 uses power supply voltage VCC as a reference voltage, and generates a high voltage of 2 ⁇ VCC higher than power supply voltage VCC.
  • the voltage generating circuit includes an N-channel MOS transistor NQ 11 connected between a power supply node (reference node) PW and an internal node (first internal node) ND 11 and having a gate connected to an internal node (second internal node) ND 12 , an N-channel MOS transistor NQ 12 connected between a power supply node PW and an internal node ND 12 and having a gate connected to internal node ND 11 , a capacitance element (first capacitance element) C 11 connected between a control signal input node (first control signal input node) S 11 receiving a first control signal ⁇ PZ and internal node ND 11 , and a capacitance element (second capacitance element) C 12 connected between a control signal input node (second control signal input node) S 12 receiving a control signal ⁇ CPZ and internal node ND 12 .
  • Control signals ⁇ PZ and ⁇ CPZ each change between power supply voltage VCC and ground voltage GND.
  • the voltage generating circuit further includes a P-channel MOS transistor (third transistor) PQ 11 connected between internal node ND 12 and an output node OD 11 and having a gate connected to an internal node (third internal node) ND 13 , a P-channel MOS transistor (fourth transistor) PQ 12 connected between internal node ND 13 and output node OD 11 and having a gate connected to internal node ND 12 , and a capacitance element (third capacitance element) C 13 connected between a control signal input node (third control signal internal node) S 13 receiving a control signal ⁇ CTZ and internal node ND 13 .
  • a P-channel MOS transistor (third transistor) PQ 11 connected between internal node ND 12 and an output node OD 11 and having a gate connected to an internal node (third internal node) ND 13
  • a P-channel MOS transistor (fourth transistor) PQ 12 connected between internal node ND 13 and output node OD 11 and having a gate connected to internal no
  • Control signal ⁇ CTZ changes between power supply voltage VCC and ground voltage GND.
  • Output node OD 11 is provided with a stabilizing capacitance C 14 for stabilizing a voltage on output node OD 11 .
  • This stabilizing capacitance C 14 may not be provided if variation in load on output node OD 1 is small.
  • a voltage generating circuit shown in FIG. 3 is equivalent to the voltage generating circuit shown in FIG. 1, provided that the conductivity types of transistors are inverted, and the ground node and the power supply node are replaced with each other.
  • Control signals ⁇ PZ, ⁇ CP and ⁇ CT are complementary to control signals ⁇ P, ⁇ CPZ and ⁇ CTZ shown in FIG. 1.
  • FIG. 4 is a signal waveform diagram illustrating an operation of the voltage generating circuit shown in FIG. 3.
  • FIG. 4 also illustrates signal waveforms in the case when the output voltage is stable at the level of 2 ⁇ VCC. Referring to FIG. 4, an operation of the voltage generating circuit shown in FIG. 3 will now be described.
  • control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ are at the levels of power supply voltage VCC, ground voltage GND and power supply voltage VCC, respectively.
  • node ND 11 is at a high voltage level of 2 ⁇ VCC
  • node ND 12 is at a level of power supply voltage VCC (in the stable state).
  • MOS transistor NQ 11 has a power supply node PW serving as a source, and has gate and source at the same voltage level, and is made non-conductive.
  • MOS transistor NQ 12 Even if MOS transistor NQ 12 receives potential of high voltage of 2 ⁇ VCC at a gate, the voltage levels of node ND 12 and power supply node PW are equal to each other, so that no current flows between the drain and source of MOS transistor NQ 12 .
  • Node ND 13 is at the level of high voltage of 2 ⁇ VCC, and MOS transistor PQ 11 has a gate not lower in potential than the source and drain, and maintains the non-conductive state.
  • node ND 12 is at the level of power supply voltage VCC, and therefore MOS transistor PQ 12 is conductive.
  • the voltage levels of node ND 13 and output node OD 11 are equal to each other, so that no current flows through MOS transistor PQ 12 .
  • MOS transistor PQ 12 In this operation, the flow of current through MOS transistor PQ 12 stops when the voltage levels of output node OD 11 and node ND 13 become equal to each other. In this state, since output node OD 11 serves as the source of MOS transistor PQ 11 , MOS transistor PQ 11 has the gate and source potentials made equal to each other, and maintains the non-conductive state.
  • control signal ⁇ PZ falls from the level of power supply voltage VCC to the level of ground voltage GND.
  • MOS transistor NQ 11 turns non-conductive, and the charge pumping by capacitance element C 11 lowers the voltage level of node ND 11 from the high voltage of 2 ⁇ VCC to power supply voltage VCC.
  • node ND 12 is at the level of power supply voltage VCC, and MOS transistor NQ 12 is non-conductive. The potential of node ND 12 causes no change, and no ineffective current flows in this state.
  • control signal ⁇ CPZ rises from the level of ground voltage GND to the level of power supply voltage VCC, and the voltage level of node ND 12 rises from power supply voltage VCC to the high voltage of 2 ⁇ VCC.
  • MOS transistor PQ 12 has the gate set at a potential not lower than the source and drain potentials, and is reliably set to the non-conductive state.
  • MOS transistor PQ 11 has the gate at the high voltage of 2 ⁇ VCC.
  • MOS transistor PQ 11 has node ND 12 serving as the source thereof, has the gate made equal in potential to the source, and therefore, maintains the non-conductive state.
  • MOS transistor PQ 12 turns non-conductive due to the potential rising of node ND 12 .
  • Output node OD 11 and internal node ND 13 are already connected electrically, and are set at the same voltage level.
  • MOS transistor PQ 11 in this state has the gate-source voltage at most at a level lower in absolute value than the threshold voltage thereof, and maintains the non-conductive state.
  • MOS transistors NQ 11 , NQ 12 , PQ 11 and PQ 12 each are of the enhancement type and turn non-conductive only when the gate-source voltage thereof attains equal to or higher in absolute value than the threshold voltage.
  • control signal ⁇ CTZ falls from the level of power supply voltage VCC to the level of ground voltage GND.
  • the charge pumping by capacitance element C 13 lowers the voltage level of node ND 13 from the high voltage of 2 ⁇ VCC to power supply voltage VCC, and MOS transistor PQ 11 has the gate much lower in potential than the source thereof, to turn conductive for coupling electrically node ND 12 to output node OD 11 .
  • control signal ⁇ CTZ rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • the charge pumping by capacitance element C 13 raises the voltage level of node ND 13 from power supply voltage VCC to the high voltage of 2 ⁇ VCC.
  • MOS transistor PQ 11 has the gate equal to or higher in potential than the source thereof, and turns non-conductive.
  • MOS transistor PQ 12 turns conductive. Even in this state, however, positive charges are supplied from node ND 13 to output node OD 11 , to raise the voltage level of output node OD 11 .
  • MOS transistor PQ 12 of the enhancement type has the gate-source voltage not higher than the absolute value of the threshold voltage, and maintains the non-conductive state.
  • MOS transistor PQ 11 has the gate equal to or higher in potential than the source (output node OD 11 ), and therefore maintains the non-conductive state. Thus, no ineffective current flows from output node OD 11 to internal node ND 12 .
  • control signal ⁇ CPZ falls from the level of power supply voltage VCC to the level of ground voltage GND.
  • the charge pumping by capacitance element C 12 lowers the voltage level of node ND 12 from the high voltage of 2 ⁇ VCC to power supply voltage VCC.
  • Node ND 11 is at the level of power supply voltage VCC.
  • MOS transistor NQ 12 has the source and gate equal in potential to each other, and maintains the non-conductive state.
  • MOS transistor PQ 12 becomes lower than the voltage level of its source (output node OD 11 ), and MOS transistor PQ 12 is turns conductive to connect electrically output node OD 11 to internal node ND 13 .
  • MOS transistor PQ 11 has the gate and source made equal in potential to each other, and thus maintains the non-conductive state. Therefore, even when internal node ND 13 is charged, only a current, which is required for accurately transferring charges to the output node, flows and no ineffective current flows.
  • MOS transistor PQ 11 In the transition period, even if the voltage level of node ND 13 becomes lower than the voltage level of internal node ND 12 in boosting of the voltage level of internal node ND 12 through control signal ⁇ CPZ, MOS transistor PQ 11 is held non-conductive (the gate-source voltage is kept not higher than the absolute value of the threshold voltage).
  • node ND 12 may lower below power supply voltage VCC when the voltage on output node OD 11 has not yet reached the final voltage level.
  • node ND 11 is at the level of the power supply voltage
  • node ND 12 is held at the voltage level lower than power supply voltage VCC by the threshold voltage of MOS transistor NQ 12 .
  • a current, which flows in this state, is only supplied from power supply node PW through MOS transistor 12 , to compensate for the voltage level. No ineffective current flows.
  • control signal ⁇ PZ rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • the charge pumping by capacitor element C 11 raises the voltage level of node ND 11 from power supply voltage VCC to the high voltage level of 2 ⁇ VCC so that MOS transistor NQ 12 is turned on, and node ND 12 is reliably set to the level of power supply voltage VCC.
  • control signal ⁇ CPZ is determined in accordance with a required voltage level.
  • power supply node PW is at a level of power supply voltage VCC
  • control signal ⁇ CPZ has the amplitude of power supply voltage VCC so that output voltage VOUT can be represented by the following relation (4):
  • VOUT 2 ⁇ VCC (4)
  • control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ are equal in voltage to each other in the high level and in the low level.
  • the high levels and the low levels of control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ may be different from each other, provided that the precharging of internal node ND 12 , supplying of charges and transferring of the charges can be performed while ensuring the on/off states of MOS transistors NQ 11 , NQ 12 , PQ 11 and PQ 12 .
  • the N-channel MOS transistors are cross-coupled, the charging of the charge-accumulation node is performed by utilizing the charge pump operation of the capacitance element.
  • the charges can be supplied to the charge-accumulation node after the MOS transistors are turned non0-conductive. Thus, flow of an ineffective current can be prevented, and a positive high voltage can be efficiently generated.
  • FIG. 5 schematically shows a structure of an internal voltage generating circuit according to a third embodiment of the invention.
  • the internal voltage generating circuit includes a control signal generating circuit 1 for producing control signals ⁇ P, ⁇ CP and ⁇ CT in accordance with a repetition signal ⁇ 0 , a negative voltage generating circuit 10 for generating a negative voltage ⁇ VCC in accordance with control signals ⁇ P, ⁇ CP and ⁇ CT received from control signal generating circuit 1 , an inverting circuit 15 for inverting control signals ⁇ P, ⁇ CP and ⁇ CT to produce control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ, respectively, and a positive voltage generating circuit 20 for producing a positive voltage of 2 ⁇ VCC in accordance with control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ applied from inverting circuit 15 .
  • Negative voltage generating circuit 10 has a construction similar to that of the voltage generating circuit shown in FIG. 1, and positive voltage generating circuit 20 has a construction similar to that of the voltage generating circuit shown in FIG. 3.
  • Control signal generating circuit 1 is provided commonly to negative and positive voltage generating circuits 10 and 20 .
  • the internal voltages at intended levels of-VCC and 2 ⁇ VCC can be efficiently produced with a reduced occupation area.
  • FIG. 6 schematically shows a construction of control signal generating circuit 1 shown in FIG. 5.
  • control signal generating circuit 1 includes cascaded delay circuits 30 a - 30 d of four stages for receiving repetition signal ⁇ 0 , an inverter 32 a receiving an output signal ⁇ 1 of delay circuit 30 a , an inverter 32 b receiving an output signal ⁇ 3 of delay circuit 30 c , and an OR circuit 33 receiving the output signal of inverter 32 a and an output signal ⁇ 4 of delay circuit 30 d to produce control signal ⁇ CP, and an AND circuit 34 receiving output signal ⁇ 2 of delay circuit 30 b and the output signal of inverter 32 b to produce control signal ⁇ CT.
  • Each of delay circuits 30 a - 30 d is formed of an even number of stages of cascaded inverters, and has a delay time DT.
  • FIG. 7 is a signal waveform diagram illustrating an operation of control signal generating circuit 1 shown in FIG. 6. Referring to FIG. 7, the operation of control signal generating circuit 1 shown in FIG. 6 will now be described.
  • Repetition signal ⁇ 0 has a constant period, and is used also as control signal ⁇ P for precharging.
  • Delay circuits 30 a - 30 d delay the received signals by a predetermined time DT to produce delayed signals ⁇ 1 - ⁇ 4 , respectively.
  • OR circuit 33 receives the output signal of inverter 32 a and output signal ⁇ 4 of delay circuit 30 d to produce control signal ⁇ CP for accumulating charges. Therefore, the period in which control signal ⁇ CP is at an L level (logical low level), is provided by the period in which output signal ⁇ 4 of delay circuit 30 d is at an L level and output signal ⁇ 1 of delay circuit 30 a is at an H level (logical high level). Therefore, control signal ⁇ CP falls to the L level when output signal ⁇ 1 of delay circuit 30 a rises to the H level, and rises to the H level when output signal ⁇ 4 of delay circuit 30 a rises to the H level. Accordingly, control signal ⁇ P is maintained at the L level for a time period of 3 ⁇ DT.
  • Control signal ⁇ CT applied from AND circuit 34 for the charge transfer is at the H level when output signal ⁇ 2 of delay circuit 30 b is at the H level and the output signal of inverter 32 b is at the H level. Therefore, control signal ⁇ CT attains the H level when output signal ⁇ 2 of delay circuit 30 b rises to the H level, and attains the L level when output signal ⁇ 3 of delay circuit 30 c attains the H level. Control signal ⁇ CT is maintained at the H level for the period of DT.
  • the high levels of output signals ⁇ 1 - ⁇ 4 of delay circuits 30 a - 30 d are at the level of power supply voltage VCC, and the low levels thereof are at the level of ground voltage GND.
  • control signals ⁇ P, ⁇ CP and ⁇ CT the high level is at the level of power supply voltage VCC and the low level is at a level of ground voltage GND.
  • Repetition signal ⁇ 0 may be produced from an internal oscillator circuit, or may be formed of a clock signal externally, repetitively supplied for the signal transfer, setting of operation cycles and others.
  • Positive voltage generating circuit 20 operates in accordance with control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ produced by inverting control signals ⁇ P, ⁇ CP and ⁇ CT, respectively.
  • control signals ⁇ PZ, ⁇ CPZ and ⁇ CTZ produced by inverting control signals ⁇ P, ⁇ CP and ⁇ CT, respectively.
  • delay circuits 30 a - 30 d have the same delay time DT.
  • Delay circuits 30 a - 30 d may have different delay times from each other, provided that the following control signal generation sequence is satisfied.
  • control signal ⁇ CP for precharging changes.
  • the voltage level of control signal ⁇ CT for the charge transfer changes to perform the charge transfer.
  • control signal ⁇ CT for the charge transfer turns inactive, the logical level of control signal ⁇ CP for the charge accumulation changes, and thereafter the voltage level of precharging control signal ⁇ CP changes and the precharging is performed.
  • Such sequence is required to be achieved.
  • the internal voltage generating circuit shown in FIG. 5 includes negative and positive voltage generating circuits 10 and 20 for producing negative voltage ⁇ VCC and positive voltage of 2 ⁇ VCC, respectively. However, even in the case where only one of negative and positive voltage generating circuits 10 and 20 is employed, the internal voltage at an intended level can be efficiently generated by utilizing the control signal generating circuit 1 .
  • the internal voltage generated may be at a level different from ⁇ VCC and 2 ⁇ VCC.
  • the delay circuits are cascaded, and the signals in an intended phase relationship are logically processed to produce the control signals for the charge precharging, charging and transferring. Therefore, the control signals for the charge pump operation for generating the internal voltages can be easily produced with a simple circuit construction.
  • FIG. 8 shows a structure of a voltage generating circuit according to a fourth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 8 differs from the voltage generating circuit shown in FIG. 1 in that a voltage drive stage 40 for increasing an absolute value of a produced internal voltage is further arranged between output node OD 1 and a final output node FOD.
  • a voltage drive stage 40 includes a capacitance element C 20 connected between a control signal input node S 31 receiving control signal ⁇ P and output node OD 1 , an N-channel MOS transistor NQ 31 connected between internal output node OD 1 and final output node FOD and having a gate connected to an internal node ND 30 , an N-channel MOS transistor NQ 32 connected between internal node ND 30 and final output node FOD and having a gate connected to internal output node OD 1 , and a capacitance element C 21 connected between a control signal input node S 32 receiving a control signal ⁇ CTF and internal node ND 30 .
  • Final output node FOD is provided with a stabilizing capacitance C 4 , similarly to the first embodiment.
  • stabilizing capacitance C 4 may be eliminated if variation in output load is small.
  • Control signal ⁇ CTF turns active when negative charges are to be supplied from final output node FOD to internal output node OD 1 .
  • Control signals ⁇ P, ⁇ CP and ⁇ CT are the same as those in the first embodiment.
  • FIG. 9 is a timing diagram illustrating an operation of the voltage generating circuit shown in FIG. 8. Referring to FIG. 9, description will now be given on the operation of the voltage generating circuit shown in FIG. 8. FIG. 9 illustrates also signal waveforms in the stable state over a time period of 2 ⁇ T. The following description will be given on the operation in the stable state. In a transition period in the initial stage of the charge pumping operation, an operation is performed as in the stable state although the respective nodes attain different voltage levels.
  • Control signals ⁇ P, ⁇ CP and ⁇ CT are the same as those in the first embodiment, and therefore, the operation itself of the circuitry upstream to output node OD 1 is substantially the same as that in the first embodiment. However, the voltage amplitude of internal output node OD 1 is different from that in the first embodiment so that the voltage change on internal node ND 3 is different from that in the first embodiment.
  • control signals ⁇ P and ⁇ CT are set to the L level, and control signal ⁇ CP is set to the H level.
  • node ND 1 is at the level of negative voltage ⁇ VCC
  • output node OD 1 is at the negative voltage level of ⁇ 2 ⁇ VCC. Therefore, node ND 1 is driven to the level of negative voltage ⁇ VCC, and node ND 2 is precharged to the level of ground voltage GND.
  • internal output node OD 1 is at the negative voltage of ⁇ 2 ⁇ VCC
  • MOS transistor NQ 2 is conductive, and internal node ND 3 is electrically connected to internal output node OD 1 , and is held at the same voltage level.
  • MOS transistor NQ 1 is maintained in the non-conductive state.
  • control signal ⁇ P rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • capacitance element C 1 drives node ND 1 to the level of ground voltage GND, and the precharge operation on node ND 2 is completed.
  • a capacitance element C 20 raises the voltage level of output node OD 1 from ⁇ 2 ⁇ VCC to ⁇ VCC.
  • node ND 2 is at the level of ground voltage GND, and MOS transistor NQ 2 maintains the conductive state so that internal node ND 3 attains the same voltage level as internal output node OD 1 , and attains the level of negative voltage ⁇ VCC.
  • MOS transistor NQ 1 has the gate (node ND 3 ) and source (internal output node OD 1 ) set to the same potential, and maintains the non-conductive state.
  • control signal ⁇ CP falls from the level of power supply voltage VCC to the level of ground voltage GND, and node ND 12 is driven to the level of negative voltage ⁇ VCC so that N-channel MOS transistor NQ 2 turns non-conductive.
  • node ND 2 is at the level of negative voltage ⁇ VCC, and all the gate, source and drain of MOS transistor NQ 1 are at the same potential in the stable state, so that MOS transistor NQ 1 maintains the non-conductive state.
  • MOS transistor NQ 1 has the gate-source voltage not exceeding the threshold voltage as in the first embodiment, and maintains the non-conductive state.
  • control signal ⁇ CT rises from the level of ground voltage GND to the level of power supply voltage VCC, and the voltage level of node ND 3 rises from negative voltage ⁇ VCC to ground voltage GND.
  • MOS transistor NQ 1 turns conductive to connect electrically node ND 2 to output node OD 1 , and internal node ND 2 and internal output node OD 1 are made the same in voltage level.
  • internal output node OD 1 is already precharged to the level of negative voltage ⁇ VCC, and the drain potential and source potential of MOS transistor NQ 1 are made equal to each other so that a current does not flow therethrough in the steady state.
  • control signal ⁇ CT falls from the level of power supply voltage VCC to the level of ground voltage GND, and the voltage level of node ND 3 lowers from ground voltage GND to negative voltage ⁇ VCC.
  • MOS transistor NQ 1 turns non-conductive to isolate node ND 2 from internal output node OD 1 .
  • MOS transistor NQ 2 In the stable state, MOS transistor NQ 2 have the gate, drain and source set at the same potential, and does not pass a current.
  • control signal ⁇ CP rises from the level of ground voltage GND to the level of power supply voltage VCC, and the voltage level of node ND 2 rises from the negative voltage ⁇ VCC to ground voltage GND.
  • MOS transistor PQ 1 is turned off for preparing for a next precharge operation.
  • MOS transistor NQ 2 is turned on to connect electrically internal node ND 3 and internal output node OD 1 , and internal node ND 3 attains the same voltage level as that on internal output node OD 1 , i.e., the level of negative voltage ⁇ VCC so that MOS transistor NQ 1 has the gate and source set at the same voltage, and is kept non-conductive.
  • control signal ⁇ P falls from the level of power supply voltage VCC to the level of ground voltage GND, and responsively the voltage on node ND 1 lowers from the level of ground voltage GND to the level of negative voltage ⁇ VCC.
  • capacitance element C 20 lowers internal output node OD 1 from the level of the shallow negative voltage ⁇ VCC to the level of the deep negative voltage of ⁇ 2 ⁇ VCC.
  • Node ND 2 is at the level of ground voltage GND, and MOS transistor NQ 2 is in a conductive state so that node ND 3 and internal output node OD 1 are at the same voltage level, and MOS transistor NQ 1 is kept off.
  • node ND 2 is at the level of ground voltage GND, internal output node OD 1 lowers to of the deep negative voltage level of ⁇ 2 ⁇ VCC, and node ND 3 also lowers to the deep negative voltage level of ⁇ 2 ⁇ VCC.
  • MOS transistor NQ 1 since MOS transistor NQ 1 has the source electrically coupled to the gate through MOS transistor NQ 2 , MOS transistor NQ 1 rapidly turns non-conductive, so that an ineffective current hardly flows, and internal output node OD 1 reliably lowers to the negative voltage level of ⁇ 2 ⁇ VCC.
  • the voltage level of internal node ND 30 may possibly exceed the voltage level of internal output node OD 1 .
  • internal node ND 30 is once connected electrically to final output node FOD, and a difference in voltage level between internal node ND 30 and internal output node OD 1 is small in such a state. Therefore, MOS transistor NQ 1 maintains the non-conductive state owing to its threshold voltage.
  • control signal ⁇ CTF rises from the level of ground voltage GND to the level of power supply voltage VCC, and the voltage level of node ND 30 rises from the deep negative voltage of ⁇ 2 ⁇ VCC to the shallow negative voltage ⁇ VCC.
  • MOS transistor NQ 31 turns conductive to couple electrically output node OD 1 to final output node FOD.
  • the voltage level of final output node FOD is higher than the deep negative voltage of ⁇ 2 ⁇ VCC, negative charges are supplied from internal output node OD 1 to final output node FOD.
  • MOS transistor NQ 2 has the gate and the source (final output node FOD) set to the same potential, and maintains the non-conductive state. Thus, the charges are efficiently transferred from internal output node OD 1 to final output node FOD.
  • control signal ⁇ P rises from the level of ground voltage GND to the level of power supply voltage VCC.
  • node ND 1 returns from the level of the shallow negative voltage ⁇ VCC to the level of ground voltage GND, and output node OD 1 rises from the level of deep negative voltage of ⁇ 2 ⁇ VCC to the level of the shallow negative voltage ⁇ VCC.
  • node ND 2 is at the ground voltage level, and node ND 3 rises in voltage level from the deep negative voltage of ⁇ 2 ⁇ VCC to negative voltage ⁇ VCC, similarly to output node OD 1 .
  • Voltage drive stage 40 has a structure similar to that of an output stage (charge transfer stage) of a circuit generating the negative voltage ⁇ VCC and arranged in ⁇ VCC generating circuit at the preceding stage. Therefore, the deep negative voltage of ⁇ 2 ⁇ VCC can be efficiently generated without causing an ineffective current flow.
  • the output stage of the circuit generating shallow negative voltage ⁇ VCC is further connected to the charge pump capacitance of the output node, and the output stage (charge transfer stage) of the same structure as the output stage of the ⁇ VCC generating circuit is arranged to form the voltage drive stage.
  • the charges can be efficiently utilized to generate the negative voltage of ⁇ 2 ⁇ VCC with low power consumption.
  • FIG. 10A schematically shows a construction of a voltage generating circuit according to a fifth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 10A includes charge transfer stages XFN 1 , XFN 2 , . . . and XFNn cascaded between node ND 2 and output node FOD.
  • P-channel MOS transistors PQ 1 and PQ 2 are cross-coupled and arranged between the ground node and nodes ND 1 and ND 2 .
  • Node ND 1 receives control signal ⁇ P for precharging via capacitance element C 1
  • node ND 2 receives control signal ⁇ CP for producing charges via capacitance element C 2 .
  • MOS transistors PQ 1 and PQ 2 as well as capacitance elements C 1 and C 2 have the same structures as those shown in FIGS. 1 and 8, and nodes ND 1 and ND 2 are changed in voltage level between ground voltage GND and negative voltage ⁇ VCC in accordance with control signals ⁇ P and ⁇ CP.
  • Capacitance elements CK 1 -CKn ⁇ 1 are connected to output nodes OD 1 -ODn ⁇ 1 of charge transfer stages XFN 1 -XFNn ⁇ 1, respectively.
  • capacitance elements CQ 1 . . . CQn ⁇ 1 arranged at respective output nodes OD 1 , OD 3 , . . . and ODn ⁇ 1 receive control signal ⁇ P via control signal input nodes S 1 .
  • capacitance elements CQ 2 . . . at even-numbered stages.
  • Charge transfer stages XFN 1 -XFNn alternately receive control signals ⁇ CT and ⁇ CTF.
  • the charge transfer stage and the capacitance element arranged at a respective input node i.e., the output node of the upstream charge transfer stage) form the voltage drive stage.
  • Final output node FOD is connected to stabilizing capacitance element C 4 . If the voltage on final output node FOD is stable, stabilizing capacitance element C 4 may not be provided.
  • FIG. 10B shows a construction of charge transfer stages XFN 1 -XFNn.
  • Charge transfer stages XFN 1 -XFNn have the same structure, and
  • FIG. 10B shows charge transfer stage XFN generally representing charge transfer stages XFN 1 -XFNn.
  • Charge transfer stage XFN includes an N-channel MOS transistor NQa connected between an input node NDI and an output node NDO, an N-channel MOS transistor NQb connected between output node NDO and an internal node NDA and having a gate connected to input node NDI, and a capacitance element Ca connected between control signal input node Sa and internal node NDA.
  • Charge transfer stage XFN is equivalent in construction to voltage drive stage 40 shown in FIG. 8 other than capacitance element C 20 .
  • Control signal input node Sa receives control signal ⁇ CT or ⁇ CTF for controlling the charge transfer.
  • the precharging of input node NDI and the charge transfer are alternately performed in charge transfer stages XFN 1 -XFNn, so that a voltage drop by ⁇ VCC can be caused in each of charge transfer stages XFN 1 -XFNn, and a voltage of ⁇ n ⁇ VCC can be generated on final output node FOD.
  • FIG. 11 is a timing chart representing an operation of the voltage generating circuit shown in FIGS. 10A and 10B.
  • FIG. 11 illustrates signal waveforms on the output and input nodes of charge transfer stages XFNi ⁇ 1, XFNi and XFNi+1.
  • Capacitance elements Ca of charge transfer stages XFNi ⁇ 1, XFNi and XFNi+1 are supplied with control signals ⁇ CTF, ⁇ CT and ⁇ CTF, respectively.
  • control signal ⁇ P rises from ground voltage GND to power supply voltage VCC
  • the voltage level of input node NDIi ⁇ 1 of charge transfer stage XFNi ⁇ 1 is raised by the charge pump operation of corresponding capacitance element CKi ⁇ 2.
  • the voltage level changes from a negative voltage of ⁇ (i ⁇ 1) ⁇ VCC to a negative voltage of ⁇ (i ⁇ 2) ⁇ VCC.
  • internal node NDAi ⁇ 1 is at the voltage of ⁇ (i ⁇ 1) ⁇ VCC, and MOS transistor NQa in charge transfer stage XFNi ⁇ 1 maintains the non-conductive state.
  • charge transfer stage XFNi+1 the charge pump operation is likewise effected on input node NDIi+1 in accordance with control signal ⁇ P, and the voltage level thereof changes from ⁇ (i+1) ⁇ VCC to ⁇ i ⁇ VCC.
  • Input node NDIi+1 of charge transfer stage XFNi+1 corresponds to output node ODi of charge transfer stage XFNi.
  • MOS transistor NQb in charge transfer stage XFNi is in a conductive state, and accordingly the level of node NDIi changes from a voltage of ⁇ (i+1) ⁇ VCC to ⁇ i ⁇ VCC. Even in this state, MOS transistor NQa in charge transfer stage XFNi has the gate lower in potential than its source, and therefore maintains the non-conductive state.
  • control signal ⁇ CP falls from the level of power supply voltage VCC to the level of ground potential GND
  • capacitance element CKi in charge transfer stage XFNi performs the charge pumping operation to change the voltage on input node NDIi from ⁇ (i ⁇ 1) ⁇ VCC to ⁇ i ⁇ VCC.
  • node NDIi ⁇ 1 is at the voltage level of ⁇ (i ⁇ 2) ⁇ VCC and MOS transistor NQb is in a conductive state, so that node NDAi ⁇ 1 rises from the voltage level of ⁇ (i ⁇ 1) ⁇ VCC to the voltage level of ⁇ i ⁇ VCC.
  • control signal ⁇ CT is driven to the level of power supply voltage VCC.
  • charge transfer stage XFNi the charge pumping by capacitance element Ca raises the voltage level of input node NDAi from ⁇ (i+1) ⁇ VCC to ⁇ i ⁇ VCC, and MOS transistor NQa turns conductive. Accordingly, the charges are driven via MOS transistor NQa in charge transfer stage XFNi.
  • node NDIi+1 is at the voltage level of ⁇ i ⁇ VCC, and the voltage level of input node NDIi in charge transfer stage XFNi is made equal to the voltage level of input node NDIi+1 in charge transfer stage XFNi+1.
  • control signal ⁇ CT falls to the ground voltage level again, the voltage level of input node NDAi in charge transfer stage XFNi is lowered by power supply voltage VCC to attain the voltage level of ⁇ i ⁇ VCC, and MOS transistor NQa in charge transfer stage XFNi turns non-conductive.
  • control signal ⁇ CP rises from the level of ground voltage GND to the level of power supply voltage VCC, and the voltage level of input node NDIi of charge transfer stage XFNi rises.
  • internal node NDAi ⁇ 1 in charge transfer stage XFNi ⁇ 1 is raised in voltage level through MOS transistor NQb in accordance with the voltage level of node NDIi, and is set to the voltage level of ⁇ (i ⁇ 1) ⁇ VCC.
  • control signal ⁇ P falls from the level of power supply voltage VCC to the level of ground voltage GND.
  • the capacitance element in charge transfer stage XFNi+1 performs the charge pump operation on input node NDIi+1, and the voltage level thereof lowers from ⁇ i ⁇ VCC to ⁇ (i+1) ⁇ VCC.
  • This voltage drop is transmitted to internal node NDAi of charge transfer stage XFNi via MOS transistor NQb, and this MOS transistor NQb is reliably made non-conductive.
  • control signal ⁇ CTF attains and maintains the level of power supply voltage VCC for a predetermined period, and the voltage levels of internal nodes NDAi ⁇ 1 and NDAi+1 in charge transfer stages XFNi ⁇ 1 and XFNi+1 are raised by power supply voltage VCC so that corresponding MOS transistors NQa turns conductive to transfer the charges.
  • the voltage level of internal node NDAi is equal to the voltage level of input node NDIi+1 of charge transfer stage XFNi+1, and therefore to the voltage level of output node ODi of charge transfer stage XFNi, and thus MOS transistor NQa maintains the non-conductive state to prevent backflow of a current in charge transfer stage XFNi.
  • FIG. 12 schematically shows a construction of a circuit for generating the control signals used in the voltage generating circuit shown in FIGS. 10A and 10B.
  • the control signal generating circuit shown in FIG. 12 includes an AND circuit 45 receiving output signal ⁇ 4 of delay circuit 30 d and the output signal of inverter 32 b to produce control signal ⁇ CTF.
  • Other components of the control signal generating circuit shown in FIG. 12 are the same as those of the control signal generating circuit shown in FIG. 6. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • control signal ⁇ CTF is at the H level when output signal ⁇ 4 of delay circuit 30 d is at the H level and the output signal of inverter 32 b is at the H level.
  • control signal ⁇ CTF is at the H level when output signals ⁇ 3 and ⁇ 4 of delay circuits 30 c and 30 d are at the L- and H levels, respectively.
  • Other control signals ⁇ P, ⁇ CP and ⁇ CT are generated from the same components as those in the circuit shown in FIG. 6, and have the same timing relationship.
  • the plurality of charge transfer stages are cascaded, and the charge transferring and the precharging of the input node are alternately performed in the respective charge transfer stages, so that a deep negative voltage can be produced with low power consumption.
  • FIG. 14 shows a construction of a voltage generating circuit according to a sixth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 14 further includes a voltage drive stage 50 for transmitting charges of output node OD 11 to final output node FOD in accordance with control signals ⁇ PZ and ⁇ CTFZ.
  • Voltage drive stage 50 includes a capacitance element CC performing a charge pump operation on internal output node OD 11 in accordance with control signal ⁇ PZ, and a charge transfer stage XFP transmitting the charged electric charges in capacitance element CC to final output node FOD in accordance with control signal ⁇ CTFZ.
  • Charge transfer stage XFP includes a P-channel MOS transistor PQa connected between internal output node OD 11 and final output node FOD and having a gate connected to an internal node NDB, a P-channel MOS transistor PQb connected between internal node NDB and final output node FOD and having a gate connected to internal output node OD 11 , and a capacitance element Cb connected between a control signal input node S 52 receiving control signal ⁇ CTFZ and internal node NDB.
  • Charge transfer stage XFP has an input node PDI connected to internal output node OD 11 , and an output node POD connected to final output node FOD.
  • These charge generating portion and the charge transferring portion have the same constructions as those in the circuit shown in FIG. 1. Corresponding components are allotted with the same reference numbers, and description thereof will not be repeated.
  • FIG. 15 is a signal waveform diagram showing an operation in the stable state of the voltage generating circuit shown in FIG. 14. Referring to FIG. 15, an operation in the stable state of the voltage generating circuit shown in FIG. 14 will now be described.
  • the voltage generating circuit shown in FIG. 14 is the same as the voltage generating circuit shown in FIG. 8, provided that the conductivities of the transistors, polarities of the control signals and polarities of the voltages are exchanged.
  • the charge pump operation for the charges of node ND 12 is the same as that of the circuit shown in FIG. 3, and capacitance element C 12 changes the voltage level of node ND 12 between power supply voltage VCC and the high voltage of 2 ⁇ VCC in accordance with control signal ⁇ CPZ.
  • Capacitance element CC changes the voltage level of internal output node OD 11 through the charge pumping operation in accordance with control signal ⁇ PZ.
  • internal output node OD 11 changes between the voltages of 2 ⁇ VCC and 3 ⁇ VCC. Since the voltage level of internal output node OD 11 changes up to 3 ⁇ VCC, the voltage level of internal node ND 13 changes between power supply voltage VCC and the high voltages of 2 ⁇ VCC and 3 ⁇ VCC over three stages.
  • control signal ⁇ PZ falls from power supply voltage VCC to ground voltage GND.
  • output node OD 11 is set to the voltage level of 2 ⁇ VCC by the charge pumping operation of capacitance element CC.
  • node ND 12 is at the level of power supply voltage VCC, and MOS transistor PQ 12 is in a conductive state, so that node ND 13 attains the voltage level of 2 ⁇ VCC similarly to internal output node OD 11 .
  • MOS transistor PQ 11 has gate and the source at the same potential, and turns non-conductive.
  • control signal ⁇ CPZ rises to the level of power supply voltage VCC. Responsively, the voltage level of node ND 12 attains the level of high voltage of 2 ⁇ VCC, so that MOS transistor PQ 12 is turned off. In this state, MOS transistor PQ 11 has the gate, drain and source set at the same voltage level, and maintains off.
  • control signal ⁇ CTFZ is at the level of power supply voltage VCC
  • node NDB is at the level of 3 ⁇ VCC
  • MOS transistor PQa is in an off state. Since internal output node OD 11 is at the voltage level of 2 ⁇ VCC, MOS transistor PQb maintains the conductive state, but a current does not flow through MOS transistor PQb because node NDB and final output node FOD are at the same voltage level.
  • control signal ⁇ CTZ falls from the level of power supply voltage VCC to the level of ground voltage GND. Responsively, the voltage level of node ND 13 lowers from the voltage of 2 ⁇ VCC to power supply voltage VCC so that MOS transistor PQ 11 turns conductive, to transfer the charges between internal output node OD 1 and internal node ND 12 . This charge transfer operation completes when internal node ND 12 and output node OD 11 attain the same potential level.
  • MOS transistor PQ 12 maintains the non-conductive state because its gate and source are set to the same voltage level.
  • node NDB is at the voltage level of 3 ⁇ VCC
  • internal output node OD 11 is at the voltage level of 2 ⁇ VCC
  • P-channel MOS transistor PQa for the charge transfer maintains the non-conductive state.
  • control signal ⁇ CPZ rises from the level of ground voltage to the level of power supply voltage VCC, and responsively the voltage level of node ND 13 rises from power supply voltage VCC to the high voltage of 2 ⁇ VCC, so that MOS transistor PQ 11 turns non-conductive.
  • MOS transistor PQ 12 maintains the non-conductive state owing to its threshold voltage because node ND 12 is at the voltage level of 2 ⁇ VCC
  • control signal ⁇ CPZ falls from power supply voltage VCC to ground voltage GND. Responsively, the charge pumping by capacitance element C 12 lowers the voltage level of node ND 12 from the high voltage of 2 ⁇ VCC to power supply voltage VCC.
  • node ND 13 and OD 11 When the voltage level of node ND 12 lowers to the level of power supply voltage VCC to turn on P-channel MOS transistor PQ 12 , for electrically connecting nodes ND 13 and OD 11 together, node ND 13 and internal output node OD 11 are at the equal voltage level of 2 ⁇ VCC, and a current does not flow in the stable state. MOS transistor PQ 11 maintains the non-conductive state because its gate and source are at the same potential level.
  • control signal ⁇ PZ rises from the level of ground voltage GND to the level of power supply voltage VCC, and responsively, node ND 11 is raised to the level of power supply voltage VCC so that node ND 12 is reliably precharged to the level of power supply voltage VCC.
  • capacitance element CC When control signal ⁇ PZ rises, capacitance element CC performs the charge pump operation to raise output node OD 1 from the level of 2 ⁇ VCC to the level of 3 ⁇ VCC.
  • node ND 12 When the voltage level of output node OD 11 rises to the voltage level of 3 ⁇ VCC, node ND 12 is at the level of power supply voltage VCC, and MOS transistor PQ 12 is rendered conductive, so that node ND 13 rises to the voltage level of 3 ⁇ VCC, and MOS transistor PQ 11 maintains the non-conductive state.
  • control signal ⁇ CTFZ falls from the level of power supply voltage VCC to the level of ground voltage GND.
  • the charge pumping by capacitance element Cb lowers the voltage level of node NDB from the voltage of 3-VCC to the voltage of 2 ⁇ VCC, and MOS transistor PQa is turned on to transfer the charges from output node OD 11 to final output node FOD so that final output node FOD is reliably kept at the voltage level of 3 ⁇ VCC.
  • node NDB is at the voltage level of 2 ⁇ VCC, and output node OD 11 and final output node FOD are at the same voltage level higher than that of node NDB.
  • MOS transistor PQb maintains the non-conductive state.
  • control signal ⁇ CTFZ rises from the level of ground voltage GND to the level of power supply voltage VCC again.
  • the charge pumping by capacitance element Cb raises the voltage level of node NDB to the voltage of 3 ⁇ VCC, and MOS transistor PQa turns non-conductive.
  • control signal ⁇ PZ falls from the level of power supply voltage VCC to the level of ground voltage GND so that the voltage level of output node OD 11 lowers to 2 ⁇ VCC.
  • MOS transistor PQ 12 is in an on-state, so that the voltage level of node ND 13 lowers from 3 ⁇ VCC to 2 ⁇ VCC. Subsequently, the above operations are repeated.
  • one voltage drive stage 50 is arranged for precharging the output node to transfer the charges in the operation of precharging the internal node, the voltage on this output node can be raised by voltage VCC, and the voltage of 3 ⁇ VCC can be produced on final output node FOD.
  • Stabilizing capacitance C 4 provided at final output node FOD may be removed if the load variation of final output node FOD is small.
  • Control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ can be produced by inverting the output signals of the control signal generating circuits shown in FIG. 12.
  • control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ are not required to change between ground voltage GND and power supply voltage VCC, and may be replaced with signals changing between any intended voltages, provided that the on/off conditions of the MOS transistors of the components are met.
  • the capacitance element for the charge pump is arranged at the output node of the circuit generating the voltage of 2 ⁇ VCC, and one stage of charge transfer stage is further arranged in which the on/off of charge transferring transistor PQa is controlled by the capacitance element and the MOS transistor detecting the potential of the output node. Accordingly, flow of ineffective charges is prevented, and the charges can be efficiently used to generate the high voltage of 3 ⁇ VCC.
  • FIG. 16 schematically shows a construction of a voltage generating circuit according to a seventh embodiment of the invention.
  • charge transfer stages XFP 1 -XFPn are cascaded between internal node ND 12 and final output node FOD.
  • Each of charge transfer stages XFP 1 -XFPn is the same in configuration as charge transfer stage XFP shown in FIG. 14.
  • Capacitance elements CC 1 to CCn ⁇ 1 are arranged corresponding to input nodes ODP 1 -ODPn ⁇ 1 of charge transfer stages XFP 2 -XFPn, respectively. Capacitance elements CC 1 to CCn ⁇ 1 are alternately supplied with control signals ⁇ PZ and ⁇ CPZ through control signal input nodes S 11 and S 12 . Charge transfer stages XFP 1 -XFPn are alternately supplied with control signals ⁇ CTZ and ⁇ CTFZ through control signal input nodes S 13 and S 52 . Thus, charge transfer stages IFX 1 , XFP 3 , . . .
  • control signal ⁇ CTZ control signal input nodes S 13 to transfer the charges
  • charge transfer stages XFP 2 , . . . and XFPn in even-numbered stages are supplied with control signal ⁇ CTFZ through control signal input nodes S 52 and has the charge transfer controlled.
  • Each of charge transfer stages XFP 1 -XFPn raises the received voltage by power supply voltage VCC. Therefore, a voltage of (n+1) ⁇ VCC is produced on final output node FOD.
  • cross-coupled N-channel MOS transistors NQ 11 and NQ 12 are arranged, and capacitance elements C 11 and C 12 performing the charge pump operation on nodes ND 11 and ND 12 in accordance with control signal ⁇ PZ and ⁇ CPZ are arranged.
  • the circuit portion performing the charge pump operation on node ND 12 is the same in configuration as that shown in FIGS. 3 and 14, and therefore the voltage on node ND 12 changes between voltage VCC and the high voltage of 2 ⁇ VCC.
  • FIG. 17 is a timing chart illustrating an operation of the voltage generating circuit shown in FIG. 16 in the stable state. Referring to FIGS. 17 and 14, description will now be given on the operation of the voltage generating circuit shown in FIG. 16 in the stable state.
  • FIG. 17 illustrates waveforms of voltages on the input and internal nodes of charge transfer stages XFPi ⁇ 1, XFPi and XFPi+1.
  • Charge transfer stages XFPi ⁇ 1 and XFPi+1 are supplied with control signal ⁇ CTF, and charge transfer stage XFPi is supplied with control signal ⁇ CT.
  • Input node NDIj of charge transfer stage XFPj is connected to internal output node ODPj ⁇ 1 of charge transfer stage XFPj ⁇ 1 at the preceding stage.
  • FIG. 17 illustrates internal output nodes ODIi ⁇ 1 and ODIi corresponding to input nodes NDIi and NDIi+1, respectively. The potentials of the input nodes of the respective charge transfer stages will now be described due to the reference to FIG. 14.
  • control signal ⁇ PZ falls to the level of ground voltage GND
  • input node NDIi ⁇ 1 of charge transfer stage XFPi ⁇ 1 lowers from a voltage level of i ⁇ VCC to a voltage level of (i ⁇ 1) ⁇ VCC.
  • charge transfer stage XFPi+1 the voltage of its input node NDIi+1 lowers from the voltage level of (i+1) ⁇ VCC to the voltage level of (i+1) ⁇ VCC.
  • MOS transistor PQb is in an conductive state
  • internal nodes NDBi ⁇ 1 and NDBi+1 are set to the voltage levels corresponding to the voltage levels of the subsequent charge transfer stages XFPi and XFPi+2, respectively.
  • control signal ⁇ CPZ rises from the level of ground voltage GND to the level of power supply voltage VCC
  • charge transfer stage XFPi the charge pumping by corresponding capacitance element CCi raises the voltage level of input node NDIi from the voltage of i ⁇ VCC to the voltage of (i+1) ⁇ VCC.
  • MOS transistor PQb in charge transfer stage XFPi ⁇ 1 is in a conductive state, such boosted voltage of node NDIi raises the voltage level of node NDBi ⁇ 1 to (i+1) ⁇ VCC, and corresponding MOS transistor PQa is kept off.
  • control signal ⁇ CTZ falls from power supply voltage VCC to ground voltage GND
  • charge transfer stage XFPi internal node NDBi attains the voltage level of i ⁇ VCC
  • MOS transistor PQa turns conductive to transmit the voltage of (i+1) ⁇ VCC on internal node NDIi to input node NDIi+1 at the subsequent or downstream charge transfer stage XFPi+1.
  • backflow of charges is prevented in charge transfer stages XFPi ⁇ 1 and XFPi+1 because MOS transistors PQa are in an off (non-conductive state).
  • control signal ⁇ CPZ rises to the level of power supply voltage VCC
  • the voltage level of internal node NDBi in charge transfer stage XFPi rises from the voltage of i ⁇ VCC to the voltage of (i+1) ⁇ VCC
  • the gate potential of corresponding P-channel MOS transistor PQa becomes equal to or higher than its source potential so that MOS transistor PQa is turned off.
  • control signal ⁇ PZ rises from ground voltage GND to power supply voltage VCC
  • capacitance elements CCi ⁇ 1 and CCi+1 in charge transfer stages XFPi ⁇ 1 and XFPi+1 perform the charge pump operations to raise the voltage levels of the corresponding input nodes by power supply voltage VCC, respectively.
  • input node NDIi ⁇ 1 of charge transfer stage XFPi ⁇ 1 attains the voltage level of i ⁇ VCC
  • input node NDIi+1 of charge transfer stage XFPi+1 attains the voltage level of (i+2) ⁇ VCC.
  • MOS transistor PQb turns conductive because the gate potential thereof is lower than the source potential thereof, and internal node NDBi rises to the level of the voltage of (i+2) ⁇ VCC equal to that of input node NDIi+1 of charge transfer stage XFPi+1, and MOS transistor PQa is kept off to prevent backflow of charges.
  • control signal ⁇ CTZF falls from power supply voltage VCC to ground voltage GND, and in charge transfer stages XFPi ⁇ 1 and XFPi+1, the voltage levels of internal nodes NDBi ⁇ 1 and NDBi+1 are lowered by power supply voltage VCC, and corresponding MOS transistors PQa are rendered conductive. Consequently, the charges are transferred from input node NDIi ⁇ 1 to output node ODPi ⁇ 1 (NDIi), and also the charges are supplied from input node NDIi+1 to the output node in charge transfer stage XFPi+1.
  • charge transfer stages XFP 1 -XFPn alternately perform the charge pump operation to boost the received voltages by the power supply voltage VCC, and can finally produce the voltage of (n+1) ⁇ VCC on final output node FOD.
  • the threshold voltage of an MOS transistor is utilized to control the setting of the non-conductive state of the MOS transistor to prevent the occurrence of an ineffective current and each node is raised in voltage level gradually to attain the final stable voltage level.
  • control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ each may be different in the high level voltage and the low level voltage from the others.
  • the capacitance elements are used to perform the charge pump operation on the input nodes of the respective charge transfer stages, and the charge transfer operations are performed in an alternate manner. Accordingly, the internal voltage at an intended level can be produced with reduced current consumption.
  • Control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ can be produced by inverting all the output signals of the control signal generating circuitry shown in FIG. 12.
  • FIG. 18 shows a construction of a voltage generating circuit according to an eighth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 18 differs in configuration from the voltage generating circuit shown in FIG. 1 in the following points.
  • Cross-coupled P-channel MOS transistors PQ 1 and PQ 2 in FIG. 1 are replaced with N-channel MOS transistors NQQ 1 and NQQ 2 forming a charge transfer stage.
  • N-channel MOS transistor NQQ 1 is connected between a precharge voltage supply node NDD 2 and internal node ND 2 , and has a gate (control electrode) connected to an internal node (first internal node) NDD 1 .
  • Precharge voltage supply node NDD 2 is connected to ground node GG supplying ground voltage GND of the reference voltage.
  • N-channel MOS transistor NQQ 2 is connected between internal nodes NDD 1 and NDD 2 , and has a gate coupled to control signal input node S 1 receiving control signal ⁇ P.
  • Internal node NDD 1 is coupled via capacitance element CQ 1 to input node S 32 receiving control signal ⁇ CTF.
  • Control signals ⁇ CTF, ⁇ P, ⁇ CP and ⁇ CT each change between ground voltage GND and power supply voltage VCC, and are produced from the control circuit shown in FIG. 12.
  • MOS transistors NQQ 1 and NQQ 2 correspond to the claimed first and second transistors, respectively, and capacitance element CQ 1 correspond to the claimed first capacitance element.
  • Control signal ⁇ CTF corresponds to the first control signal
  • control signal ⁇ P corresponds to the second control signal in the claim recitation.
  • MOS transistors NQ 1 and NQ 2 correspond to the claimed third and fourth transistors, respectively, and capacitance elements C 2 and C 3 correspond to the claimed second and third capacitance elements, respectively.
  • Control signals ⁇ CP and ⁇ CT correspond to the claimed third and fourth control signals, respectively. All the MOS transistors are each of the enhancement type.
  • FIG. 19 is a signal waveform diagram illustrating an operation of the voltage generating circuit shown in FIG. 18. Referring to FIG. 19, description will now be given on the operation of the voltage generating circuit shown in FIG. 18. FIG. 19 illustrates signal waveforms in the case when negative voltage ⁇ VCC is produced on output node OD 1 .
  • control signals ⁇ P, ⁇ CT and ⁇ CTF are at the L level, and control signal ⁇ CP is at the H level.
  • internal node ND 2 is at the level of ground voltage GND through the charge pump operation of capacitance element C 2 receiving control signal ⁇ CP.
  • Internal node ND 3 attains the level of negative voltage ⁇ VCC through the charge pump operation of capacitance element C 3 .
  • MOS transistor NQ 2 is turned on (output node OD 1 is at the level of negative voltage ⁇ VCC), and internal node ND 3 is set to the same voltage level as that of output node OD 1 .
  • Internal node NDD 1 is at the level of ground voltage GND through the charge pump operation of capacitance element CQ 1 .
  • Control signal ⁇ P is at the L level of the ground voltage, and MOS transistor NQQ 2 is in a non-conductive state.
  • control signal ⁇ P rises to the H level of power supply voltage VCC.
  • MOS transistor NQQ 2 is turned on, so that internal nodes NDD 1 and ND 2 are electrically coupled together, to attain the same voltage level (set to the ground voltage level).
  • control signal ⁇ P falls to the L level of ground voltage GND.
  • the charge pumping by capacitance element C 2 lowers the voltage level of node ND 2 .
  • MOS transistor NQQ 2 is in a conductive state, the charge pumping by capacitance element C 2 lowers the voltage levels of nodes NDD 1 and ND 2 from the ground voltage to negative voltage ⁇ VCC.
  • capacitance element C 2 By making capacitance element C 2 to have a capacitance value much larger than that of capacitance element CQ 1 , both internal nodes NDD 1 and ND 2 can be lowered from the level of ground voltage GND to the level of negative voltage ⁇ VCC.
  • MOS transistor NQ 2 in the output charge transfer stage turns off, so that internal node ND 3 is isolated from output node OD 1 , and enters into an electrically floating state.
  • control signal ⁇ CT is raised from the level of ground voltage GND to the level of power supply voltage VCC at time t 3 .
  • the charge pumping by capacitance element C 3 raises the voltage level of node ND 3 from negative voltage ⁇ VCC to the level of ground voltage GND, and MOS transistor NQ 1 is turned on to couple electrically internal node ND 2 to output node OD 1 .
  • output node OD 1 is at a higher voltage level than internal node ND 2 , positive charges move from output node OD 1 to internal node ND 2 so that the voltage level of output node OD 1 lowers.
  • Internal node ND 3 is at the level of ground voltage GND.
  • the gate-source voltage of MOS transistor NQ 1 is equal to power supply voltage VCC, and the charges can be transferred between internal node ND 2 and output node OD 1 without an influence by the threshold voltage of MOS transistor NQ 1 .
  • MOS transistor NQ 1 When MOS transistor NQ 1 is turned on to move the charges between internal node ND 2 and output node OD 1 , the gate and source of MOS transistor NQ 2 attain the same potential level. In this state, MOS transistor NQ 2 is of the enhancement type, and maintains the non-conductive state due to its threshold voltage.
  • control signal ⁇ CT falls from the H level to the L level. Responsively, the charge pumping by capacitance element C 3 lowers the voltage level of internal node ND 3 to negative voltage ⁇ VCC again, and MOS transistor NQ 1 turns non-conductive.
  • MOS transistor NQQ 2 When the charges move between internal node ND 2 and output node OD 1 , MOS transistor NQQ 2 is in a conductive state to couple electrically internal nodes NDD 1 and ND 2 , and can supply negative charges from internal node ND 2 to internal node NDD 1 so that the charges can be efficiently transferred. In the above operation, MOS transistor NQQ 1 maintains the non-conductive state because internal nodes NDD 1 and ND 2 are at substantially equal potentials, and the gate-source voltage thereof is lower than the threshold voltage.
  • control signal ⁇ CP is raised from the L level of ground voltage GND to the H level of power supply voltage VCC.
  • the charge pumping by capacitance element C 2 raises the potential of internal node ND 2 from the level of negative voltage ⁇ VCC.
  • control signal ⁇ P is at the level of power supply voltage VCC, and MOS transistor NQQ 2 is in a conductive state, so that the voltage levels of both internal nodes NDD 1 and ND 2 rise to ground voltage GND.
  • control signal ⁇ P falls to the L level, and MOS transistor NQQ 2 is turned off, and internal nodes ND 2 and NDD 1 are electrically isolated from each other.
  • control signal ⁇ CTF rises to the H level.
  • the charge pump operation of capacitance element CQ 1 raises the voltage level of internal node NDD 1 from ground voltage GND to power supply voltage VCC (MOS transistor NQQ 2 is off).
  • MOS transistor NQQ 1 is turned on to precharge internal node ND 2 to the level of ground voltage GND.
  • control signal ⁇ CTF falls to the L level. Responsively, the charge pumping by capacitance element CC 1 lowers the potential of internal node NDD 1 to the level of ground voltage GND again, and MOS transistor NQQ 1 is turned off (node ND 2 is at the ground voltage level).
  • node NDD 1 attains the level of power supply voltage VCC in accordance with the H level of control signal ⁇ CTF in the period between times t7 and t8, to turn MOS transistor NQ 1 conductive, so that internal node ND 2 is coupled to the ground node to be set to the ground voltage level.
  • control signal ⁇ CP is lowered from the H level to the L level.
  • internal node ND 2 attains the level of negative voltage ⁇ VCC, and positive charges flow from output node OD 1 into internal node ND 2 (negative charges flow from internal node ND 2 into output node OD 1 ) when MOS transistor NQ 1 is conductive, and the voltage level of output node OD 1 gradually lowers.
  • MOS transistors NQ 1 , NQ 2 , NQQ 1 and NQQ 2 are individually controlled by control signals ⁇ CT, ⁇ CP, ⁇ CTF and ⁇ P, respectively. Therefore, by appropriately setting the timing of these control signals, the charges can be transferred after cutting off a path of flow of ineffective charges, and the flow of ineffective charges can be prevented so that the negative charges can be efficiently transferred to output node OD 1 to produce negative voltage ⁇ VCC.
  • the construction shown in FIG. 18 can set the voltage level produced from output node OD 1 at any intended level by appropriately setting the amplitudes of control signals ⁇ CT, ⁇ CP, ⁇ P and ⁇ CTF, and the level of voltage applied to a ground node OGG serving as the precharge voltage supply node coupled to MOS transistor NQQ 1 .
  • the charge transfer stages are cascaded, these charge transfer stages alternately perform the charge transfer, and the precharging and the charge accumulation are alternately performed on the internal nodes connected to these charge transfer stages.
  • the charges can be efficiently utilized to produce the negative voltage at an intended voltage level.
  • the circuits are formed of the MOS transistors of the same conductivity type, and therefore a region for isolating the PMOS and NMOS transistors from each other is not required.
  • the number of manufacturing steps can be reduced, and therefore, the manufacturing cost can be reduced.
  • FIG. 20 shows a construction of a voltage generating circuit according to a ninth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 20 differs in construction from the voltage generating circuit shown in FIG. 3 in the following points.
  • Cross-coupled N-channel MOS transistors NQ 11 and NQ 12 shown in FIG. 3 are replaced with P-channel MOS transistors PQQ 1 and PQQ 2 .
  • P-channel MOS transistor PQQ 1 is connected between a precharge voltage supply node NDD 12 and internal node ND 12 , and has a gate connected to an internal node NDD 13 .
  • Precharge voltage supply node NDD 12 is connected to power supply node PW supplying power supply voltage VCC, and supplies charges for precharging internal node ND 12 to the level of power supply voltage VCC.
  • Internal node NDD 13 is coupled via a capacitance element CQ 13 to input node S 52 receiving control signal ⁇ CTFZ.
  • the high voltage 2 ⁇ VCC (equal to 2 ⁇ VCC) is produced on output node OD 11 .
  • P-channel MOS transistor PQQ 2 is connected between internal nodes ND 12 and NDD 13 , and has a gate connected to input node S 11 receiving control signal ⁇ PZ.
  • a charge transfer stage transferring charges between internal node ND 12 and output node OD 11 has the same construction as that shown in FIG. 3. Corresponding elements are allotted with the same reference numerals, and description thereof will not be repeated.
  • Internal node ND 12 is coupled to input node S 12 receiving control signal ⁇ CPZ via capacitance element C 12 .
  • control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ are produced by inverting control signals ⁇ P, ⁇ CP, ⁇ CT and ⁇ CTF generated from the control signal generating circuits.
  • MOS transistors PQQ 1 and PQQ 2 correspond to the first and second transistors
  • MOS transistors PQ 11 and PQ 12 correspond to the third and fourth transistors, respectively.
  • Control signals ⁇ CTFZ, ⁇ PZ, ⁇ CPZ and ⁇ CTZ correspond to the first, second, third and fourth control signals, respectively.
  • Capacitance elements CQ 13 , C 12 and C 13 correspond to the first, second and third capacitance elements, respectively.
  • FIG. 21 is a signal waveform diagram illustrating an operation of the voltage generating circuit shown in FIG. 20.
  • the voltage generating circuit shown in FIG. 20 generates a voltage of 2 ⁇ VCC on output node OD 11 on the basis of the voltage VCC applied to power supply node PW. Accordingly, the operation waveforms of the voltage generating circuit shown in FIG. 20 can be obtained by inverting voltage polarities of the signals and nodes of the voltage generating circuit shown in FIG. 18, and measuring the voltages on the respective nodes with reference to power supply voltage VCC. Therefore, the operation of the voltage generating circuit shown in FIG. 20 will now be described briefly with reference to FIG. 21.
  • control signals ⁇ PZ, ⁇ CTZ and ⁇ CTFZ are at the H level of power supply voltage VCC, and control signal ⁇ CPZ is at the L level of ground voltage GND.
  • node ND 12 is at the level of power supply voltage VCC
  • node ND 13 is at the level of power supply voltage VCC.
  • MOS transistor PQQ 2 is in a non-conductive state
  • MOS transistor PQQ 1 is also in a non-conductive state.
  • node ND 13 is at the level of high voltage 2 ⁇ VCC, similarly to the second embodiment, and MOS transistor PQ 11 is in an off state (non-conductive state).
  • MOS transistor PQ 12 is an on state (conductive state), and internal node ND 13 is electrically coupled to output node OD 11 .
  • control signal ⁇ PZ falls from the H level of power supply voltage VCC to the L level of ground voltage GND, and MOS transistor PQQ 2 turns conductive to couple electrically internal node NDD 13 to internal node ND 12 .
  • MOS transistor PQQ 1 maintains the non-conductive state because the gate, source and drain potentials thereof are equal to each other.
  • control signal ⁇ CPZ rises from the L level to the H level.
  • the charge pumping by capacitance element C 12 raises the voltage level of node ND 12 from power supply voltage VCC to high voltage 2 ⁇ VCC by an amplitude VCC of control signal ⁇ CPZ.
  • MOS transistor PQQ 2 is conductive so that the voltage level of node NDD 13 rises to high voltage 2 ⁇ VCC.
  • capacitance element C 12 much larger in capacitance value than capacitance element CQ 13 , node NDD 13 can be charged to the level of high voltage 2 ⁇ VCC, similarly to the charging operation of node NDD 12 .
  • MOS transistor PQQ 1 turns non-conductive.
  • MOS transistor PQ 12 turns non-conductive (output node OD 11 is at the potential level of voltage 2 ⁇ VCC), and internal node ND 13 is isolated from output node OD 11 .
  • control signal ⁇ CTZ falls from the H level to the L level, and the charge pumping by capacitance element C 13 lowers the potential level of internal node ND 13 from the high voltage 2 ⁇ VCC to power supply voltage VCC.
  • MOS transistor PQ 11 turns conductive to transfer the charges between internal node ND 12 and output node OD 11 . Since the absolute value of threshold voltage of MOS transistor PQ 11 is much smaller than power supply voltage VCC, the charges can be transferred between internal node ND 12 and output node OD 11 without an influence of the threshold voltage of MOS transistor PQ 1 .
  • the voltage level of output node OD 11 is lower than the voltage of 2 ⁇ VCC, positive charges are supplied from internal node ND 12 to output node OD 11 , and the voltage level of output node OD 11 rises.
  • control signal ⁇ CTZ rises from the L level to the H level, and the charge pumping by capacitance element C 13 raises the potential level of internal node ND 13 to the high voltage 2 ⁇ VCC again. Accordingly, MOS transistor PQ 11 turns non-conductive, and the charge transfer operation completes. In this state, the potential level of internal node ND 12 is lower than the potential level of internal node ND 13 , and the positive charges move from internal node ND 13 to output node OD 11 via MOS transistor PQ 12 even when MOS transistor PQ 12 is in a conductive state. Responsively, the voltage level of output node OD 11 rises so that the flow-out charges are effectively utilized, and no ineffective current flows. This is the same as in the second embodiment.
  • control signal ⁇ CPZ falls from the H level to the L level, and responsively the charge pumping by capacitance element C 12 lowers the voltage level of internal node ND 12 from high voltage 2 ⁇ VCC to power supply voltage VCC.
  • MOS transistor PQ 12 is turned on to make node ND 13 and output node OD 11 equal in potential to each other, and accordingly MOS transistor PQ 11 is turned off, and internal node ND 13 is isolated from output node OD 11 (in the case where the voltage level of output node OD 11 is higher than power supply voltage VCC).
  • MOS transistor PQQ 2 Since MOS transistor PQQ 2 is conductive, the voltage level of internal node NDD 13 lowers from the positive high voltage 2 ⁇ VCC to power supply voltage VCC in accordance with the potential change on internal node ND 12 . In this state, MOS transistor PQQ 1 of the enhancement type has the gate and source set at equal potential, and maintains the non-conductive state so that no charges flow from internal node ND 12 to power supply node PW.
  • control signal ⁇ PZ rises from the L level to the H level.
  • MOS transistor PQQ 2 has the gate and source set to the potential equal to each other, and turns non-conductive to isolate electrically internal node NDD 13 from internal node ND 12 .
  • control signal ⁇ CTFZ lowers from the H level to the L level.
  • the charge pumping by capacitance element CQ 13 lowers the voltage level of internal node NDD 13 from power supply voltage VCC to ground voltage GND, and MOS transistor PQQ 1 turns conductive to couple internal node ND 12 to power supply node PW, and internal node ND 12 is precharged to the level of power supply voltage VCC.
  • control signal ⁇ CTFZ rises from the L level to the H level again, and the charge pump operation of capacitance element CQ 13 changes the voltage level of internal node NDD 13 to power supply voltage VCC again. Responsively, MOS transistor PQQ 1 is turned off, and the precharging operation of internal node ND 12 completes.
  • control signal ⁇ CTFZ lowers to the L level of ground voltage GND in a period between times t7 and t8, and responsively MOS transistor PQQ 1 is turned on to precharge internal node ND 12 to the level of power supply voltage VCC.
  • MOS transistor PQ 12 is reliably maintained non-conductive.
  • MOS transistor PQQ 1 turns non-conductive, and the flow of current from internal node ND 12 to power supply node PW is suppressed.
  • MOS transistor PQ 12 has the gate potential higher than its source and drain potentials, and is reliably turned off.
  • control signal ⁇ CTZ When control signal ⁇ CTZ is at the L level, internal node ND 13 lowers to or below the level of power supply voltage VCC in a transition period, and MOS transistor PQ 11 has the gate potential lower than its source potential, and is turned on. Therefore, the positive charges can be supplied from internal node ND 12 to output node OD 1 , and the voltage level of output node OD 11 rises.
  • the voltage level of node ND 13 changes between power supply voltage VCC and high voltage 2 ⁇ VCC.
  • MOS transistor PQ 12 maintains the non-conductive state.
  • the voltage level of internal node ND 13 changes between power supply voltage VCC and ground voltage GND, and MOS transistor PQ 11 is turned on when internal node ND 13 is set to the ground voltage level in accordance with control signal ⁇ CPZ. Consequently, the positive charges are supplied to output node OD 11 to raise its voltage level.
  • the voltage generating circuit shown in FIG. 20 can efficiently transfer the charges without causing any ineffective current, and thereby can produce high voltage 2 ⁇ VCC on output node OD 11 .
  • control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ have the amplitudes of power supply voltage VCC, and a high voltage 2 ⁇ VCC higher by this amplitude than the reference voltage being power supply voltage VCC.
  • the voltage applied to the power supply node may be at the level different from power supply voltage VCC, and control signals ⁇ PZ, ⁇ CPZ, ⁇ CTZ and ⁇ CTFZ may have the amplitudes different from power supply voltage VCC.
  • the voltage supplied to the reference precharge voltage supply node can be used as a reference voltage, and a high voltage higher by the amplitude of control signal ⁇ CPZ can be produced on output node OD 11 on the basis of such reference voltage.
  • the PMOS transistor is utilized to accumulate and transfer the charges by controlling the gate voltage, and the positive high voltage, at an intended level can be produced without causing an ineffective current.
  • FIG. 22 shows a structure of a voltage generating circuit according to a tenth embodiment of the invention.
  • precharge voltage supply node NDD 2 is coupled to input node S 1 receiving control signal ⁇ P.
  • Other construction of the voltage generating circuit shown in FIG. 22 is the same as that of the voltage generating circuit shown in FIG. 18. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • MOS transistor NQQ 1 is provided for reliably precharging internal node ND 2 to the level of ground voltage GND in accordance with control signal ⁇ CTF.
  • control signal ⁇ CTF attains the H level of power supply voltage VCC
  • control signal ⁇ P is at the L level of ground voltage GND (FIG. 19). Therefore, when MOS transistor NQQ 1 is conductive, internal node ND 2 can be precharged to the ground voltage level in accordance with control signal ⁇ P.
  • control signal ⁇ P is at the H level of power supply voltage VCC
  • control signal ⁇ CTF is at the L level of ground voltage GND.
  • MOS transistor NQQ 2 is in a conductive state to electrically couple internal nodes NDD 1 and ND 2 . Accordingly, MOS transistor NQQ 1 have the gate and source made equal in potential to each other, and maintains the non-conductive state. Therefore, such a situation can be reliably prevented that a current flows from control signal input node S 1 to internal node ND 2 when the potential level of internal node ND 2 lowers.
  • Operation waveforms of the voltage generating circuit shown in FIG. 22 are the same as those in FIG. 19 for the voltage generating circuit shown in FIG. 18. It is not necessary to use ground voltage GND for generating negative voltage ⁇ VCC, and the circuit configuration and layout can be made simple. Stabilizing capacitance 4 merely has the other electrode coupled to ground node GG, and therefore can be arranged in any position. Accordingly, the voltage generating circuit is not subject to restriction by the interconnection layout of the power supply line and ground line, and the restrictions on the circuit arrangement positions are mitigated, which improves the freedom degree in arrangement position of the voltage generating circuit in the semiconductor device incorporating the voltage generating circuit.
  • FIG. 23 shows a structure of a voltage generating circuit according to an eleventh embodiment of the invention.
  • the voltage generating circuit shown in FIG. 23 differs in configuration from the voltage generating circuit shown in FIG. 20 in the following points. Specifically, precharge voltage supply node NDD 12 coupled to P-channel MOS transistor PQQ 1 is coupled to control signal input node S 11 receiving control signal ⁇ PZ.
  • Other configuration of the voltage generating circuit shown in FIG. 23 is the same as in the voltage generating circuit shown in FIG. 20. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • MOS transistor PQQ 1 is provided for precharging internal node ND 12 to the level of power supply voltage VCC.
  • Control signal ⁇ PZ is at the H level of power supply voltage VCC when control signal ⁇ CTZF turning on MOS transistor PQQ 1 is at the L level.
  • control signal ⁇ PZ can precharge internal node ND 12 to the level of power supply voltage VCC. Accordingly, the operation waveforms of the voltage generating circuit shown in FIG. 23 are provided by the operation waveforms corresponding to those illustrated in FIG. 21, and the same operations as the voltage generating circuit shown in FIG. 20 can be implemented.
  • control signal ⁇ PZ is at the L level
  • control signal ⁇ CTFZ is at the H level
  • MOS transistor PQQ 2 electrically couples internal nodes NDD 13 and ND 12 . Therefore, MOS transistor PQQ 1 has the equal potential at its gate and source (internal node 12 ), and therefore maintains the non-conductive state so that the flow of a current from internal node ND 12 to input node S 11 can be reliably suppressed.
  • the voltage generating circuit shown in FIG. 23 does not utilize power supply voltage VCC for producing high voltage 2 ⁇ VCC. Therefore, the circuit configuration can be made simple, and the interconnection layout can also be made simple. Since the voltage generating circuit does not utilize the power supply voltage VCC, the voltage generating circuit can be arranged without a restriction by the interconnection layout of power supply voltage VCC (if it is arranged as an internal circuit of a semiconductor integrated circuit). This voltage generating circuit may be arranged in a structure such as a system LSI as a macro of one circuit block.
  • control signals are utilized for precharging the internal node, and a power supply voltage is not required so that the circuit configuration can be made simple.
  • FIG. 24 shows a construction of a voltage generating circuit according to a twelfth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 24 differs in configuration from the voltage generating circuit shown in FIG. 10A in the following points.
  • the negative charge producing stage is not formed of cross-coupled P-channel MOS transistors PQ 1 and PQ 2 in FIG. 10A, but is formed of MOS transistors NQQ 1 and NQQ 2 as well as capacitance elements CQ 1 and CQ 2 shown in FIG. 18.
  • charge transfer stages XFN 1 -XFNn are connected in series, similarly to the construction shown in FIG. 10A.
  • the construction arranged between internal node ND 2 and final output node FOD is the same as that shown in FIG. 10A. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • Each of charge transfer stages XFN 1 -XFNn has the same configuration as in charge transfer stage XFN shown in FIG. 10B.
  • the voltage level of internal node ND 2 changes between ground voltage GND and negative voltage ⁇ VCC, and charge transfer stage XFN 1 supplies negative charges to internal output node OD 1 from internal node ND 2 .
  • control signal ⁇ P is at the H level, and internal output node OD 1 has been precharged to negative voltage ⁇ VCC (in the stable operation), so that internal output node OD 1 is reliably set to the level of negative voltage ⁇ VCC in accordance with transfer control signal ⁇ CT.
  • MOS transistor NQ 2 is non-conductive, and internal node ND 3 is set to the ground voltage level in response to control signal ⁇ CT, and accordingly, MOS transistor NQ 1 turns conductive, so that the negative charges can be transferred between node ND 2 and OD 1 .
  • control signal ⁇ CP attains the H level
  • internal node ND 2 attains the ground voltage level
  • MOS transistor NQ 2 is turned on to connect electrically internal output node OD 1 to internal node ND 3 so that MOS transistor NQ 1 is reliably turned on.
  • control signal ⁇ P falls from the H level to the L level, the voltage level of internal output node OD 1 lowers from negative voltage ⁇ VCC to the negative voltage of ⁇ 2 ⁇ VCC.
  • MOS transistor NQ 2 is conductive, and MOS transistor NQ 1 has the source and drain made equal in potential to each other, and maintains the non-conductive state. Therefore, backflow of the negative charges does not occur.
  • capacitance element C 2 is provided for internal node ND 2 , and negative voltage of ⁇ n ⁇ VCC is produced on final output node FOD.
  • the negative potential of internal node ND 2 is changed between ground voltage GND and negative voltage ⁇ VCC, and accordingly, charge transfer stage XFN 1 can reliably transfer negative voltage ⁇ VCC to internal output node OD 1 when internal MOS transistor (NQ 1 ) for charge transfer is turned on in response to control signal ACT.
  • the charge transfer transistor (NQ 1 ) can be made non-conductive in charge transfer stage XFN 1 .
  • charge transfer stage XFN 1 therefore, the charge transfer operation can be controlled in accordance with control signal ⁇ CT, and therefore, the voltage drop by the amplitude of VCC can be caused in each of charge transfer stages XFN 1 -XFNn without causing an ineffective current flow.
  • charge transfer stages XFN 1 -XFNn in the voltage generating circuit shown in FIG. 24 are each formed of N-channel MOS transistors, and the basic negative charge producing stage producing the basic negative charges on internal node ND 2 is formed of N-channel MOS transistors NQQ 1 and NQQ 2 .
  • each stage is formed of the N-channel MOS transistors, and the negative voltage of ⁇ n ⁇ VCC at an intended level can be produced with a small circuit occupation area and reduced current consumption.
  • FIG. 25 shows a construction of a voltage generating circuit of a modification of the twelfth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 25 differs in configuration from the voltage generating circuit shown in FIG. 24 in the following points.
  • Precharge voltage supply node NDD 2 of N-channel MOS transistor NQQ 1 is connected to input node S 1 receiving control signal ⁇ P.
  • Other configuration of the voltage generating circuit shown in FIG. 25 is the same as that of the voltage generating circuit shown in FIG. 24. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • the operation waveforms of the voltage generating circuit shown in FIG. 25 are represented by those illustrated in FIG. 11.
  • ground voltage GND is not used for generating the negative voltage, so that the circuit configuration can be made simple as in the tenth embodiment, and thus, the manufacturing cost can be reduced.
  • each charge transfer stage is formed of the N-channel MOS transistors, the circuit configuration can be made simple. Also, the circuit layout area can be reduced, and the manufacturing cost can be made low.
  • FIG. 26 shows a construction of a voltage generating circuit according to a thirteenth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 26 differs in configuration from the voltage generating circuit shown in FIG. 16 in the following points.
  • the voltage generating circuit shown in FIG. 26 employs P-channel MOS transistors PQQ 1 and PQQ 2 as well as capacitance elements CQ 13 and C 12 , as in the construction shown in FIG. 20.
  • Precharge voltage supply node NDD 12 of MOS transistor PQQ 1 is coupled to power supply node PW, and receives power supply voltage VCC.
  • the circuit configuration for supplying the positive charges to internal node ND 12 is the same as the configuration shown in FIG. 20. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • charge transfer stages XFP 1 -XFPn of n stages are cascaded between internal node ND 12 and final output node FOD.
  • capacitance elements CC 1 -CCn ⁇ 1 are connected to internal output nodes ODP 1 -ODPn ⁇ 1 of charge transfer stages XFP 1 -XFPn ⁇ 1, respectively.
  • the connection and operation of these charge transfer stages XFP 1 -XFPn and capacitance elements CC 1 to CCn ⁇ 1 are the same as those of the voltage generating circuit shown in FIG. 18, and corresponding portions are allotted with the same reference numerals.
  • charge transfer stages XFP 1 -XFPn alternately perform the precharging of the internal nodes and the charge transfer operation
  • capacitance elements CC 1 to CCn ⁇ 1 alternately perform the precharging and the boosting of corresponding internal output nodes ODP 1 -ODPn ⁇ 1.
  • Internal node ND 12 changes in potential between power supply voltage VCC and high voltage 2 ⁇ VCC, similarly to the construction of the voltage generating circuit shown in FIG. 20.
  • charge transfer stage XFP 1 transmits high voltage 2 ⁇ VCC to internal output node ODP 1 (OD 11 )
  • capacitance element CC 1 further raises the voltage level of internal output node ODP 1 by voltage VCC in accordance with control signal ⁇ PZ. Therefore, charge transfer stages XFP 1 to XFPn ⁇ 1 produce on their respective output nodes the voltages boosted by the voltage VCC relative to the output node voltages in the preceding stages.
  • the operation waveforms of voltage generating circuit shown in FIG. 26 are represented by those of the voltage generating circuit shown in FIG. 19, and the high voltage of (n+1) ⁇ VCC can likewise be produced from power supply voltage VCC.
  • Charge transfer stages XFP 1 to XFPn are each formed of the P-channel MOS transistors, and the stage for supplying positive charges to internal node ND 12 is likewise formed of P-channel MOS transistors PQQ 1 and PQQ 2 , or of the MOS transistors of the same conductivity type. Therefore, the positive high voltage of (n+1) ⁇ VCC at any voltage level can be produced with the circuit of simplified configuration.
  • FIG. 27 shows a construction of a voltage generating circuit of a modification of the thirteenth embodiment of the invention.
  • the voltage generating circuit shown in FIG. 27 differs in configuration from the voltage generating circuit shown in FIG. 26 in the following points.
  • Precharge voltage supply node NDD 12 is coupled to input node S 11 receiving control signal ⁇ PZ.
  • Other configuration of the voltage generating circuit shown in FIG. 27 is the same as that of the voltage generating circuit shown in FIG. 26.
  • Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.
  • the voltage generating circuit shown in FIG. 27 does not use power supply voltage VCC for generating the high voltage of (n+1) ⁇ VCC. Therefore, the circuit configuration can be made simple.
  • a plurality of charge transfer stages are cascaded between the internal node and the final output node, and these charge transfer stages alternately perform the precharging of the output node and the charge transferring.
  • all the transistor elements are formed of the P-channel MOS transistors, and the charges can be efficiently transferred to produce a positive high voltage. Further, the circuit occupation area and the manufacturing cost can be reduced.
  • the voltage generating circuit according to the invention can be applied to a general LSI (Large Scale Integrated Circuit) as an embedded circuit producing an internal voltage.
  • the present invention can be generally applied to semiconductor device requiring a voltage at a level different from the power supply voltage and/or the ground voltage.
  • the voltage generating circuit according to the invention can be utilized for driving liquid crystal elements in a liquid crystal display device requiring positive and negative voltages.
  • the gate potential of each transistor is controlled by the charge pump operation of the capacitance element to generate the charges for generating an internal voltage, and conduction/non-conduction states of the transistors are individually and accurately controlled to produce the charges for generating the internal voltage.
  • flow of an ineffective current can be suppressed, and the charges can be efficiently used to generate an internal voltage at an intended level with reduced power consumption.

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JP4969322B2 (ja) * 2007-06-01 2012-07-04 三菱電機株式会社 電圧発生回路およびそれを備える画像表示装置
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JP5142861B2 (ja) * 2008-07-09 2013-02-13 パナソニック株式会社 内部電圧発生回路
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KR101764125B1 (ko) 2010-12-15 2017-08-02 삼성전자주식회사 음의 고전압 발생기 및 음의 고전압 발생기를 포함하는 비휘발성 메모리 장치
US8897073B2 (en) * 2012-09-14 2014-11-25 Freescale Semiconductor, Inc. NVM with charge pump and method therefor
KR102118277B1 (ko) * 2016-04-27 2020-06-02 도시바 미쓰비시덴키 산교시스템 가부시키가이샤 무정전 전원 장치
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DE102004024612A1 (de) 2004-12-23
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DE102004024612B4 (de) 2020-03-05
TWI240276B (en) 2005-09-21

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STCB Information on status: application discontinuation

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