US20040187976A1 - Phase change lead-free super plastic solders - Google Patents

Phase change lead-free super plastic solders Download PDF

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Publication number
US20040187976A1
US20040187976A1 US10/404,695 US40469503A US2004187976A1 US 20040187976 A1 US20040187976 A1 US 20040187976A1 US 40469503 A US40469503 A US 40469503A US 2004187976 A1 US2004187976 A1 US 2004187976A1
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United States
Prior art keywords
solder
lead
alloy
component comprises
free solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/404,695
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English (en)
Inventor
Fay Hua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US10/404,695 priority Critical patent/US20040187976A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUA, FAY
Priority to CN2004800087141A priority patent/CN1767921B/zh
Priority to EP04708990A priority patent/EP1608481A1/en
Priority to PCT/US2004/003385 priority patent/WO2004094097A1/en
Priority to KR1020057018602A priority patent/KR100841138B1/ko
Priority to TW093103220A priority patent/TWI273140B/zh
Priority to US10/933,966 priority patent/US20050029675A1/en
Publication of US20040187976A1 publication Critical patent/US20040187976A1/en
Priority to US11/073,277 priority patent/US7776651B2/en
Abandoned legal-status Critical Current

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
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Definitions

  • the field of invention relates generally to soldering processes and, more specifically but not exclusively relates to lead-free super plastic solders.
  • Solders are special composition metals (known as alloys) that, when in the presence of flux, melt at relatively low temperatures (120-450° C.).
  • the most commonly used solders contain tin and lead as base components.
  • Solder works by melting when it is heated, and bonding (wetting) to metallic surfaces.
  • the solder forms a permanent intermetallic bond between the metals joined, essentially acting like a metal “glue.”
  • solder joints also provide an electrical connection between soldered components and a heat transfer path.
  • Solders are available in many forms including paste, wire, bar, ribbon, preforms and ingots.
  • ICs such as microprocessors, graphics processors, microcontrollers, and the like are packaged in a manner that use of a large number of I/O lines.
  • Common packaging techniques employed for this purpose include “flip chip” packaging and ball grid array (BGA) packages. Both of these packaging techniques employ solder connections (joints) for each I/O line (e.g., pin or ball).
  • solder connections joints
  • I/O line e.g., pin or ball
  • Flip Chip is not a specific package (like SOIC), or even a package type (like BGA).
  • Flip chip describes the method of electrically connecting the die to the package carrier.
  • the package carrier either substrate or leadframe, then provides the connection from the die to the exterior of the package.
  • “standard” packaging the interconnection between the die and the carrier is made using wire.
  • the die is attached to the carrier face up, then a wire is bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35 ⁇ cm in diameter.
  • the interconnection between the die and carrier in flip chip packaging is made through a conductive “bump” that is placed directly on the die surface.
  • the bumped die is then “flipped over” and placed face down, with the bumps connecting to the carrier directly.
  • a bump is typically 70-100 ⁇ m high, and 100-125 ⁇ m in diameter.
  • the flip chip connection is generally formed one of two ways: using solder or using conductive adhesive.
  • solder the most common packaging interconnect is solder, high 97Pb-3Sn at die side and attached with eutectic Pb—Sn to substrate.
  • the solder bumped die is attached to a substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior.
  • underfill is added between the die and the substrate. Underfill is a specially engineered epoxy that fills the area between the die and the carrier, surrounding the solder bumps. It is designed to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier, as described in further detail below.
  • the underfill absorbs much of the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package.
  • the chip attach and underfill steps are the basics of flip chip interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and can generally utilize existing manufacturing processes and package formats.
  • the leading candidate solders are near-ternary eutectic Sn—Ag—Cu alloys for various soldering applications.
  • the near-eutectic ternary Sn—Ag—Cu alloys yield three phases upon solidification, ⁇ -Sn, Ag 3 Sn and Cu 6 Sn 5 .
  • the equilibrium eutectic transformation is kinetically inhibited.
  • the Ag 3 Sn phase nucleates with minimal undercooling
  • the ⁇ -Sn phase requires a typical undercooling of 15 to 30° C. for nucleation.
  • FIGS. 1 a - 1 c are cross-section views illustrating a conventional flip-chip assembly process, wherein FIG. 1 a illustrates a condition at a solder reflow temperature, FIG. 1 b illustrates a condition after the assembly has cooled, and FIG. 1 c illustrates a condition after an underfill is added and a cap is molded over the assembly;
  • FIG. 2 is a phase diagram corresponding to an Sn—In alloy
  • FIG. 3 is a schematic diagram illustrating a change in lattice structure for an Sn—In alloy as it cooled from a high temperature to a low temperature;
  • FIG. 4 is a graph illustrating relative percentage of the phase change vs. temperature and Sn—In weight ratios
  • FIG. 5 is a microscopic scan illustrating formation of Martensite for an Sn-7In allow that is air cooled;
  • FIG. 6 is a microscopic scan illustrating results of a martensitic phase transformation for Sn-9In that was formed under a compression stress.
  • FIG. 7 is a graph illustrating displacement characteristics of Silicon (Si) and Sn-7In vs. temperature under a typical cooling rate
  • solder compositions Details of lead-free solder compositions and exemplary uses for the solders are described herein. In the following description, numerous specific details are set forth, such as implementing the lead-free solder for flip-chip packaging, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
  • a typical flip-chip assembly includes a substrate 100 having a plurality of pads 102 on which respective solder bumps 104 are formed. Substrate 100 further includes a plurality of solder balls 106 coupled to its underside. Respective leads 108 are routed between each pad 102 and solder ball 106 .
  • An integrated circuit die 110 is “flip-chip” mounted to substrate 100 by means of solder bumps 104 . To facilitate electronic connections to the die circuitry, die includes a plurality of pads 112 mounted to it underside, each of which are connected to a respective portion of the die circuitry via electrical lines (not shown) passing through an inner layer dielectric (ILD) 114 .
  • the ILD typically comprises a dielectric layer that is formed over the die substrate, such as silicon dioxide for a silicon die substrate.
  • the flip-chip components are assembled by raising the temperature of the solder bumps until the solder's reflow temperature is reached, causing the solder bumps to melt. This is typically performed in a reflow oven or the like. Subsequently, the assembled components are cooled, resulting in reversion of the solder back to its solid state, thereby forming a metallic bond between pads 102 and 112 .
  • the substrate will be formed of a rigid material, such as a rigid laminate.
  • the die and inner layer dielectric is typically formed from a semiconductive substrate, such as silicon.
  • Silicon has a typical coefficient of thermal expansion (CTE) of 2-4 parts per million (ppm) per degree Celsius.
  • CTE coefficient of thermal expansion
  • the CTE for a typical flip-chip substrate is approximately 16-19 ppm/° C. This difference in CTE's leads to induced stresses in the solder bumps and inner layer dielectric, as follows.
  • the substrate and die have respective relative length L S1 and L D1 in accordance with that shown in FIG. 1 a.
  • the relative lengths are reduced, as shown by lengths L S2 and L D2 in FIG. 1 b.
  • the respective reductions in length are depicted as ⁇ L S and ⁇ L D , wherein ⁇ L D is shown as substantially 0 for clarity. Since the CTE for the die is much less than the CTE for the substrate, ⁇ L S is much greater than ⁇ L D .
  • solder bumps 104 are caused to elongate, as shown by solder bumps 104 A in FIG. 1 b.
  • solder bumps 104 A For example, consider the configuration of the solder bumps when the assembled components are cooled to a temperature just below the reflow temperature. At this point, the length of the components is substantially the same as that for the reflow configuration of FIG. 1 a. The solder is in a solid state, although it is fairly ductile due to the elevated temperature. The solidified solder of each solder bump adheres to respective pairs of pads 102 and 112 . As the cooling of the components continues, the length of substrate 100 is reduced by a greater amount than the length of die 110 . As a result, the solder bumps are caused to be elongated (strained), inducing a stress in the solder material. Additionally, a portion of the stress is transferred through pads 112 to ILD 114 .
  • die 110 During operation, die 110 generates heat in correspondence with resistance losses in its circuitry. As a result, the temperature of the die, as well as nearby thermally-coupled components including substrate 100 , increase. When the die circuitry is operating under a high workload condition, its temperature is higher, while lower workload operations result in a lower temperature, and of course no operation results in a still lower temperature. As a result, operation of the die circuitry induces thermal cycling and corresponding stress cycling on the solder bumps due to the CTE mismatch. This in turn may lead to failure conditions, such as pad peel off and ILD cracking.
  • One technique commonly used to reduce the thermal cycling stress-related failures is to fill the volume proximate to solder bumps 104 with an epoxy underfill 116 , as shown in FIG. 1 c.
  • the packaging process is usually then completed by molding a cap 118 over the top of the various assembly components.
  • an underfill is employed in this manner, the stress load is placed across the cross section of the combination of the solder bump/pad interfaces and the underfill rather than just the solder bump/pad interfaces alone. This reduces the stress on the bulk solder and solder bump/pad interfaces to some degree, but doesn't entirely remove the stress. More importantly, the residual stress built into the solder bumps (which is concurrently transferred to the solder bump/pad interfaces) as a result of the initial cooling from reflow to room temperature remains the same, since the underfill is not added until after the components have cooled.
  • solder bumps 104 would typically comprise a lead-based solder, such as those discussed above. Such solders generally exhibit good plasticity (are very ductile) throughout the temperature ranges the package components are typically expose to. As a result, failure due to pad peel-off and ILD cracking are fairly uncommon.
  • solder bumps for these products must comprise a lead-free material.
  • Sn—Ag—Cu alloys have become the leading candidate solders for replacing lead-based solders. This leads to a problems in many applications, since Sn—Ag—Cu solders do not exhibit good plasticity when compared with lead-based solders, leading to the failure modes discussed above.
  • the lead-free solder comprises a Sn—In alloy, wherein the weight % ratio, wt. % is 4-15% Indium (85-96 wt. % Sn).
  • the super plasticity is due to a phase change in the Sn—In alloy as it is cooled from its reflow temperature to room temperature. This phase change dramatically reduced the residual stress problem associated with flip-chip assemblies and the like.
  • FIG. 2 is phase diagram of Sn—In alloy system.
  • the ratio of In to Sn is 4-15% wt. %
  • the phase transformation can happen as a Martensite transformation (Y. Koyama, H.suzuki and O. Nittono, Scripta Metallurgica, vol. 18, pp.715-717, 1984). It has been realized by the inventor that this Martensite transformation is an advantageous feature of 4-15% wt. % Sn—In alloys with regard to it use for solder joints.
  • the bulk solder will elongate in a manner that compensates for the CTE mismatch between joined components, such as a die and substrate, with minimum introduction of stress in the solder joints. Furthermore, a reduction in the stress in the inner layer dielectric will also result. These improved solder characteristics lead to increased package reliability.
  • FIG. 3 A schematic diagram illustrating the phase change at the molecular level is shown in FIG. 3.
  • the Sn—In alloy lattice structure corresponds to the packed hexagonal ⁇ phase bco (body-centered orthorhombic) structure 300 .
  • the corners of each plane are alternately occupied by Sn atoms 302 (light colored) and In atoms 304 (dark colored).
  • the atoms are separated along one planel axis by a distance “a” and along the other planel axis by a distance of ⁇ square root ⁇ square root over (3) ⁇ a.
  • the planes are separated by a distance “c”; thus the distance between Sn planes is 2c.
  • FIG. 4 shows the phase-transformation behavior of several Sn—In alloys over a normal cooling range. As the temperature is lowered, more ⁇ bco phase transfers to ⁇ -Sn bct phase. It is further noted that as the wt. % In is decreased, the percentage of phase transformation at a given temperature increases. As a result, the plasticity behavior of a particular Sn—In alloy can be tailored to suit a targeted application in which it is to be used.
  • Martinsite transformation that occurs when the alloy is cooled.
  • Martinsite and “martensitic” transformations concern diffusionless crystallographic changes that are used to change the material properties of alloys.
  • German metallographier A. Martens was the first to identify such a crystallographic change in iron-carbon steels, and thus Martensite is named after him.
  • martensitic transformation form plates, needles, or leaf-like structures in the new phase.
  • the Martensite structures change the material properties of the alloy. For example, it common to heat-treat steels to form Martensite on wear surfaces, such as knives and the like. Under this type of use, the martensitic structure comprises a hardened material at the surface of the steel that is very wear-resistant. Although increased hardness is often beneficial, a downside is a loss in ductility: martensitic steels are generally classified as brittle materials (when compared with non-martensitic phases of corresponding steel alloy, such as annealed steel).
  • martensitic steels exhibit brittle (i.e., non-ductile) behavior
  • other martensitic alloys exhibit substantially different behaviors, including super plasticity.
  • some memory metals i.e., a class of metals that can be deformed and returned to their undeformed shape
  • employ a martensitic phase i.e., a class of metals that can be deformed and returned to their undeformed shape
  • the metallurgical reason for the Martensite deformability is considered to be the “twinned” structure of the phase: the twin boundaries can be moved without much force and without formation of dislocations, which are typically considered to initiate material fracture.
  • a further advantage of this structure is the material is not prone to strain hardening, which leads to a decrease in ductility over time as a material is exposed to strain cycling. Such cycling occurs as a result of the temperature cycling of the die in the foregoing flip-chip application. Thus, a conventional solder becomes hardened over time, leading to the formation of fatigue cracking and eventual joint failure.
  • FIGS. 5 and 6 Details of microscopic structures that result from martensitic phase transformations are shown in FIGS. 5 and 6.
  • FIG. 5 shows a microscopic scan of an Sn-7In (i.e., 7 wt. % In) alloy that has been exposed to air cooling. Note the “needle”-like structure shown in the central portion of the scan.
  • FIG. 6 shown a result of a martensitic phase transformation for Sn-9In that was formed under a compression stress. In this case, the direction of the martensitic structure coincides with the material strain.
  • Displacement characteristics of Silicon (Si) and Sn-7In vs. temperature are shown in FIG. 7. As shown in the figure, the relative displacement of Si substantially mirrors the temperature profile, as would be expected with a constant CTE value. Initially, the Sn-7In alloy exhibits a similar proportional behavior, until the temperature is falls through the range of approximately 80-70° C. During this time frame, a martensitic transformation takes place. After the transformation has occurred, the displacement of the Sn-7In alloy remains substantially constant even the temperature continues to be reduced.
  • FIGS. 6 and 7 The behavior shown in FIGS. 6 and 7 is directly applicable to the flip-chip CTE mismatch problem discussed above.
  • the CTE mismatch between the die and substrate materials causes a strain to be induced on the solder bumps. This, in turn, results in stresses within the bulk solder material, and more importantly, at the solder bump/pad interfaces.
  • an Sn—In solder having the weight ratios disclosed herein is used, a martinsitic phase change under stress occurs.
  • the bulk solder elongates in the direction of the stress as the solder cools, substantially eliminating the residual stress in the solder bumps that result from the CTE mismatch.
  • the foregoing principles may be applied to other types of solder joints as well.
  • problems similar to the flip-chip CTE mismatch result in joint failures for BGA packages.
  • the CTE mismatch is between the package material, typically a ceramic or the like, and the circuit board to which it is attached, typically a multi-layer fiberglass.
  • these alloys may be altered by adding small amounts of various metals to produce targeted behaviors.
  • small amounts e.g. ⁇ 2 wt. % of Sb, Cu, Ag, Ni, Ge, and Al may be added to further refine the as-cast microstructure and improve thermal stability.
  • the particular wt. % of these metals that is optimal will generally be dependent on the particular application the solder is to be used in. Such factors include solder reflow temperature, plasticity requirements, expected thermal cycling temperature ranges, etc.
  • the super-plastic solder alloys described herein are not only very ductile, but also resistant to fatigue. Under typical fatigue loading (e.g., cyclical inducement of strain due to temperature cycling), a conventional solder undergoes a change in its structure. This structural change weakens the bulk material over time, eventually leading to failure. In contrast, the deformation of the super-plastic solder alloys due to the phase change mechanism does not cause a similar level of damage to the bulk material. As a result, the super-plastic solder alloys may be successfully employed in application that would normally lead to fatigue failures when implemented with conventional solders.
  • the super-plastic solders are well-suited for applications in which the joined materials have CTE mismatches.
  • the foregoing discussion of uses of the solders for die to flip-chip substrate bonding and BGA packing are merely exemplary uses of the super-plastic solders.
  • the solders may be employed in bonding solderable materials having CTE mismatches. Further examples of such uses include bonding an integrated heatsink (IHS) to a die. In this instance, solder further performs the function of the thermal interface material used in conventional IHS to die couplings.
  • IHS integrated heatsink

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US10/404,695 2003-03-31 2003-03-31 Phase change lead-free super plastic solders Abandoned US20040187976A1 (en)

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US10/404,695 US20040187976A1 (en) 2003-03-31 2003-03-31 Phase change lead-free super plastic solders
CN2004800087141A CN1767921B (zh) 2003-03-31 2004-02-06 无铅相变超塑性焊料及使用其进行焊接的方法
EP04708990A EP1608481A1 (en) 2003-03-31 2004-02-06 Phase change lead-free super plastic solders
PCT/US2004/003385 WO2004094097A1 (en) 2003-03-31 2004-02-06 Phase change lead-free super plastic solders
KR1020057018602A KR100841138B1 (ko) 2003-03-31 2004-02-06 무연 솔더 합금 및 이 합금을 이용한 솔더링 방법
TW093103220A TWI273140B (en) 2003-03-31 2004-02-11 Phase change lead-free super plastic solders
US10/933,966 US20050029675A1 (en) 2003-03-31 2004-09-03 Tin/indium lead-free solders for low stress chip attachment
US11/073,277 US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

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US11/073,277 Division US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

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US7776651B2 (en) 2010-08-17
TW200424322A (en) 2004-11-16
CN1767921A (zh) 2006-05-03
WO2004094097A1 (en) 2004-11-04
US20050153523A1 (en) 2005-07-14
EP1608481A1 (en) 2005-12-28
KR20050119175A (ko) 2005-12-20
KR100841138B1 (ko) 2008-06-24
CN1767921B (zh) 2011-09-14

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