US20040187976A1 - Phase change lead-free super plastic solders - Google Patents

Phase change lead-free super plastic solders Download PDF

Info

Publication number
US20040187976A1
US20040187976A1 US10/404,695 US40469503A US2004187976A1 US 20040187976 A1 US20040187976 A1 US 20040187976A1 US 40469503 A US40469503 A US 40469503A US 2004187976 A1 US2004187976 A1 US 2004187976A1
Authority
US
United States
Prior art keywords
lead
solder
alloy
component
free solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/404,695
Inventor
Fay Hua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US10/404,695 priority Critical patent/US20040187976A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUA, FAY
Priority claimed from US10/933,966 external-priority patent/US20050029675A1/en
Publication of US20040187976A1 publication Critical patent/US20040187976A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262Sn as the principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00Articles made by soldering, welding or cutting
    • B23K2101/36Electric or electronic devices
    • B23K2101/42Printed circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01063Europium [Eu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process

Abstract

Lead-free solders comprising 85-96% tin (Sn) and 4-15% Indium (In) by weight percentage (wt. %) and exemplary uses of the same are disclosed. The Sn—In solder undergoes a martensitic phase change when it is cooled from a reflow temperature to room temperature. As a result, residual stresses that would normally occur due to solder strain caused by relative movement between joined components are substantially reduced. Typically, the relative movement results from a coefficient of thermal expansion (CTE) mismatch between the joined components. The disclosed exemplary uses include flip-chip assembly and IC package to circuit board mounting, such as ball grid array packages.

Description

    FIELD OF THE INVENTION
  • The field of invention relates generally to soldering processes and, more specifically but not exclusively relates to lead-free super plastic solders. [0001]
  • BACKGROUND INFORMATION
  • Solders are special composition metals (known as alloys) that, when in the presence of flux, melt at relatively low temperatures (120-450° C.). The most commonly used solders contain tin and lead as base components. Many alloy variations exist that include two or more of the following metallic elements: tin (Sn), lead (Pb), silver (Ag), bismuth (Bi), antimony (Sb) and copper (Cu). Solder works by melting when it is heated, and bonding (wetting) to metallic surfaces. The solder forms a permanent intermetallic bond between the metals joined, essentially acting like a metal “glue.” In addition to providing a bonding function, solder joints also provide an electrical connection between soldered components and a heat transfer path. Solders are available in many forms including paste, wire, bar, ribbon, preforms and ingots. [0002]
  • Many high-density integrated circuits (ICs), such as microprocessors, graphics processors, microcontrollers, and the like are packaged in a manner that use of a large number of I/O lines. Common packaging techniques employed for this purpose include “flip chip” packaging and ball grid array (BGA) packages. Both of these packaging techniques employ solder connections (joints) for each I/O line (e.g., pin or ball). In conjunction with the every-increasing density of complex ICs, a corresponding increase in the I/O connection density of flip chip and BGA has occurred. As a result, the solder joints employed in the packages have had to be reduced in size. [0003]
  • More specifically, Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip chip describes the method of electrically connecting the die to the package carrier. The package carrier, either substrate or leadframe, then provides the connection from the die to the exterior of the package. In “standard” packaging, the interconnection between the die and the carrier is made using wire. The die is attached to the carrier face up, then a wire is bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35 ∝cm in diameter. In contrast, the interconnection between the die and carrier in flip chip packaging is made through a conductive “bump” that is placed directly on the die surface. The bumped die is then “flipped over” and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 μm high, and 100-125 μm in diameter. [0004]
  • The flip chip connection is generally formed one of two ways: using solder or using conductive adhesive. By far, the most common packaging interconnect is solder, high 97Pb-3Sn at die side and attached with eutectic Pb—Sn to substrate. The solder bumped die is attached to a substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior. After the die is soldered, underfill is added between the die and the substrate. Underfill is a specially engineered epoxy that fills the area between the die and the carrier, surrounding the solder bumps. It is designed to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier, as described in further detail below. Once cured, the underfill absorbs much of the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package. The chip attach and underfill steps are the basics of flip chip interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and can generally utilize existing manufacturing processes and package formats. [0005]
  • Recently, the European Union has mandated that no new products sold after May 31, 2003 contain lead-based solder. Other counties and regions are considering similar restrictions. This poses a problem for manufactures of IC products, as well as for other industries that employ soldering processes during product manufacture. Although many Pb-free solders are well-known, these solders have properties that make them disadvantageous when compared with lead-based solders, including reduction in ductility (plasticity). This is especially problematic in flip-chip and BGA assembly processes. [0006]
  • Owing to active R & D efforts, substantial progress toward a full transition to Pb-free soldering technology has been made recently. At present, the leading candidate solders are near-ternary eutectic Sn—Ag—Cu alloys for various soldering applications. The near-eutectic ternary Sn—Ag—Cu alloys yield three phases upon solidification, β-Sn, Ag[0007] 3Sn and Cu6Sn5. During solidification, the equilibrium eutectic transformation is kinetically inhibited. While the Ag3Sn phase nucleates with minimal undercooling, the β-Sn phase requires a typical undercooling of 15 to 30° C. for nucleation. As a consequence of this disparity in the required undercooling, large, plate-like Ag3Sn structures can grow rapidly within the liquid phase, during cooling, before the final solidification of solder joints. When large Ag3Sn plates are present in solder joints, they may adversely affect the mechanical behavior and possibly reduce the fatigue life of solder joints by providing a preferential crack propagation path along the interface between a large Ag3Sn plate and the β-Sn phase. Further problems common to Sn—Ag—Cu solders include ILD (inner layer dielectric) cracking and pad peel off at the substrate for flip chip assemblies, and pad peel off at the BGA side for BGA packages.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified: [0008]
  • FIGS. 1[0009] a-1 c are cross-section views illustrating a conventional flip-chip assembly process, wherein FIG. 1a illustrates a condition at a solder reflow temperature, FIG. 1b illustrates a condition after the assembly has cooled, and FIG. 1c illustrates a condition after an underfill is added and a cap is molded over the assembly;
  • FIG. 2 is a phase diagram corresponding to an Sn—In alloy; [0010]
  • FIG. 3 is a schematic diagram illustrating a change in lattice structure for an Sn—In alloy as it cooled from a high temperature to a low temperature; [0011]
  • FIG. 4 is a graph illustrating relative percentage of the phase change vs. temperature and Sn—In weight ratios; [0012]
  • FIG. 5 is a microscopic scan illustrating formation of Martensite for an Sn-7In allow that is air cooled; [0013]
  • FIG. 6 is a microscopic scan illustrating results of a martensitic phase transformation for Sn-9In that was formed under a compression stress; and [0014]
  • FIG. 7 is a graph illustrating displacement characteristics of Silicon (Si) and Sn-7In vs. temperature under a typical cooling rate; [0015]
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Details of lead-free solder compositions and exemplary uses for the solders are described herein. In the following description, numerous specific details are set forth, such as implementing the lead-free solder for flip-chip packaging, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. [0016]
  • Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. [0017]
  • With reference to FIGS. 1[0018] a and 1 b, a typical flip-chip assembly includes a substrate 100 having a plurality of pads 102 on which respective solder bumps 104 are formed. Substrate 100 further includes a plurality of solder balls 106 coupled to its underside. Respective leads 108 are routed between each pad 102 and solder ball 106. An integrated circuit die 110 is “flip-chip” mounted to substrate 100 by means of solder bumps 104. To facilitate electronic connections to the die circuitry, die includes a plurality of pads 112 mounted to it underside, each of which are connected to a respective portion of the die circuitry via electrical lines (not shown) passing through an inner layer dielectric (ILD) 114. The ILD typically comprises a dielectric layer that is formed over the die substrate, such as silicon dioxide for a silicon die substrate.
  • The flip-chip components are assembled by raising the temperature of the solder bumps until the solder's reflow temperature is reached, causing the solder bumps to melt. This is typically performed in a reflow oven or the like. Subsequently, the assembled components are cooled, resulting in reversion of the solder back to its solid state, thereby forming a metallic bond between pads [0019] 102 and 112.
  • Typically, the substrate will be formed of a rigid material, such as a rigid laminate. Meanwhile, the die and inner layer dielectric is typically formed from a semiconductive substrate, such as silicon. Silicon has a typical coefficient of thermal expansion (CTE) of 2-4 parts per million (ppm) per degree Celsius. The CTE for a typical flip-chip substrate is approximately 16-19 ppm/° C. This difference in CTE's leads to induced stresses in the solder bumps and inner layer dielectric, as follows. [0020]
  • At the reflow temperature, the substrate and die have respective relative length L[0021] S1 and LD1 in accordance with that shown in FIG. 1a. As the assembly is cooled, the relative lengths are reduced, as shown by lengths LS2 and LD2 in FIG. 1b. The respective reductions in length are depicted as ΔLS and ΔLD, wherein ΔLD is shown as substantially 0 for clarity. Since the CTE for the die is much less than the CTE for the substrate, ΔLS is much greater than ΔLD.
  • As a result of the CTE mismatch, solder bumps [0022] 104 are caused to elongate, as shown by solder bumps 104A in FIG. 1b. For example, consider the configuration of the solder bumps when the assembled components are cooled to a temperature just below the reflow temperature. At this point, the length of the components is substantially the same as that for the reflow configuration of FIG. 1a. The solder is in a solid state, although it is fairly ductile due to the elevated temperature. The solidified solder of each solder bump adheres to respective pairs of pads 102 and 112. As the cooling of the components continues, the length of substrate 100 is reduced by a greater amount than the length of die 110. As a result, the solder bumps are caused to be elongated (strained), inducing a stress in the solder material. Additionally, a portion of the stress is transferred through pads 112 to ILD 114.
  • During operation, die [0023] 110 generates heat in correspondence with resistance losses in its circuitry. As a result, the temperature of the die, as well as nearby thermally-coupled components including substrate 100, increase. When the die circuitry is operating under a high workload condition, its temperature is higher, while lower workload operations result in a lower temperature, and of course no operation results in a still lower temperature. As a result, operation of the die circuitry induces thermal cycling and corresponding stress cycling on the solder bumps due to the CTE mismatch. This in turn may lead to failure conditions, such as pad peel off and ILD cracking.
  • One technique commonly used to reduce the thermal cycling stress-related failures is to fill the volume proximate to solder bumps [0024] 104 with an epoxy underfill 116, as shown in FIG. 1c. The packaging process is usually then completed by molding a cap 118 over the top of the various assembly components. When an underfill is employed in this manner, the stress load is placed across the cross section of the combination of the solder bump/pad interfaces and the underfill rather than just the solder bump/pad interfaces alone. This reduces the stress on the bulk solder and solder bump/pad interfaces to some degree, but doesn't entirely remove the stress. More importantly, the residual stress built into the solder bumps (which is concurrently transferred to the solder bump/pad interfaces) as a result of the initial cooling from reflow to room temperature remains the same, since the underfill is not added until after the components have cooled.
  • Under prior manufacturing techniques, solder bumps [0025] 104 would typically comprise a lead-based solder, such as those discussed above. Such solders generally exhibit good plasticity (are very ductile) throughout the temperature ranges the package components are typically expose to. As a result, failure due to pad peel-off and ILD cracking are fairly uncommon.
  • However, the use of lead-based solders is not a viable option henceforth for many manufactured products, such as products designated for sale to EU countries. Thus, the solder bumps for these products must comprise a lead-free material. As discussed above, Sn—Ag—Cu alloys have become the leading candidate solders for replacing lead-based solders. This leads to a problems in many applications, since Sn—Ag—Cu solders do not exhibit good plasticity when compared with lead-based solders, leading to the failure modes discussed above. [0026]
  • In accordance with principles of the invention, a lead-free solder compound with super plasticity is now disclosed. In one embodiment, the lead-free solder comprises a Sn—In alloy, wherein the weight % ratio, wt. % is 4-15% Indium (85-96 wt. % Sn). The super plasticity is due to a phase change in the Sn—In alloy as it is cooled from its reflow temperature to room temperature. This phase change dramatically reduced the residual stress problem associated with flip-chip assemblies and the like. [0027]
  • FIG. 2 is phase diagram of Sn—In alloy system. When the ratio of In to Sn is 4-15% wt. %, there is a high temperature packed hexagonal γ phase to lower temperature β-Sn bct (body-centered tetragonal) transition. It has been demonstrated that the phase transformation can happen as a Martensite transformation (Y. Koyama, H.suzuki and O. Nittono, Scripta Metallurgica, vol. 18, pp.715-717, 1984). It has been realized by the inventor that this Martensite transformation is an advantageous feature of 4-15% wt. % Sn—In alloys with regard to it use for solder joints. More specifically, in accordance with the Martensite transformation, the bulk solder will elongate in a manner that compensates for the CTE mismatch between joined components, such as a die and substrate, with minimum introduction of stress in the solder joints. Furthermore, a reduction in the stress in the inner layer dielectric will also result. These improved solder characteristics lead to increased package reliability. [0028]
  • A schematic diagram illustrating the phase change at the molecular level is shown in FIG. 3. At higher temperature, the Sn—In alloy lattice structure corresponds to the packed hexagonal γ phase bco (body-centered orthorhombic) structure [0029] 300. In this structure, the corners of each plane are alternately occupied by Sn atoms 302 (light colored) and In atoms 304 (dark colored). The atoms are separated along one planel axis by a distance “a” and along the other planel axis by a distance of {square root}{square root over (3)}a. The planes are separated by a distance “c”; thus the distance between Sn planes is 2c. As the alloy cools, a phase transformation from γ phase bco structure 300 to a β-Sn bct (body-centered tetragonal) structure 306. This results from a translation of In atoms relative to the Sn atoms of a/4. At the same time, the distance between the planes is decreased, such that the distance between two Sn planes is reduced to {square root}{square root over (3)}a. This results in a shortening of the lattice structure in one direction, and a lengthening in a perpendicular direction.
  • FIG. 4 shows the phase-transformation behavior of several Sn—In alloys over a normal cooling range. As the temperature is lowered, more γ bco phase transfers to β-Sn bct phase. It is further noted that as the wt. % In is decreased, the percentage of phase transformation at a given temperature increases. As a result, the plasticity behavior of a particular Sn—In alloy can be tailored to suit a targeted application in which it is to be used. [0030]
  • Further aspects of the invention relate to a Martinsite transformation that occurs when the alloy is cooled. In general, Martinsite and “martensitic” transformations concern diffusionless crystallographic changes that are used to change the material properties of alloys. German metallographier A. Martens was the first to identify such a crystallographic change in iron-carbon steels, and thus Martensite is named after him. [0031]
  • Depending on the type of martensitic transformation, which is generally dependent upon the alloyed elements and/or heat treatment parameters, martensitic transformation form plates, needles, or leaf-like structures in the new phase. The Martensite structures change the material properties of the alloy. For example, it common to heat-treat steels to form Martensite on wear surfaces, such as knives and the like. Under this type of use, the martensitic structure comprises a hardened material at the surface of the steel that is very wear-resistant. Although increased hardness is often beneficial, a downside is a loss in ductility: martensitic steels are generally classified as brittle materials (when compared with non-martensitic phases of corresponding steel alloy, such as annealed steel). [0032]
  • Although martensitic steels exhibit brittle (i.e., non-ductile) behavior, other martensitic alloys exhibit substantially different behaviors, including super plasticity. For example, some memory metals (i.e., a class of metals that can be deformed and returned to their undeformed shape) employ a martensitic phase. In this instance, the metallurgical reason for the Martensite deformability is considered to be the “twinned” structure of the phase: the twin boundaries can be moved without much force and without formation of dislocations, which are typically considered to initiate material fracture. [0033]
  • A further advantage of this structure is the material is not prone to strain hardening, which leads to a decrease in ductility over time as a material is exposed to strain cycling. Such cycling occurs as a result of the temperature cycling of the die in the foregoing flip-chip application. Thus, a conventional solder becomes hardened over time, leading to the formation of fatigue cracking and eventual joint failure. [0034]
  • Details of microscopic structures that result from martensitic phase transformations are shown in FIGS. 5 and 6. FIG. 5 shows a microscopic scan of an Sn-7In (i.e., 7 wt. % In) alloy that has been exposed to air cooling. Note the “needle”-like structure shown in the central portion of the scan. FIG. 6 shown a result of a martensitic phase transformation for Sn-9In that was formed under a compression stress. In this case, the direction of the martensitic structure coincides with the material strain. [0035]
  • Displacement characteristics of Silicon (Si) and Sn-7In vs. temperature are shown in FIG. 7. As shown in the figure, the relative displacement of Si substantially mirrors the temperature profile, as would be expected with a constant CTE value. Initially, the Sn-7In alloy exhibits a similar proportional behavior, until the temperature is falls through the range of approximately 80-70° C. During this time frame, a martensitic transformation takes place. After the transformation has occurred, the displacement of the Sn-7In alloy remains substantially constant even the temperature continues to be reduced. [0036]
  • The behavior shown in FIGS. 6 and 7 is directly applicable to the flip-chip CTE mismatch problem discussed above. As discussed above, as the assembly is cooled, the CTE mismatch between the die and substrate materials causes a strain to be induced on the solder bumps. This, in turn, results in stresses within the bulk solder material, and more importantly, at the solder bump/pad interfaces. When an Sn—In solder having the weight ratios disclosed herein is used, a martinsitic phase change under stress occurs. Thus, the bulk solder elongates in the direction of the stress as the solder cools, substantially eliminating the residual stress in the solder bumps that result from the CTE mismatch. [0037]
  • The foregoing principles may be applied to other types of solder joints as well. For example, problems similar to the flip-chip CTE mismatch result in joint failures for BGA packages. In this instance, the CTE mismatch is between the package material, typically a ceramic or the like, and the circuit board to which it is attached, typically a multi-layer fiberglass. [0038]
  • In addition to the Sn—In alloy compositions discussed above, these alloys may be altered by adding small amounts of various metals to produce targeted behaviors. For example, small amounts (e.g. <2 wt. %) of Sb, Cu, Ag, Ni, Ge, and Al may be added to further refine the as-cast microstructure and improve thermal stability. The particular wt. % of these metals that is optimal will generally be dependent on the particular application the solder is to be used in. Such factors include solder reflow temperature, plasticity requirements, expected thermal cycling temperature ranges, etc. [0039]
  • The super-plastic solder alloys described herein are not only very ductile, but also resistant to fatigue. Under typical fatigue loading (e.g., cyclical inducement of strain due to temperature cycling), a conventional solder undergoes a change in its structure. This structural change weakens the bulk material over time, eventually leading to failure. In contrast, the deformation of the super-plastic solder alloys due to the phase change mechanism does not cause a similar level of damage to the bulk material. As a result, the super-plastic solder alloys may be successfully employed in application that would normally lead to fatigue failures when implemented with conventional solders. [0040]
  • As discussed above, the super-plastic solders are well-suited for applications in which the joined materials have CTE mismatches. The foregoing discussion of uses of the solders for die to flip-chip substrate bonding and BGA packing are merely exemplary uses of the super-plastic solders. In general, the solders may be employed in bonding solderable materials having CTE mismatches. Further examples of such uses include bonding an integrated heatsink (IHS) to a die. In this instance, solder further performs the function of the thermal interface material used in conventional IHS to die couplings. [0041]
  • The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. [0042]
  • These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. [0043]

Claims (28)

What is claimed is:
1. A lead-free solder alloy comprising 85-96% tin (Sn) and 4-15% Indium (In) by weight percentage (wt. %).
2. The lead-free solder alloy of claim 1, further comprising at least one element from the following group: Sb, Cu, Ag, Ni, Ge, and Al.
3. The lead-free solder alloy of claim 2, wherein the combined wt. % of said at least one element is less than 2 percent.
4. The lead-free solder alloy of claim 1, wherein the wt. % of In is 7%.
5. The lead-free solder alloy of claim 1, wherein the wt. % of In is 8%.
6. The lead-free solder alloy of claim 1, wherein the wt. % of In is 9%.
7. The lead-free solder alloy of claim 1, wherein the wt. % of In is 10%.
8. A lead-free solder alloy, having a composition that undergoes a martensitic phase transformation when it is cooled from a reflow temperature to room temperature.
9. The lead-free solder alloy of claim 8, wherein the alloy is tin (Sn) based, and wherein the martensitic phase transformation transforms a lattice structure of the alloy from a packed hexagonal γ phase bco (body-centered orthorhombic) to a β-Sn bct (body-centered tetragonal) structure.
10. The lead free solder alloy of claim 9, wherein the alloy has a composition comprising at least 85 percentage by weight (wt. %) Sn and at least 4 wt. % Indium (In).
11. A method for joining first and second components, comprising:
disposing a lead-free solder between said first and second components, said solder comprising 85-96% tin (Sn) and 4-15% Indium (In) by weight percentage (wt. %);
heating the solder to a reflow temperature; and
cooling the first and second components to re-solidify the solder.
12. The method of claim 11, wherein the solder further comprises at least one element from the following group: Sb, Cu, Ag, Ni, Ge, and Al.
13. The method of claim 12, wherein the combined wt. % of said at least one element is less than 2 percent.
14. The method of claim 11, wherein the wt. % of In is 7%.
15. The method of claim 11, wherein the wt. % of In is 8%.
16. The method of claim 11, wherein the wt. % of In is 9%.
17. The method of claim 11, wherein the wt. % of In is 10%.
18 The method of claim 11, wherein the first component comprises a semiconductor die and the second component comprises a flip-chip substrate.
19. The method of claim 11, wherein the first component comprises an integrated circuit package and the second component comprises a circuit board.
20. The method of claim 11, wherein the first component comprises a processor die and the second component comprises an integrated heat sink.
21. A method for joining first and second components having mismatched coefficients of thermal expansion (CTE), comprising:
disposing a lead-free solder between said first and second components,
heating the solder to a reflow temperature; and
cooling the first and second components to re-solidify the solder,
wherein the solder is caused to deform during cooling as a result of the CTE mismatch of the first and second components; and wherein the solder comprises a composition that undergoes a phase transformation when it is cooled from the reflow temperature that reduces residual stress in the solder that would normally appear under the same deformation.
22. The method of claim 21, wherein the first component comprises a semiconductor die and the second component comprises a flip-chip substrate.
23. The method of claim 21, wherein the first component comprises an integrated circuit package and the second component comprises a circuit board.
24. The method of claim 21, wherein the first component comprises a processor die and the second component comprises an integrated heat sink.
25. The method of claim 21, wherein the led-free alloy comprises Tin (Sn) and Indium (In).
26. The method of claim 21, wherein the phase transformation comprises a martensitic phase transformation.
27. The method of claim 26, wherein, wherein the lead-free solder alloy is tin (Sn) based, and wherein the martensitic phase transformation transforms a lattice structure of the alloy from a packed hexagonal γ phase bco (body-centered orthorhombic) to a β-Sn bct (body-centered tetragonal) structure.
28. The method of claim 26, further comprising controlling the rate of cooling to produce a needle-like Martensite microstructure.
US10/404,695 2003-03-31 2003-03-31 Phase change lead-free super plastic solders Abandoned US20040187976A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/404,695 US20040187976A1 (en) 2003-03-31 2003-03-31 Phase change lead-free super plastic solders

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US10/404,695 US20040187976A1 (en) 2003-03-31 2003-03-31 Phase change lead-free super plastic solders
CN2004800087141A CN1767921B (en) 2003-03-31 2004-02-06 Phase change lead-free super plastic solders and welding method therefor
EP04708990A EP1608481A1 (en) 2003-03-31 2004-02-06 Phase change lead-free super plastic solders
KR1020057018602A KR100841138B1 (en) 2003-03-31 2004-02-06 Lead-free solder alloy and soldering method using the alloy
PCT/US2004/003385 WO2004094097A1 (en) 2003-03-31 2004-02-06 Phase change lead-free super plastic solders
TW093103220A TWI273140B (en) 2003-03-31 2004-02-11 Phase change lead-free super plastic solders
US10/933,966 US20050029675A1 (en) 2003-03-31 2004-09-03 Tin/indium lead-free solders for low stress chip attachment
US11/073,277 US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10/933,966 Continuation-In-Part US20050029675A1 (en) 2003-03-31 2004-09-03 Tin/indium lead-free solders for low stress chip attachment
US11/073,277 Division US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

Publications (1)

Publication Number Publication Date
US20040187976A1 true US20040187976A1 (en) 2004-09-30

Family

ID=32990172

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/404,695 Abandoned US20040187976A1 (en) 2003-03-31 2003-03-31 Phase change lead-free super plastic solders
US11/073,277 Expired - Fee Related US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/073,277 Expired - Fee Related US7776651B2 (en) 2003-03-31 2005-03-04 Method for compensating for CTE mismatch using phase change lead-free super plastic solders

Country Status (6)

Country Link
US (2) US20040187976A1 (en)
EP (1) EP1608481A1 (en)
KR (1) KR100841138B1 (en)
CN (1) CN1767921B (en)
TW (1) TWI273140B (en)
WO (1) WO2004094097A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050100474A1 (en) * 2003-11-06 2005-05-12 Benlih Huang Anti-tombstoning lead free alloys for surface mount reflow soldering
US20070036670A1 (en) * 2005-08-12 2007-02-15 John Pereira Solder composition
US20070037004A1 (en) * 2005-08-12 2007-02-15 Antaya Technologies Corporation Multilayer solder article
US20070048172A1 (en) * 2005-08-30 2007-03-01 Indium Corporation Of America Technique for increasing the compliance of tin-indium solders
US20070071634A1 (en) * 2005-09-26 2007-03-29 Indium Corporation Of America Low melting temperature compliant solders
US20070166875A1 (en) * 2005-12-29 2007-07-19 Intel Corporation Method of forming a microelectronic package and microelectronic package formed according to the method
US20070231594A1 (en) * 2005-08-12 2007-10-04 John Pereira Multilayer solder article
US20070292708A1 (en) * 2005-08-12 2007-12-20 John Pereira Solder composition
US20080175748A1 (en) * 2005-08-12 2008-07-24 John Pereira Solder Composition

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050029675A1 (en) * 2003-03-31 2005-02-10 Fay Hua Tin/indium lead-free solders for low stress chip attachment
US20040187976A1 (en) 2003-03-31 2004-09-30 Fay Hua Phase change lead-free super plastic solders
KR100744149B1 (en) * 2006-08-30 2007-08-01 삼성전자주식회사 Semiconductor package having silver bump and method for fabricating the same
JP4899115B2 (en) * 2008-03-05 2012-03-21 千住金属工業株式会社 Lead-free solder connection structure and solder ball
US7977160B2 (en) * 2009-08-10 2011-07-12 GlobalFoundries, Inc. Semiconductor devices having stress relief layers and methods for fabricating the same
KR101097868B1 (en) * 2010-02-18 2011-12-23 주식회사 하이닉스반도체 Method for fabricating semiconductor package
US8673761B2 (en) 2011-02-19 2014-03-18 International Business Machines Corporation Reflow method for lead-free solder
US9373559B2 (en) 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
US10403595B1 (en) 2017-06-07 2019-09-03 United States Of America, As Represented By The Secretary Of The Navy Wiresaw removal of microelectronics from printed circuit board

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242658A (en) * 1992-07-07 1993-09-07 The Indium Corporation Of America Lead-free alloy containing tin, zinc and indium
US5256370A (en) * 1992-05-04 1993-10-26 The Indium Corporation Of America Lead-free alloy containing tin, silver and indium
US5429689A (en) * 1993-09-07 1995-07-04 Ford Motor Company Lead-free solder alloys
US5658528A (en) * 1994-11-02 1997-08-19 Mitsui Mining & Smelting Co., Ltd. Lead-free solder
US5985212A (en) * 1996-12-12 1999-11-16 H-Technologies Group, Incorporated High strength lead-free solder materials
US20030007886A1 (en) * 2001-07-09 2003-01-09 Quantum Chemical Technologies ( Singapore) Pte Ltd. Solders
US6521176B2 (en) * 1994-09-29 2003-02-18 Fujitsu Limited Lead-free solder alloy and a manufacturing process of electric and electronic apparatuses using such a lead-free solder alloy
US6555052B2 (en) * 2000-06-12 2003-04-29 Hitachi, Ltd. Electron device and semiconductor device
US20030143104A1 (en) * 2002-01-21 2003-07-31 Fujitsu Limited Solder alloy and soldered bond

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0435278B2 (en) 1985-05-24 1992-06-10 Mitsubishi Materials Corp
JPH02217193A (en) 1989-02-17 1990-08-29 Matsushita Electric Works Ltd Indium series powdery solder
JPH03201554A (en) 1989-12-28 1991-09-03 Suzuki Motor Corp Electronic part to be packaged on board
TW251249B (en) 1993-04-30 1995-07-11 At & T Corp
JP3201554B2 (en) 1993-08-20 2001-08-20 日本電信電話株式会社 Crossed optical waveguide
JPH09256085A (en) 1996-03-25 1997-09-30 Furukawa Electric Co Ltd:The Pin mounted type package and production of the pin
AU6121598A (en) * 1997-03-10 1998-09-29 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
JPH10314980A (en) * 1997-05-14 1998-12-02 Sony Corp Solder material
JP2000141078A (en) 1998-09-08 2000-05-23 Nippon Sheet Glass Co Ltd Leadless solder
JP3363393B2 (en) 1998-12-21 2003-01-08 千住金属工業株式会社 Lead-free solder alloy
SG98429A1 (en) 1999-10-12 2003-09-19 Singapore Asahi Chemical & Solder Ind Pte Ltd Lead-free solders
JP3074649B1 (en) * 1999-02-23 2000-08-07 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Lead-free solder powder, lead-free solder paste, and methods for producing them
JP2001024021A (en) 1999-07-09 2001-01-26 Hitachi Ltd Semiconductor device and manufacturing method
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
JP2002076606A (en) * 2000-06-12 2002-03-15 Hitachi Ltd Electronic equipment and semiconductor device
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6713318B2 (en) 2001-03-28 2004-03-30 Intel Corporation Flip chip interconnection using no-clean flux
US20030021718A1 (en) * 2001-06-28 2003-01-30 Osamu Munekata Lead-free solder alloy
TW498009B (en) 2001-10-09 2002-08-11 Quantum Chem Tech Singapore Improvements in or relating to solders
US20040129764A1 (en) * 2003-01-07 2004-07-08 Dong Chun Christine Reducing surface tension and oxidation potential of tin-based solders
US20040141873A1 (en) * 2003-01-22 2004-07-22 Tadashi Takemoto Solder composition substantially free of lead
US20040187976A1 (en) 2003-03-31 2004-09-30 Fay Hua Phase change lead-free super plastic solders
US7111771B2 (en) 2003-03-31 2006-09-26 Intel Corporation Solders with surfactant-refined grain sizes, solder bumps made thereof, and methods of making same
US7014093B2 (en) 2003-06-26 2006-03-21 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256370A (en) * 1992-05-04 1993-10-26 The Indium Corporation Of America Lead-free alloy containing tin, silver and indium
US5256370B1 (en) * 1992-05-04 1996-09-03 Indium Corp America Lead-free alloy containing tin silver and indium
US5242658A (en) * 1992-07-07 1993-09-07 The Indium Corporation Of America Lead-free alloy containing tin, zinc and indium
US5429689A (en) * 1993-09-07 1995-07-04 Ford Motor Company Lead-free solder alloys
US6521176B2 (en) * 1994-09-29 2003-02-18 Fujitsu Limited Lead-free solder alloy and a manufacturing process of electric and electronic apparatuses using such a lead-free solder alloy
US5658528A (en) * 1994-11-02 1997-08-19 Mitsui Mining & Smelting Co., Ltd. Lead-free solder
US5985212A (en) * 1996-12-12 1999-11-16 H-Technologies Group, Incorporated High strength lead-free solder materials
US6555052B2 (en) * 2000-06-12 2003-04-29 Hitachi, Ltd. Electron device and semiconductor device
US20030007886A1 (en) * 2001-07-09 2003-01-09 Quantum Chemical Technologies ( Singapore) Pte Ltd. Solders
US20030143104A1 (en) * 2002-01-21 2003-07-31 Fujitsu Limited Solder alloy and soldered bond

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050100474A1 (en) * 2003-11-06 2005-05-12 Benlih Huang Anti-tombstoning lead free alloys for surface mount reflow soldering
US20070036670A1 (en) * 2005-08-12 2007-02-15 John Pereira Solder composition
US20070037004A1 (en) * 2005-08-12 2007-02-15 Antaya Technologies Corporation Multilayer solder article
US20070231594A1 (en) * 2005-08-12 2007-10-04 John Pereira Multilayer solder article
US20070292708A1 (en) * 2005-08-12 2007-12-20 John Pereira Solder composition
US20080175748A1 (en) * 2005-08-12 2008-07-24 John Pereira Solder Composition
US20070048172A1 (en) * 2005-08-30 2007-03-01 Indium Corporation Of America Technique for increasing the compliance of tin-indium solders
US7749336B2 (en) 2005-08-30 2010-07-06 Indium Corporation Of America Technique for increasing the compliance of tin-indium solders
US20070071634A1 (en) * 2005-09-26 2007-03-29 Indium Corporation Of America Low melting temperature compliant solders
US20070166875A1 (en) * 2005-12-29 2007-07-19 Intel Corporation Method of forming a microelectronic package and microelectronic package formed according to the method

Also Published As

Publication number Publication date
KR100841138B1 (en) 2008-06-24
CN1767921A (en) 2006-05-03
CN1767921B (en) 2011-09-14
US20050153523A1 (en) 2005-07-14
WO2004094097A1 (en) 2004-11-04
TW200424322A (en) 2004-11-16
KR20050119175A (en) 2005-12-20
TWI273140B (en) 2007-02-11
US7776651B2 (en) 2010-08-17
EP1608481A1 (en) 2005-12-28

Similar Documents

Publication Publication Date Title
US20160023309A1 (en) Lead-free and antimony-free tin solder reliable at high temperatures
CN1820889B (en) Layered structure of lead free solder composition
TWI226854B (en) Lead-free tin-silver-copper alloy solder composition
US5410184A (en) Microelectronic package comprising tin-copper solder bump interconnections, and method for forming same
EP1223613B1 (en) Electrode structure for semiconductor device, manufacturing method and apparatus for the same
EP1796156B1 (en) Flip chip mounting method
JP3681542B2 (en) Printed circuit boards and relay boards for multistage bumps
EP1163971B1 (en) Electronic device and semiconductor device
JP4913605B2 (en) Method for manufacturing member for semiconductor device
US6689678B2 (en) Process for fabricating ball grid array package for enhanced stress tolerance
US5931371A (en) Standoff controlled interconnection
JP4152596B2 (en) Electronic member having solder alloy, solder ball and solder bump
JP4051893B2 (en) Electronics
US6689488B2 (en) Lead-free solder and solder joint
US8845826B2 (en) Lead-free solder for vehicles and a vehicle-mounted electronic circuit using the solder
US6917113B2 (en) Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly
KR100548114B1 (en) Solder foil and semiconductor device and electronic device
JP5224430B2 (en) Power semiconductor module
Zeng et al. Development of high-temperature solders
DE60126157T2 (en) Compositions; method and devices for lead-free high-temperature solvent
KR101151542B1 (en) Semiconductor device
JP5585746B2 (en) High temperature lead-free solder alloy
US7554201B2 (en) Tin-bismuth (Sn-Bi) family alloy solder and semiconductor device using the same
US5550407A (en) Semiconductor device having an aluminum alloy wiring line
US7012018B2 (en) Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUA, FAY;REEL/FRAME:014471/0832

Effective date: 20030826

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION