CN1767921B - 无铅相变超塑性焊料及使用其进行焊接的方法 - Google Patents

无铅相变超塑性焊料及使用其进行焊接的方法 Download PDF

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CN1767921B
CN1767921B CN2004800087141A CN200480008714A CN1767921B CN 1767921 B CN1767921 B CN 1767921B CN 2004800087141 A CN2004800087141 A CN 2004800087141A CN 200480008714 A CN200480008714 A CN 200480008714A CN 1767921 B CN1767921 B CN 1767921B
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scolder
alloy
parts comprise
phase transformation
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CN1767921A (zh
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F·华
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Abstract

披露了包括重量百分比(wt.％)为85-96％的锡(Sn)和4-15％的铟(In)的无铅焊料及其典型应用。所述Sn-In焊料在从回流温度冷却至室温时进行马氏体相变。结果是，由于连接部件之间的相对运动导致的焊料应变所产生的通常将出现的残余应力显著降低。通常情况下，所述相对运动由所述连接部件之间的热膨胀系数(CTE)的不匹配而产生。所披露的典型应用包括倒装芯片组装和将集成电路封装到电路板安装架上，例如球栅阵列封装。

Description

无铅相变超塑性焊料及使用其进行焊接的方法
技术领域
本发明的技术领域主要涉及焊接工艺，且更具体而言，但不排它地涉及无铅超塑性焊料。
背景技术
焊料是具有特定组成的金属(已公知为合金)，当有焊剂存在时，焊料在相对较低的温度(120-450℃)下熔化。最普遍使用的焊料包含锡和铅作为基本组分。存在许多合金变型，所述合金变型中包括两种或两种以上下列金属元素：锡(Sn)、铅(Pb)、银(Ag)、铋(Bi)、锑(Sb)和铜(Cu)。焊料通过受热时熔化，并结合(浸湿)到金属表面上而起作用。焊料形成了接合金属之间的永久性金属间结合剂，大体上作用类似于金属“胶水”。除了提供结合功能外，焊料接合点还提供了焊接部件之间的电连接和传热路径。焊料可具有多种形式，包括焊膏、焊丝、棒、带、预成型件和锭料。
许多高密度集成电路(ICs)，例如微处理器、图形处理器、微控制器和类似物以使用大量输入/输出(I/O)线路的方式进行封装。为此目的采用的普通封装技术包括“倒装芯片”封装技术和球栅阵列(BGA)封装技术。这两种封装技术对于每条输入/输出(I/O)线路(例如管脚或球)采用了焊料连接点(接合点)。随着复杂集成电路密度的不断增加，倒装芯片和球栅阵列的输入/输出(I/O)连接点密度相应增加。结果是，封装中采用的焊料接合点的尺寸不得不减少。
更具体而言，倒装芯片(FC)不是特定封装(类似于SOIC)，或甚至是封装类型(如球栅阵列)。倒装芯片技术描述了将管芯电连接到封装载体上的方法。封装载体，或基板或引线框架，随后提供了从管芯到封装件外部的连接。在“标准”封装中，利用金属丝实现管芯和载体之间的相互连接。管芯被附接到面朝上的载体上，随后金属丝首先被结合到管芯上，随后形成环并结合到载体上。通常情况下，金属丝长1-5mm，且直径为25-35∞m。相反，通过被直接放置在管芯表面上的导电“凸起”而实现在倒装芯片封装中管芯和载体之间的相互 连接。凸起的管芯随后“倒转”并面朝下放置，且凸起直接连接到载体上。凸起通常高70-100μm且直径为100-125μm。
通常通过两种方式中的一种形成倒装芯片连接，所述方式为：使用焊料或使用导电粘结剂。迄今为止，最普遍的封装互连手段是焊料，所述焊料为在管芯侧的高97Pb-3Sn且通过共晶Pb-Sn被附接到基板上。形成焊料凸起的管芯采用焊料回流工艺被附接到基板上，所述焊料回流工艺与用以将球栅阵列的焊球附接到封装件外部上的工艺非常相似。在进行芯片焊接后，底部填充胶被添加在管芯和基板之间。底部填充胶是特制的工程环氧，所述环氧填充管芯和载体之间围绕焊料凸起的区域。其被设计以控制由硅片和载体之间的热膨胀差异所导致的焊料接合点中的应力，正如下面所进一步详细讨论的。一旦固化，则底部填充胶吸收了大量应力，这样减少了焊料凸起上的应变，大大增加了成品封装件的寿命。芯片附接和底部填充步骤是倒装芯片相互连接的基础。除此之外，围绕管芯的封装构造的其余部分可采取多种形式且通常可利用现有制造工艺和封装规格。
近来，欧盟已要求2003年5月31日后售出的新产品不含基于铅的焊料。其它国家和地区正在考虑相类似的限制措施。这就为集成电路产品的制造商以及在产品制造过程中使用焊接工艺的其它行业提出了问题。尽管许多无铅焊料是众所周知的，但这些焊料具有使它们与基于铅的焊料相比时不利的性质，包括延性(塑性)的降低。这尤其在倒装芯片和球栅阵列组装工艺中是成问题的。
由于努力积极地进行研发，最近已在向无铅焊接技术的完全转变方面取得了显著进步。目前，首要候选焊料是用于多种焊接应用的近三元共晶Sn-Ag-Cu合金。近共晶三元Sn-Ag-Cu合金在固化时产生三相，即β-Sn、Ag3Sn和Cu6Sn5。在固化过程中，平衡共晶转变在动力学上受到抑制。当Ag3Sn相通过最小过冷形核时，β-Sn相典型地需要15至30℃的过冷以形核。与所需过冷的这种不一致所产生的结果是，在焊料接合点最终凝固之前的冷却过程中，大的板状Ag3Sn结构可在液相内快速生长。当大的Ag3Sn板存在于焊料接合点中时，它们可通过提供沿大的Ag3Sn板和β-Sn相之间的界面的优先裂纹扩展路径而不利地影响焊料接合点的机械行为且可能减少焊料接合点的疲劳寿命。对于Sn-Ag-Cu焊料普遍存在的进一步问题包括内层电介质(ILD)开裂 和倒装芯片组件基板处的焊盘剥离，以及在球栅阵列封装件的球栅阵列侧的焊盘剥离。
附图说明
通过参考以下详细说明并当结合附图，本发明得到更好地理解，因此将更易于意识到本发明的前述方面和许多附带优点，其中除非特别进行说明，否则使用相似的附图标记表示各个附图中的相似部件：
图1a-图1c是示出了常规倒装芯片组装工艺的横截面图，其中图1a示出了在焊料回流温度下的状态，图1b示出了组件已冷却后的状态，且图1c示出了底部填充胶被加入且盖被模制成型在组件上之后的状态；
图2是对应于Sn-In合金的相图；
图3是示出了当Sn-In合金从高温冷却至低温时其点阵结构的变化的示意图；
图4是示出了相变的相对百分比对温度和Sn-In重量比率的曲线图；
图5是示出了进行空冷的Sn-7In合金马氏体形成的显微扫描照片；
图6是示出了在压缩应力下形成的Sn-9In合金马氏体相变的结果的显微扫描照片；和
图7是示出了在典型冷却速率下硅(Si)和Sn-7In的位移特征对温度的曲线图。
具体实施方式
在此对无铅焊料组成的细节和焊料的典型用途进行了描述。在以下描述中，阐述了许多具体细节，例如施加用于倒装芯片封装的无铅焊料，从而提供对本发明实施例的彻底理解。然而，相关领域的技术人员将认识到可不通过具体细节中的一个或多个，或通过其它方法、部件、材料等实践本发明。在其它实例中，未详细示出或描述众所周知的结构、材料或操作以避免使本发明的方面不再突出。
整个说明书中对“一个实施例”或“实施例”的参考意味着结合实施例描述的特定部件、结构或特征被包括在本发明的至少一个实施 例中。因此，在整个说明书中各处出现的短语“在一个实施例中”或“在实施例中”不一定都指的是相同的实施例。此外，特定部件、结构或特征可以任何适当方式被结合在一个或多个实施例中。
参见图1a和图1b，典型倒装芯片组件包括具有多个焊盘102的基板100，在所述焊盘上形成了相应的焊料凸起104。基板100进一步包括联接到其下侧上的多个焊球106。相应的引线108在每个焊盘102和焊球106之间沿特定路径延伸。集成电路管芯110通过焊料凸起104被“倒装芯片式”安装到基板100上。为了便于与管芯电路的电连接，管芯包括安装到其下侧上的多个焊盘112，每个所述焊盘经由通过内层电介质(ILD)114的电线(未示出)被连接到管芯电路的相应部分上。内层电介质通常包括在管芯基板上形成的介电层，例如用于硅管芯基板的二氧化硅。
通过升高焊料凸起的温度直至达到焊料的回流温度使得焊料凸起熔化而组装倒装芯片部件。这通常在回流炉等类似装置中进行。随后冷却组装部件，致使焊料回复其固体状态，由此形成焊盘102和112之间的金属结合部。
通常情况下，基板由刚性材料，例如刚性层压结构形成。同时管芯和内层电介质通常由半导体基板，例如硅形成。硅具有百万分之2-4(2-4ppm)/摄氏度的典型热膨胀系数(CTE)。典型倒装芯片基底的热膨胀系数约为16-19ppm/℃。在热膨胀系数上的差异导致在焊料凸起和内层电介质中产生诱发应力，如下面所述。
根据图1a所示，基板和管芯在回流温度下具有相应的相对长度LS1 和LD1当组件冷却时，相对长度减少，如图1b中的长度LS2和LD2所示。相应的长度减少量被描述为ΔLS和ΔLD，其中为清楚起见，ΔLD被大体上示作0。由于管芯的热膨胀系数远小于基板的热膨胀系数，因此ΔLs远大于ΔLD。
作为热膨胀系数失配的结果，导致焊料凸起104伸长，如图1b中的焊料凸起104A所示。例如，考虑当组装部件被冷却至刚好回流温度以下的温度时的焊料凸起构型。在该点处，部件的长度与图1a所示的回流构型的长度大体上相同。焊料处于固体状态，尽管其由于高温而相当易于延展。每个焊料凸起的固化焊料附着到相应的成对焊盘102和112上。随着部件继续冷却，基板100的长度比管芯110的长度减 少了更大的量。结果是，导致焊料凸起伸长(应变)，在焊料材料中诱发应力。此外，一部分应力通过焊盘112被传递至内层电介质114。
在操作中，管芯110产生与其电路中电阻损耗对应的热量。结果是，管芯以及包括基板100的邻近热耦部件的温度增加。当管芯电路在高工作负载状态下操作时，其温度更高，而更低的工作负载操作导致更低的温度，且当然无操作导致还要更低的温度。结果是，管芯电路的操作由于热膨胀系数失配诱发了焊料凸起上的热循环和相应的应力循环。这进一步可导致失效条件，例如焊盘剥离和内层电介质开裂。
通常用以减少与热循环应力相关的失效的一种技术是用环氧底部填充胶116填充邻近焊料凸起104的空间，如图1c所示。随后通常通过将盖118模制成型在各个组件部件顶部上而完成封装工艺。当以这种方式使用底部填充胶时，应力载荷被置于焊料凸起/焊盘界面和底部填充胶组合的横截面上而不只是仅在焊料凸起/焊盘界面上。这在某种程度上减小了在主体焊料和焊料凸起/焊盘界面上的应力，但没有完全消除应力。更重要地，作为从回流温度初始冷却至室温的结果而在焊料凸起内形成的残余应力(所述残余应力同时被传递至焊料凸起/焊盘界面)保持相同，这是由于直到部件已经冷却后才添加底部填充胶。
在现有制造技术条件下，焊料凸起104通常包括基于铅的焊料，例如上面讨论的那些。这些焊料通常在封装部件通常暴露于的整个温度范围内呈现出良好的塑性(非常易于延展)。结果是，由于焊盘剥离和内层电介质开裂所致的失效相当少见。
然而，今后基于铅的焊料的使用对于许多制造产品，例如设计用以出售给欧盟国家的产品来说不再是可行的选择。因此，这些产品的焊料凸起必须包括无铅材料。正如上面讨论地，Sn-Ag-Cu合金已成为取代基于铅的焊料的首要候选焊料。这导致许多应用中出现问题，这是由于与基于铅的焊料相比，Sn-Ag-Cu焊料不具有良好的塑性，从而导致上面讨论的失效模式。
根据本发明的原理，下面披露一种具有超塑性的无铅焊料化合物。在一个实施例中，无铅焊料包括Sn-In合金，其中重量百分比，wt.％为4-15％的铟(85-96wt.％的Sn)。超塑性是由于当Sn-In合金从其回流温度冷却至室温时其中的相变所致。该相变显著降低了与倒装芯片组件以及类似物相关的残余应力问题。
图2是Sn-In合金体系的相图。当In与Sn的比率为4-15％wt.％时，存在高温密排六方γ相向低温β-Sn bct(体心四方)的转变。已证实相变可作为马氏体转变发生(Y.Koyama，H.suzuki和O.Nittono，冶金快报(Scripta Metallurgica)，vol.18，715-717页，1984)。发明人已认识到，该马氏体转变就4-15％wt.％的Sn-In合金用于焊料接合点而言是其有利特征。更具体而言，根据马氏体转变，主体焊料将以补偿接合部件，例如管芯和基板之间的热膨胀系数失配的方式伸长，且在焊料接合点中最小程度地引入应力。此外，还将导致内层电介质中的应力的减小。这些改进的焊料特征导致封装可靠性的增加。
图3示出了在分子水平上阐明相变的示意图。在更高的温度下，Sn-In合金点阵结构对应于密排六方γ相bco(体心斜方)结构300。在该结构中，每个平面的角交替地由Sn原子302(浅色)和In原子304(深色)占据。原子沿一条平面轴线(planel axis)隔开距离“a”，且沿另一条平面轴线隔开距离 a。所述平面隔开距离“c”；因此Sn平面之间的距离为2c。当合金冷却时，产生从γ相体心斜方结构300向β-Sn bct(体心四方)结构306的相变。这是由In原子相对于Sn原子a/4的平移而产生。与此同时，平面之间的距离减小，以使得两个Sn平面之间的距离减少至 a。这导致点阵结构在一个方向上的缩短和在垂直方向上的增长。
图4示出了多种Sn-In合金在正常冷却范围内的相变行为。随温度的降低，更多的γ体心斜方相转变为β-Sn体心四方相。还应注意到，当In的重量百分比减小时，给定温度下的相变百分比增加。结果是，特定Sn-In合金的塑性行为可进行调整以适应其将用于的目标应用。
本发明其它方面涉及当合金冷却时发生的马氏体转变。通常情况下，马氏体和“马氏体的”转变涉及用以改变合金的材料性质的无扩散结晶变化。德国的金相学家A.Martens是第一个确认碳钢中的这种结晶变化的人，且因此以他的名字命名马氏体。
根据主要取决于合金化的元素和/或热处理参数的马氏体转变类型，马氏体转变在新相中形成了板状、针状或叶状结构。马氏体结构改变了合金的材料性质。例如，对热处理钢来说在磨损表面，例如刀和类似物上形成马氏体是普遍的。在这种类型的使用条件下，马氏体结构包括在钢表面处的非常耐磨的硬化材料。尽管增加硬度通常是有 利的，但是延性损失呈下降趋势：马氏体钢通常被分类成脆性材料(与对应的钢合金，例如退火钢的非马氏体相相比)。
尽管马氏体钢具有脆性(即非延性)行为，但是其它马氏体合金呈现出显著不同的行为，包括超塑性。例如，一些记忆金属(即，一种可变形并回复其未变形形状的金属)采用马氏体相。在这种情况下，马氏体可变形能力的冶金原因被认为是所述相的“孪晶”结构：孪晶边界可在没有较大力和没有位错形成的情况下移动，所述较大力和位错形成通常被认为引发了材料断裂。
这种结构的进一步优点在于材料不易于应变硬化，当材料暴露于应变循环中时，所述应变硬化导致延性随时间而降低。这种循环作为前述倒装芯片应用中管芯温度循环的结果而发生。因此，常规焊料随时间变硬，导致疲劳裂纹的形成和最终的接合点失效。
图5和图6示出了由马氏体相变产生的显微结构的细节。图5示出了已进行空冷的Sn-7In(即7wt.％的In)合金的显微扫描照片。注意扫描照片的中心部分中所示出的“针”状结构。图6示出了在压缩应力下形成的Sn-9In马氏体相变的结果。在这种情况下，马氏体结构的取向与材料应变一致。
图7示出了硅(Si)和Sn-7In的位移特性对温度的曲线图。如图所示，Si的相对位移大体上反映出温度曲线，正如通过恒定热膨胀系数值所预期的那样。起初，Sn-7In合金呈现相似的成比例行为，直至温度下落通过约80-70℃的范围。在该时间范围中，发生马氏体转变。在所述转变已发生后，即使温度继续降低，Sn-7In合金的位移保持大体上恒定。
图6和图7所示的行为可直接应用于上面讨论的倒装芯片热膨胀系数失配问题。如上面讨论地，当组件冷却时，管芯和基板材料之间的热膨胀系数失配导致在焊料凸起上诱发应变。这进而导致在主体焊料材料内，且更重要地在焊料凸起/焊盘界面处产生应力。当使用具有在此披露的重量比的Sn-In焊料时，发生在应力下的马氏体相变。因此，当焊料冷却时，主体焊料在应力方向上伸长，大体上消除了由热膨胀系数失配产生的焊料凸起中的残余应力。
上述原理还可应用于其它类型的焊料接合点。例如，类似于倒装芯片热膨胀系数失配的问题导致球栅阵列封装件的接合点失效。在这 种情况下，在封装材料，通常为陶瓷或类似物和其附接到的电路板，通常为多层玻璃纤维之间产生热膨胀系数失配。
除了上面讨论的Sn-In合金组成外，可通过添加少量多种金属改变这些合金以产生目标行为。例如，可添加少量(例如＜2wt.％)的Sb、Cu、Ag、Ni、Ge和Al以进一步改进铸态微观结构并改进热稳定性。这些金属的最佳具体重量百分含量wt.％主要取决于焊料要用于的具体应用。这种因素包括焊料回流温度、塑性要求、预期热循环温度范围等。
在此描述的超塑性焊料合金不仅非常易于延展，而且抗疲劳。在典型疲劳载荷条件下(例如，由于温度循环所致的应变的循环诱发)，常规焊料其结构发生变化。该结构变化随时间使主体材料弱化，最终导致失效。相反，由于相变机理所致的超塑性焊料合金的变形不会导致对主体材料相似水平的损坏。结果是，超塑性焊料合金可成功地用于当使用常规焊料进行实施时将通常导致疲劳失效的应用中。
正如上面讨论地，超塑性焊料非常适于连接材料具有失配的热膨胀系数的应用。前述讨论的将焊料用于管芯以进行倒装芯片基板结合和球栅阵列封装的应用仅是超塑性焊料的典型应用。通常情况下，焊料可用于结合具有失配的热膨胀系数的可焊接材料。这种应用的进一步实例包括将集成散热器(IHS)结合到管芯上。在这种情况下，焊料进一步执行在常规的集成散热器与管芯的联结中所使用的热界面材料的功能。
上面对本发明示例实施例的描述，包括摘要中的描述内容，并不旨在是穷举的或使本发明限于所披露的确切形式。尽管在此对本发明的具体实施例和实例的描述是为了示例目的，但正如相关领域的技术人员将认识到地，多种等效变型可能落入本发明的范围内。
可根据上面的详细描述对本发明做出这些变型。下列权利要求中所使用的术语不应被解释为将本发明限于说明书披露的具体实施例和权利要求中。相反地，要通过下列权利要求整体地确定本发明的范围，所述权利要求要根据权利要求解释的制定原则进行解释。

Claims (18)

1.一种无铅焊料合金，具有当其从回流温度冷却至室温时进行马氏体相变的组成，所述无铅焊料合金仅包括Sn和In。
2.根据权利要求1所述的无铅焊料合金，其中所述合金是Sn基的，且其中所述马氏体相变将所述合金的点阵结构从密排六方γ相体心斜方转变成β-Sn体心四方结构。
3.根据权利要求2所述的无铅焊料合金，其中所述合金具有包括重量百分比至少为85％的Sn和至少4％的In的组成。
4.一种用于连接第一和第二部件的方法，包括以下步骤：
在所述第一和第二部件之间设置无铅焊料，所述焊料仅包括重量百分比为85-96％的Sn和4-15％的In；
将所述焊料加热至回流温度；以及
冷却所述第一和第二部件以使所述焊料重新固化。
5.根据权利要求4所述的方法，其中In的重量百分比为7％。
6.根据权利要求4所述的方法，其中In的重量百分比为8％。
7.根据权利要求4所述的方法，其中In的重量百分比为9％。
8.根据权利要求4所述的方法，其中In的重量百分比为10％。
9.根据权利要求4所述的方法，其中所述第一部件包括半导体管芯，且所述第二部件包括倒装芯片基板。
10.根据权利要求4所述的方法，其中所述第一部件包括集成电路封装件，且所述第二部件包括电路板。
11.根据权利要求4所述的方法，其中所述第一部件包括处理器管芯，且所述第二部件包括集成散热器。
12.一种用于连接具有不匹配的热膨胀系数的第一和第二部件的方法，包括以下步骤：
在所述第一和第二部件之间设置无铅焊料，所述无铅焊料仅包括Sn和In；
将所述焊料加热至回流温度；以及
冷却所述第一和第二部件以使所述焊料重新固化，
其中作为所述第一和第二部件的所述热膨胀系数失配的结果使得所述焊料在冷却过程中发生形变；且其中所述焊料包括当其自所述回流温度冷却时进行相变的组成，所述相变降低了在相同形变量条件下通常将出现的所述焊料中的残余应力。
13.根据权利要求12所述的方法，其中所述第一部件包括半导体管芯，且所述第二部件包括倒装芯片基板。
14.根据权利要求12所述的方法，其中所述第一部件包括集成电路封装件，且所述第二部件包括电路板。
15.根据权利要求12所述的方法，其中所述第一部件包括处理器管芯，且所述第二部件包括集成散热器。
16.根据权利要求12所述的方法，其中所述相变包括马氏体相变。
17.根据权利要求16所述的方法，其中所述无铅焊料合金是Sn基的，且其中所述马氏体相变将所述合金的点阵结构从密排六方γ相体心斜方转变成β-Sn体心四方结构。
18.根据权利要求16所述的方法，进一步包括控制冷却速率以产生针状马氏体微观结构。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040187976A1 (en) 2003-03-31 2004-09-30 Fay Hua Phase change lead-free super plastic solders
US20050029675A1 (en) * 2003-03-31 2005-02-10 Fay Hua Tin/indium lead-free solders for low stress chip attachment
DE10319888A1 (de) 2003-04-25 2004-11-25 Siemens Ag Lotmaterial auf SnAgCu-Basis
US20050100474A1 (en) * 2003-11-06 2005-05-12 Benlih Huang Anti-tombstoning lead free alloys for surface mount reflow soldering
US20070292708A1 (en) * 2005-08-12 2007-12-20 John Pereira Solder composition
US20070037004A1 (en) * 2005-08-12 2007-02-15 Antaya Technologies Corporation Multilayer solder article
US20070231594A1 (en) * 2005-08-12 2007-10-04 John Pereira Multilayer solder article
US20070036670A1 (en) * 2005-08-12 2007-02-15 John Pereira Solder composition
US20080175748A1 (en) * 2005-08-12 2008-07-24 John Pereira Solder Composition
US7749336B2 (en) * 2005-08-30 2010-07-06 Indium Corporation Of America Technique for increasing the compliance of tin-indium solders
US20070071634A1 (en) * 2005-09-26 2007-03-29 Indium Corporation Of America Low melting temperature compliant solders
US20070166875A1 (en) * 2005-12-29 2007-07-19 Intel Corporation Method of forming a microelectronic package and microelectronic package formed according to the method
KR100744149B1 (ko) * 2006-08-30 2007-08-01 삼성전자주식회사 은 범프를 이용한 반도체 패키지 구조 및 형성 방법
JP4899115B2 (ja) * 2008-03-05 2012-03-21 千住金属工業株式会社 鉛フリーはんだ接続構造体およびはんだボール
US7977160B2 (en) * 2009-08-10 2011-07-12 GlobalFoundries, Inc. Semiconductor devices having stress relief layers and methods for fabricating the same
KR101097868B1 (ko) * 2010-02-18 2011-12-23 주식회사 하이닉스반도체 반도체 패키지의 제조방법
US8673761B2 (en) 2011-02-19 2014-03-18 International Business Machines Corporation Reflow method for lead-free solder
US9373559B2 (en) 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
JP6513465B2 (ja) * 2015-04-24 2019-05-15 日本航空電子工業株式会社 リード接合構造
US10403595B1 (en) 2017-06-07 2019-09-03 United States Of America, As Represented By The Secretary Of The Navy Wiresaw removal of microelectronics from printed circuit board
CN109702372A (zh) * 2019-03-06 2019-05-03 上海莜玮汽车零部件有限公司 无铅焊料合金及其应用
JP6799701B1 (ja) * 2020-03-12 2020-12-16 有限会社 ナプラ 金属粒子
KR102245616B1 (ko) * 2020-04-22 2021-04-27 서울시립대학교 산학협력단 무연솔더 합금 조성물
JP7041710B2 (ja) * 2020-04-30 2022-03-24 千住金属工業株式会社 鉛フリーかつアンチモンフリーのはんだ合金、はんだボール、Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙおよびはんだ継手

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400081A (zh) * 2001-06-28 2003-03-05 千住金属工业株式会社 无铅焊料合金

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61269998A (ja) 1985-05-24 1986-11-29 Mitsubishi Metal Corp Ｓｎ合金はんだ箔材の製造法
JPH02217193A (ja) 1989-02-17 1990-08-29 Matsushita Electric Works Ltd インジウム系粉末状ハンダ
JPH03201554A (ja) 1989-12-28 1991-09-03 Suzuki Motor Corp 基板実装用の電子部品
US5256370B1 (en) 1992-05-04 1996-09-03 Indium Corp America Lead-free alloy containing tin silver and indium
US5242658A (en) * 1992-07-07 1993-09-07 The Indium Corporation Of America Lead-free alloy containing tin, zinc and indium
TW251249B (zh) 1993-04-30 1995-07-11 At & T Corp
JP3201554B2 (ja) 1993-08-20 2001-08-20 日本電信電話株式会社 交差光導波路
US5429689A (en) * 1993-09-07 1995-07-04 Ford Motor Company Lead-free solder alloys
US6184475B1 (en) * 1994-09-29 2001-02-06 Fujitsu Limited Lead-free solder composition with Bi, In and Sn
JP2805595B2 (ja) * 1994-11-02 1998-09-30 三井金属鉱業株式会社 鉛無含有半田合金
JPH09256085A (ja) 1996-03-25 1997-09-30 Furukawa Electric Co Ltd:The ピン実装型パッケージ及び前記ピンの製造方法
US5985212A (en) * 1996-12-12 1999-11-16 H-Technologies Group, Incorporated High strength lead-free solder materials
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
JPH10314980A (ja) * 1997-05-14 1998-12-02 Sony Corp はんだ材料
JP2000141078A (ja) 1998-09-08 2000-05-23 Nippon Sheet Glass Co Ltd 無鉛ハンダ
JP3363393B2 (ja) 1998-12-21 2003-01-08 千住金属工業株式会社 鉛フリーはんだ合金
JP3074649B1 (ja) * 1999-02-23 2000-08-07 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 無鉛半田粉末、無鉛半田ペースト、およびそれらの製造方法
JP2001024021A (ja) 1999-07-09 2001-01-26 Hitachi Ltd 半導体装置及びその製造方法
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
SG98429A1 (en) 1999-10-12 2003-09-19 Singapore Asahi Chemical & Solder Ind Pte Ltd Lead-free solders
JP2002076606A (ja) * 2000-06-12 2002-03-15 Hitachi Ltd 電子機器および半導体装置
KR100407448B1 (ko) * 2000-06-12 2003-11-28 가부시키가이샤 히타치세이사쿠쇼 전자 기기 및 반도체 장치
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6713318B2 (en) 2001-03-28 2004-03-30 Intel Corporation Flip chip interconnection using no-clean flux
SG139507A1 (en) * 2001-07-09 2008-02-29 Quantum Chem Tech Singapore Improvements in or relating to solders
TW498009B (en) 2001-10-09 2002-08-11 Quantum Chem Tech Singapore Improvements in or relating to solders
CN1254347C (zh) * 2002-01-21 2006-05-03 富士通株式会社 钎料合金和钎焊接头
US20040129764A1 (en) * 2003-01-07 2004-07-08 Dong Chun Christine Reducing surface tension and oxidation potential of tin-based solders
US20040141873A1 (en) * 2003-01-22 2004-07-22 Tadashi Takemoto Solder composition substantially free of lead
US7111771B2 (en) 2003-03-31 2006-09-26 Intel Corporation Solders with surfactant-refined grain sizes, solder bumps made thereof, and methods of making same
US20040187976A1 (en) 2003-03-31 2004-09-30 Fay Hua Phase change lead-free super plastic solders
US7014093B2 (en) 2003-06-26 2006-03-21 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400081A (zh) * 2001-06-28 2003-03-05 千住金属工业株式会社 无铅焊料合金

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