US20040174483A1 - Liquid crystal display device having auxiliary capacitive electrode - Google Patents

Liquid crystal display device having auxiliary capacitive electrode Download PDF

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Publication number
US20040174483A1
US20040174483A1 US10/794,276 US79427604A US2004174483A1 US 20040174483 A1 US20040174483 A1 US 20040174483A1 US 79427604 A US79427604 A US 79427604A US 2004174483 A1 US2004174483 A1 US 2004174483A1
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Prior art keywords
electrode
display device
thin film
insulating film
auxiliary capacitive
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Abandoned
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US10/794,276
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English (en)
Inventor
Yayoi Nakamura
Hiromitsu Ishii
Shinichi Shimomaki
Hitoshi Watanabe
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority claimed from JP2003061440A external-priority patent/JP4182779B2/ja
Priority claimed from JP2003137232A external-priority patent/JP4102925B2/ja
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Assigned to CASIO COMPUTER CO., LTD. reassignment CASIO COMPUTER CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHII, HIROMITSU, NAKAMURA, YAYOI, SHIMOMAKI, SHINICHI, WATANABE, HITOSHI
Publication of US20040174483A1 publication Critical patent/US20040174483A1/en
Priority to US11/410,752 priority Critical patent/US7545449B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to a liquid crystal display device and particularly to a liquid crystal display device having a structure in which display quality is improved by an auxiliary capacitive electrode.
  • scanning lines and data lines are formed on a glass substrate in a X-direction and a Y-direction, respectively.
  • a thin film transistor connected to both lines is provided as a switching element.
  • An insulating film is formed thereon, and on the insulating film, pixel electrodes are formed to be connected the thin film transistors, which are provided near the intersections, through contact holes provided to the insulating film, respectively.
  • the edge portion of each pixel electrode is overlapped with both lines in order to obtain a high aperture ratio.
  • an object of the present invention is to provide a liquid crystal display device capable of preventing occurrence of vertical crosstalk.
  • a display device of the present invention includes a substrate.
  • the display device of the present invention further includes a plurality of scanning lines formed in parallel with each other on the substrate in one direction and a plurality of data lines formed in parallel with each other on the substrate in orthogonal to the scanning lines.
  • the display device of the present invention further includes a thin film transistor being formed in the vicinity of each intersection of that scanning lines and that data lines and having a semiconductor thin film, a gate electrode connected to one of the scanning lines, a source electrode, a drain electrode connected to one of the scanning lines.
  • the display device of the present invention further includes pixel electrodes each connected to the source electrode of that thin film transistor.
  • the display device of the present invention further includes auxiliary capacitive electrodes each having an overlap region that overlaps with the pixel electrodes and forming an auxiliary capacitance with the pixel electrodes.
  • the display device of the present invention further includes a first insulating film arranged between that auxiliary capacitive electrodes and that data lines.
  • the display device of the present invention further includes a second insulting film arranged between that pixel electrodes and that auxiliary capacitive electrodes.
  • FIG. 1 is a plan view of a main part of a thin film transistor panel in a liquid crystal display device shown as respective layers being seen through according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken on the line II-II of FIG. 1;
  • FIGS. 3A to 3 C are plan views each explaining a thin film transistor portion illustrated in FIG. 1;
  • FIG. 4 is a cross-sectional view of an initial process at the time of manufacturing a thin film transistor panel illustrated in FIGS. 1 and 2;
  • FIG. 5 is a cross-sectional view of a process subsequent to FIG. 4;
  • FIG. 6 is a cross-sectional view of a process subsequent to FIG. 5;
  • FIG. 7 is a cross-sectional view of a process subsequent to FIG. 6;
  • FIG. 8 is a cross-sectional view of a process subsequent to FIG. 7;
  • FIG. 9 is a plan view of a main part of a thin film transistor panel in a liquid crystal display device shown as respective layers being seen through according to a second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view taken on the line X-X of FIG. 9;
  • FIG. 11 is a cross-sectional view taken on the line XI-XI of FIG. 9;
  • FIG. 12 is a cross-sectional view taken on the line XII-XII of FIG. 9;
  • FIGS. 13A to 13 C are plan views each explaining a thin film transistor portion illustrated in FIG. 9;
  • FIG. 14 is a plan view of a main part of a thin film transistor panel in a liquid crystal display device shown as respective layers being seen through according to a third embodiment of the present invention.
  • FIG. 15 is a cross-sectional view taken on the line XV-XV of FIG. 14;
  • FIG. 16 is a cross-sectional view of a thin film transistor panel in a liquid crystal display device according to a fourth embodiment of the present invention, similar to FIG. 15 ;
  • FIG. 17 is a plan view of a thin film transistor panel in an active matrix type liquid crystal display device shown as respective layers being seen through according to a fifth embodiment of the present invention.
  • FIG. 18 is a cross-sectional view taken on the line XVIII-XVIII of FIG. 17;
  • FIG. 19 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a sixth embodiment of the present invention, similar to FIG. 17;
  • FIG. 20 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a seventh embodiment of the present invention, similar to FIG. 18;
  • FIG. 21 is a plan view of a thin film transistor panel shown as respective layers being seen through according to an eighth embodiment of the present invention, similar to FIG. 17;
  • FIG. 22 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a ninth embodiment of the present invention, similar to FIG. 21;
  • FIG. 23 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a tenth embodiment of the present invention, similar to FIG. 22;
  • FIGS. 24A and 24B are views explaining the problem of the conventional liquid crystal display device.
  • FIG. 1 is a plan view of a main part of a thin film transistor panel in a liquid crystal display device shown as respective layers being seen through according to a first embodiment of the present invention.
  • the thin film transistor panel includes a glass substrate 1 .
  • a plurality of scanning lines 2 are formed in parallel with each other in a horizontal direction and a plurality of data lines 3 are formed in parallel with each other in a vertical direction, orthogonal to the scanning lines 2 .
  • a thin film transistor 4 having a double gate structure, a pixel electrode 5 , and an auxiliary capacitive electrode 6 are formed.
  • an edge portion of each pixel electrode 5 is hatched with oblique short solid lines.
  • the right and left edges of the pixel electrode 5 are arranged at the same position as the edges of the data lines 3 arranged at right and left sides of the pixel electrode 5 as seen from the plane, respectively.
  • the right and left edges of the pixel electrode 5 may be arranged to overlap with the data lines 3 . Accordingly, a region, which is obtained by removing forming regions of the data lines 3 provided at the right and left sides of the pixel electrode 5 and a forming region of the thin film transistor 4 from a forming region of the pixel electrode 5 , is used as a substantial pixel region. This makes it possible to obtain a high aperture ratio.
  • a black mask is formed on a portion, which corresponds to at least each of the thin film transistors 4 , of a counter panel (not shown) provided to be opposite to the thin film transistor panel.
  • Each auxiliary capacitive electrode 6 includes a linear electrode portion 6 a placed in parallel with the scanning line 2 , a strip electrode portion 6 b placed in parallel with the left data line 3 of the pixel electrode 5 , and a strip electrode portion 6 c placed in parallel with the right data line 3 of the pixel electrode 5 .
  • the electrode portion 6 a is overlapped with a lower side portion of the pixel electrode 5 .
  • Each of the electrode portions 6 b and 6 c is overlapped with the opposing side portions of the pixel electrodes 5 , which are adjacent to each right and left, and the data line 3 formed therebetween.
  • each of the electrode portions 6 b and 6 c is placed between the pixel electrodes 5 and the data line 3 in a thickness direction of the thin film transistor panel, namely, a vertical direction on paper of FIG. 1.
  • the width of each of the electrodes 6 b and 6 c (a length in a direction parallel to the scanning line 2 ) is set to be wider than the width of the data line 3 to some degree. Accordingly, the data line 3 is entirely covered with the electrode portion 6 b or 6 c , not to oppose to the pixel electrodes 5 directly, even if there is a positional shift in a direction parallel to the scanning line 2 in an alignment step.
  • FIG. 2 is a cross-sectional view taken on the line II-II of FIG. 1.
  • first and second underlying insulating films 11 and 12 are formed on the upper surface of the glass substrate 1 .
  • a polysilicone thin film 13 is formed on a predetermined portion of an upper surface of the second underlying insulating film 12 .
  • the polysilicone thin film 13 including multiple gate (channel) regions is substantially linearly formed.
  • an n-type impurity low concentration region 13 a having a low concentration of n-type impurities is formed.
  • channel regions 13 b each having an intrinsic region are formed at both sides of the n-type impurity low concentration region 13 a .
  • n-type impurity low concentration regions 13 c are formed at both sides of the channel regions 13 b that sandwich the n-type impurity low concentration region 13 a .
  • n-type impurity high concentration regions 13 d each having a high concentration of n-type impurities are formed at both sides of channel regions 13 c that sandwich the n-type impurity low concentration region 13 a and the channel regions 13 b.
  • a gate insulating film 14 is formed on the upper surfaces of the second underlying insulating film 12 and the polysilicone thin film 13 .
  • Two gate electrodes 15 are formed on predetermined portions of the upper surface of the gate insulting film 14 , so as to cover two channel regions 13 b of the polysilicone thin film 13 as illustrated in FIG. 3B.
  • two gate electrodes 15 have a common connecting portion 15 a that connects both electrodes 15 to each other to form a substantially U-shape island.
  • the island means an area that is physically and electrically separated from the other elements, and is used based on the same definition in the explanation hereinafter.
  • the data line 3 is formed as illustrated in FIG. 3B.
  • a connecting portion 3 a with a large width is formed on a predetermined portion of the data line 3 .
  • an interlayer insulating film 16 is formed on the upper surfaces of the gate insulating film 14 , the gate electrodes 15 and the data line 3 .
  • an interlayer insulating film 16 is formed on the upper surfaces of the gate insulating film 14 , the gate electrodes 15 and the data line 3 .
  • a source electrode 17 and a drain electrode 18 are formed in an island shape.
  • the source electrode 17 is connected to one n-type impurity high concentration region 13 d of the polysilicone thin film 13 through a contact hole 19 provided to the interlayer insulating film 16 and the gate insulating film 14 .
  • One end of the drain electrode 18 is connected to the other n-type impurity high concentration region 13 d of the polysilicone thin film 13 through a contact hole 20 provided to the interlayer insulating film 16 and the gate insulating film 14 .
  • the other end of the drain electrode 18 is connected to the connecting portion 3 a of the data line 3 through a contact hole 21 provided to the interlayer insulating film 16 .
  • the scanning line 2 is formed on a predetermined portion of the upper surface of the interlayer insulating film 16 .
  • a connecting portion 2 a formed on a predetermined portion of the scanning line 2 is connected to the common connecting portion 15 a of the gate electrodes 15 through a contact hole 22 provided to the interlayer insulating film 16 .
  • the auxiliary capacitive electrode 6 is formed on a predetermined portion of the upper surface of the interlayer insulating film 16 . In this case, electrode portions 6 b and 6 c of the auxiliary capacitive electrode 6 are formed on the interlayer insulating film 16 , so as to cover the data lines 3 .
  • an overcoat film 23 is formed on the upper surfaces of the interlayer insulating film 16 , the source electrode 17 and the like.
  • an overcoat film 23 is formed on a predetermined portion of the upper surface of the overcoat film 23 .
  • the pixel electrode 5 is connected to the source electrode 17 through a contact hole 24 provided to the overcoat film 23 .
  • Two divided gate electrodes 15 formed on the gate insulating film 14 cover the polysilicone thin film 13 to oppose to two channel regions 13 b of the polysilicone thin film 13 , respectively.
  • the thin film transistor 4 having the double gate structure is structured by the polysilicone thin film 13 , the gate insulating film 14 , the gate electrodes 15 , the source electrode 17 , and the drain electrode 18 .
  • the first underlying insulating film 11 of silicon nitride, the second underlying insulating film 12 of silicon oxide, and an amorphous silicon thin film 31 are continuously formed by a plasma CVD (Chemical Vapor Deposition) method.
  • the amorphous silicon thin film 31 is crystallized by irradiation of excimer lasers to form a polysilicone thin film 32 .
  • resist pattern 33 having openings 33 a formed on portions corresponding to the forming regions of the n-type impurity high concentration region 13 d as illustrated in FIG. 2.
  • the resist pattern 33 is used as a mask and n-type impurities are injected threreonto with a high concentration. Thereafter, the resist pattern 33 is peeled from the polysilicone thin film 32 .
  • the polysilicone thin film 32 is patterned to form the polysilicone thin film 13 on a predetermined portion of the upper surface of the second underlying insulating film 12 as illustrated in FIG. 6.
  • the gate insulating film 14 of silicon oxide is formed by a plasma CVD method.
  • a metallic film of Al and the like is formed by a sputtering method.
  • the gate electrodes 15 having the common connecting portion 15 a and the data line 3 having the connecting portion 3 a are formed.
  • n-type impurity low concentration region 13 a is formed on a region of the polysilicone thin film 13 , which corresponds to a portion between two gate electrodes 15 .
  • channel regions 13 b each having an intrinsic region are formed on regions directly below two gate electrodes 15 .
  • n-type impurity low concentration regions 13 c are formed at both sides of the channel regions 13 b
  • n-type impurity high concentration regions 13 d are formed at both sides of the n-type impurity low concentration regions 13 c .
  • anneal processing is performed at temperature of about 500° C. for about one hour. As a result, the injected impurities are activated.
  • the interlayer insulating film 16 of silicon nitride is formed by a plasma CVD method.
  • openings 19 and 20 are formed to the interlayer insulating film 16 and the gate insulating film 14 , so as to reach the high n-type impurity concentration regions 13 d of the polysilicone thin film 13 .
  • an opening 21 is formed to the interlayer insulating film 16 , so as to reach the connecting portion 3 a of the data line 3 .
  • an opening 22 is formed to the interlayer insulating film 16 , so as to reach the common connection portion 15 a of two gate electrodes 15 .
  • an Al film and a Cr film (or Mo film) for ITO contact are successively formed in the openings 19 , 20 , 21 and 22 and on the upper surface of the interlayer insulating film 16 by a sputtering method. As a result, a metal film 34 is formed.
  • the source electrode 17 is connected to one n-type impurity high concentration region 13 d of the polysilicone thin film 13 through the contact hole 19 .
  • one end of the drain electrode 18 is connected to the other n-type impurity high concentration region 13 d of the polysilicone thin film 13 through the contact hole 20 .
  • the other end of the drain electrode 18 is connected to the connecting portion 3 a of the data line 3 through the contact hole 21 .
  • the connecting portion 2 a of the scanning line 2 is connected to the common connecting portion 15 a of two gate electrodes 15 through the contact hole 22 .
  • the overcoat film 23 of silicon nitride is formed by a plasma CVD method.
  • a contact hole 24 is formed on a predetermined portion of the overcoat film 23 , so as to reach the source electrode 17 .
  • an ITO film is formed on the upper surface of the overcoat film 23 by a sputtering method.
  • the formed ITO film is patterned to form the pixel electrode 5 connected to the source electrode 17 through the contact hole 24 .
  • the thin film transistor panel as illustrated in FIGS. 1 and 2 can be obtained.
  • the electrode portions 6 b and 6 c of the auxiliary capacitive electrode 6 each having a larger width than that of the data line 3 are formed between the edge portions of the pixel electrodes 5 and the data lines 3 .
  • the electrode portions 6 b and 6 c can prevent the coupling capacitance from occurring between the edge portions of the pixel electrodes 5 and the data lines 3 . Accordingly, it is possible to prevent occurrence of vertical crosstalk and achieve a high display characteristic.
  • the aforementioned manufacturing method includes first to fifth processes.
  • the first process forms the data line 3 and the island gate electrodes 15 on the gate insulating film 14 .
  • the second process forms the contact holes 19 and 20 through the interlayer insulating film 16 and the gate insulating film 14 .
  • the third process forms the scanning line 2 , the auxiliary capacitive electrode 6 , the island source electrode 17 and the island drain electrode 18 on the interlayer insulating film 16 .
  • the fourth process forms the contact hole 24 to the overcoat film 23 .
  • the fifth process forms the pixel electrode 5 on the overcoat film 23 . While, for example, a manufacturing method for the display device illustrated in FIGS. 1 and 4 of the above-described Unexamined Japanese Patent Application KOKAI Publication No.
  • H1-156725 includes first to fifth processes.
  • the first process forms a scanning line and a gate electrode on a gate insulating film.
  • the second process forms a contact hole passing through an interlayer insulating film and the gate insulating film, so as to reach one source and drain regions.
  • the third process forms a data line on the interlayer insulating film.
  • the fourth process forms a contact hole passing through an overcoat film, the interlayer insulating film and the gate insulating film, so as to reach the other source and drain regions.
  • the fifth process forms a pixel electrode on the overcoat film. Accordingly, even if the gate electrode 15 , the source electrode 17 and the drain electrode 18 are formed in an island shape in the above-mentioned manufacturing method, the number of manufacturing processes does not increase.
  • FIG. 9 is a plan view of a main part of a thin film transistor panel in a liquid crystal display device shown as respective layers being seen through according to a second embodiment of the present invention.
  • the edge portion of each pixel electrode 5 is also hatched with oblique short solid lines for the purpose of clarifying FIG. 9.
  • the point which is largely different from the case shown in FIGS. 1 and 2, relates to a thin film transistor structure having a double gate structure.
  • a polysilicone thin film is flat and U-shaped and a gate electrode is linearly formed to bridge the opposing portions of the U-shaped polysilicone thin film.
  • the gate electrode and a scanning line are connected to each other through a contact hole formed to an interlayer insulating film.
  • the width of the scanning line can be set to the same or less than the width of the gate electrode. This makes it possible to improve the aperture ratio as compared with the double gate structure where the divided portions of the U-shaped gate electrode projects from the scanning line.
  • FIG. 10 is a cross-sectional view taken on the line X-X of FIG. 9
  • FIG. 11 is a cross-sectional view taken on the line XI-XI of FIG. 9
  • FIG. 12 is a cross sectional view taken on the line XII-XII of FIG. 9.
  • the first and second underlying insulating films 11 and 12 are formed on the upper surface of the glass substrate 1 .
  • the polysilicone thin film 13 is formed on a predetermined portion of the upper surface of the second underlying insulating film 12 . As illustrated in FIG.
  • the polysilicone thin film 13 is substantially U-shaped and symmetrical with a vertical center line, and includes multiple gate (channel) regions. At a substantially central portion of each of a pair of side bars, the channel region 13 b having an intrinsic region is formed. Moreover, the n-type impurity low concentration regions 13 c are formed at both sides of the channel region 13 b . Furthermore, the n-type impurity high concentration regions 13 d are formed at both sides of the n-type impurity low concentration regions 13 c.
  • the gate insulating film 14 is formed on the upper surfaces of the second underlying insulating film 12 and the polysilicone thin film 13 .
  • One linear gate electrode 15 is formed in an island shape on a predetermined portion of the upper surface of the gate insulting film 14 , so as to cover two channel regions 13 b of the polysilicone thin film 13 as illustrated in FIG. 13B.
  • connecting portions 15 b are provided at both ends of the gate electrode 15 .
  • the data line 3 is formed as illustrated in FIG. 13B.
  • the connecting portion 3 a with a large width is formed on a predetermined portion of the data line 3 .
  • the interlayer insulating film 16 is formed on the upper surfaces of the gate insulating film 14 , the gate electrode 15 and the data line 3 .
  • the source electrode 17 and the drain electrode 18 are formed on predetermined portions of the upper surface of the interlayer insulating film 16 in an island shape, respectively.
  • the source electrode 17 is connected to one n-type impurity high concentration region 13 d of the polysilicone thin film 13 through the contact hole 19 provided to the interlayer insulating film 16 and the gate insulating film 14 .
  • One end of the drain electrode 18 is connected to the other n-type impurity high concentration region 13 d of the polysilicone thin film 13 through the contact hole 20 provided to the interlayer insulating film 16 and the gate insulating film 14 .
  • the other end of the drain electrode 18 is connected to the connecting portion 3 a of the data line 3 through the contact hole 21 provided to the interlayer insulating film 16 .
  • the scanning line 2 is formed as illustrated in FIG. 13C.
  • the scanning line 2 has a narrow width portion 2 b provided above a portion of the gate electrode 15 , which is sandwiched by the connecting portions 15 b .
  • the narrow width portion 2 b is set to be narrower than the sandwiched portion.
  • Both side portions of the narrow width portion 2 b of the scanning line 2 are connected to the connecting portions 15 b of the gate electrode 15 through the contact holes 22 provided to the interlayer insulating film 16 . Accordingly, the narrow width portion 2 b of the scanning line 2 may be omitted.
  • substantially the same auxiliary capacitive electrode 6 as the first embodiment is formed on a predetermined portion of the upper surface of the interlayer insulating film 16 .
  • the overcoat film 23 is formed on the upper surfaces of the interlayer insulating film 16 , the source electrode 17 and the like.
  • the pixel electrode 5 is formed on a predetermined portion of the upper surface of the overcoat film 23 .
  • the pixel electrode 5 is connected to the source electrode 17 through the contact hole 24 provided to the overcoat film 23 .
  • the thin film transistor 4 having the double gate structure is structured by the polysilicone thin film 13 having two channel regions 13 b , the gate insulating film 14 , the gate electrode 15 , the source electrode 17 , and the drain electrode 18 .
  • the thin film transistor panel manufacturing method of the second embodiment is substantially the same as the first embodiment, and the explanation is omitted.
  • the linear and island-shaped gate electrode 15 formed on the gate insulating film 14 and the scanning line 2 formed on the interlayer insulating film 16 are overlapped with each other as seen from the plane. This makes it possible to reduce the plane arranging space of the gate electrode 15 in the direction perpendicular to the scanning line 2 . As a result, a much higher aperture ratio can be achieved.
  • the following method can be used. Namely, in the process of forming the gate electrode 15 on the gate insulating film 14 , an auxiliary capacitive electrode of the lower layer is formed on a region overlapping with the polysilicone thin film 13 and the pixel electrode 5 , simultaneously, and the auxiliary capacitive electrode of the lower layer is connected to the auxiliary capacitive electrode 6 of the first and second embodiments.
  • the third embodiment shows a thin film transistor panel in the above-manufactured liquid crystal display device.
  • FIG. 14 is a plan view of a main part of the thin film transistor panel in the liquid crystal display device shown as respective layers being seen through according to the third embodiment of the present invention
  • FIG. 15 is a cross-sectional view taken on the line XV-XV of FIG. 14.
  • this thin film transistor panel on the interlayer insulating film 16 , there is formed an electrode portion 6 d drawn from the electrode portion 6 a of the auxiliary capacitive electrode 6 in a direction opposite to the drawing directions of electrode portions 6 b and 6 c , and corresponding to the lower side portion of the pixel electrode 5 .
  • an island electrode portion 6 e is formed on a region of the gate insulating film 14 , which corresponds to the forming regions of the electrode portion 6 d and the source electrode 17 .
  • the electrode portion 6 d is connected to the electrode portion 6 e through a contact hole provided to a predetermined portion of the interlayer insulating film 16 .
  • the above-described structure is different from the structure shown in FIGS. 1 and 2.
  • auxiliary capacitances there are further formed an auxiliary capacitance Cs 1 between the electrode portion 6 d and the upper pixel electrode 5 , an auxiliary capacitance Cs 2 between the electrode portion 6 e and the upper pixel electrode 5 , an auxiliary capacitance Cs 3 between the electrode portion 6 d and the upper source electrode 17 , and an auxiliary capacitance Cs 4 between the electrode portion 6 e and the lower n-type impurity high concentration region 13 d . Accordingly, more auxiliary capacitances can be ensured.
  • FIG. 16 is a cross-sectional view of a thin film transistor panel in a liquid crystal display device according to a fourth embodiment of the present invention, similar to FIG. 15.
  • a relative thicker flatting film 26 formed of polyimide resin, epoxy resin or the like is used in place of the overcoat film 23 formed of silicon nitride.
  • the flatting film 26 is relatively thicker, a normal auxiliary capacitance Cs 0 between the auxiliary capacitive electrode 6 and the pixel electrode 5 shown in FIG. 1 becomes small.
  • the auxiliary capacitances Cs 1 , Cs 2 , Cs 3 , and Cs 4 are formed in addition to this as mentioned above, necessary auxiliary capacitance can be fully ensured.
  • First to fourth embodiments showed the top gate type thin film transistor.
  • the present invention can be applied to a bottom gate type thin film transistor.
  • the auxiliary capacitive electrode is formed on only the portion overlapping with the data line, a much higher aperture ratio can be achieved.
  • Fifth embodiment shows a thin film transistor panel in such an active matrix type liquid crystal display device.
  • FIG. 17 is a plan view of the thin film transistor panel shown as respective layers being seen through.
  • This thin film transistor panel includes a glass substrate 101 . On the upper surface side of the glass substrate 101 , scanning lines 102 and data lines 103 are formed in such a manner as the manner set forth in the first embodiment.
  • a thin film transistor 104 and a pixel electrode 105 are formed.
  • auxiliary capacitive electrodes 106 are formed to be parallel with the data lines 103 , respectively.
  • Each auxiliary capacitive electrode 106 is overlapped with the data line 103 . Moreover, though this is explained later, each of the auxiliary capacitive electrodes 106 is formed between the data line 103 and the pixel electrodes 105 in a thickness direction of the thin film transistor panel, namely, a vertical direction on paper of FIG. 17. Then, the width of each auxiliary capacitive electrode 106 (a length in a direction parallel to the scanning line 102 ) is set to be wider than the width of the data line 103 . Accordingly, the data line 3 is entirely covered with the auxiliary capacitive electrode 106 not to oppose to the pixel electrodes 105 directly even if there is a positional shift in a direction parallel to the scanning line 102 .
  • each auxiliary capacitive electrode 106 is formed over almost the entire area of the arranging region of the data line 103 . Thereby, even if the position of the auxiliary capacitive electrode 106 is shifted to the pixel electrode 105 in a direction perpendicular to the scanning line 102 in an alignment step, the auxiliary capacitive electrode 106 is overlapped with the pixel electrode 105 without fail. Accordingly, variations in the auxiliary capacitance caused by the positional shift are surely prevented.
  • FIG. 18 is a cross-sectional view taken on the line XVIII-XVIII of FIG. 17.
  • the scanning line 102 (FIG. 17) including a gate electrode 102 a formed of chromium and molybdenum is formed.
  • a gate insulating film 51 of silicon nitride is formed on the upper surfaces of the glass substrate 101 .
  • a semiconductor thin film 113 made of intrinsic amorphous silicon is formed so as to cover the gate electrode 102 a .
  • a channel protective film 52 made of silicon nitride is formed so as to overlap with the gate electrode 102 a.
  • Ohmic contact layers 53 and 54 of n-type amorphous silicon.
  • source electrode 57 and a drain electrode 58 of chromium and molybdenum, respectively.
  • the thin film transistor 104 is formed by the gate electrode 102 a , the gate insulating film 51 , the semiconductor thin film 113 , the channel protective film 52 , the Ohmic contact layers 53 and 54 , the source electrode 57 and the drain electrode 58 .
  • the data line 103 On the upper surface of the gate insulating film 51 , the data line 103 is formed.
  • the data line 103 has a structure including three layers of intrinsic amorphous silicon 103 a, n -type amorphous silicon 103 b and a metallic layer 103 c formed of chromium and molybdenum. Then, the intrinsic amorphous silicon 103 a , the n-type amorphous silicon 103 b and the metallic layer 103 c are connected to the semiconductor thin film 113 , the Ohmic contact layer 54 and the drain electrode 58 , respectively.
  • an interlayer insulating film 59 of silicon nitride On the upper surface of the interlayer insulating film 59 , the auxiliary capacitive electrode 106 of chromium and molybdenum is formed so as to cover the data line 103 .
  • an overcoat film 123 of silicon nitride is formed on the upper surfaces of the interlayer insulating film 59 and the auxiliary capacitive electrode 106 .
  • a contact hole 61 is formed to the interlayer insulating film 59 and the overcoat film 123 , so as to reach the source electrode 57 .
  • the pixel electrode 105 of transparent conductive material such as ITO or ZnO is formed so as to be connected to the source electrode 57 through the contact hole 61 .
  • the auxiliary capacitive electrode 106 having a width larger than the data line 103 are formed between the data line 103 and the pixel electrodes 105 .
  • the auxiliary capacitive electrode 106 can prevent occurrence of coupling capacitance between the data line 103 and the pixel electrodes 105 . Accordingly, this makes it possible to prevent occurrence of vertical crosstalk and achieve a high display characteristic.
  • the vicinity of each intersection of the scanning lines 102 and data lines 103 can be shielded by the auxiliary capacitive electrode 106 .
  • FIG. 19 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a sixth embodiment of the present invention, similar to FIG. 17.
  • the point different form the case shown in FIG. 17 is that the upper side portion of the pixel electrode 105 is extended and overlapped with the scanning line 102 .
  • the width of the scanning line 102 is set to be larger than the case shown in FIG. 17 to some degree.
  • the upper side portion of the pixel electrode 105 is extended and overlapped with the scanning line 102 .
  • the electric field between the upper side portion of the pixel electrode 105 and the scanning line 102 more increases.
  • the liquid crystal disposed between the upper side portion of the pixel electrode 105 and the counter panel is strongly restricted by off-potential of the scanning line 102 overlapping with the upper side portion of the pixel electrode 105 , so that disclination lessens as compared with the case shown in FIG. 17. This makes it possible to reduce the black mask, which is formed on the counter panel to hide disclination, to some degree and increase the aperture ratio.
  • FIG. 20 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a seventh embodiment of the present invention, similar to FIG. 19.
  • the auxiliary capacitive electrode 106 placed at the left side of the pixel electrode 105 has a first extending portion 106 a extending in parallel with the scanning line 102 .
  • the first extending portion 106 a extends right from a portion in the vicinity of the thin film transistor 104 .
  • the first extending portion 106 a is overlapped with the left portion of the lower side portion of the pixel electrode 105 .
  • the auxiliary capacitive electrode 106 placed at the right side of the pixel electrode 105 has a second extending portion 106 b extending in parallel with the scanning line 102 .
  • the second extending portion 106 b extends left from a portion in the vicinity of the scanning line 102 .
  • the second extending portion 106 b is overlapped with the right portion of the lower side portion of the pixel electrode 105 , the scanning line 102 , and the right portion of the upper side portion of the adjacent pixel electrode 105 A.
  • the above-explained structure is different from the structure shown in FIG. 19.
  • a connecting portion (namely, a contact hole 61 in FIG. 18) between the source electrode 57 of the thin film transistor 104 and the pixel electrode 105 is formed at a position that avoids the second extending portion 106 b.
  • the first extending portion 106 a extended from the left auxiliary capacitive electrode 106 is placed between the gate electrode 102 a of the thin film transistor 104 and the left portion of the lower side portion of the pixel electrode 105 .
  • the second extending portion 106 b extended from the right auxiliary capacitive electrode 106 is placed between the right portion of the lower side portion of the pixel electrode 105 and the scanning line 102 .
  • a gap between the right portion of the lower side portion of the pixel electrode 105 and the scanning line 102 is covered with the second extending portion 106 b to make it possible to eliminate a light leak from the gap. Accordingly, there is no need to shield the gap by a black mask provided on the counter panel and the aperture ratio can be largely increased as compared with the case of shielding by the black mask.
  • FIG. 21 is a plan view of a thin film transistor panel shown as respective layers being seen through according to an eighth embodiment of the present invention, similar to FIG. 1.
  • the auxiliary capacitive electrodes 106 at right and left sides of the pixel electrode 105 are formed together with connecting portions 106 c which are formed in the vicinity of the scanning lines 102 , so as to be entirely connected with each other via the connecting portions 106 c .
  • Each connecting portion 106 c is overlapped with the lower side portion of the pixel electrode 105 and the upper side portion of the adjacent pixel electrode 105 A.
  • the above-explained structure is different from the structure shown in FIG. 17.
  • a connecting portion (namely, the contact hole 61 in FIG. 18) between the source electrode 57 of the thin film transistor 104 and the pixel electrode 105 is formed at a position that avoids the connecting portion 106 c.
  • each connecting portion 106 c is overlapped with the lower side portion of the pixel electrode 105 and the upper side portion of the adjacent pixel electrode 105 A. This makes it possible to cover all regions except the central portion (transparent pixel) of the pixel electrode 10 S with the auxiliary capacitive electrodes 106 including the connecting portions 106 c . Accordingly, there is no need to provide a black mask for preventing a light leak on the counter panel and a considerably high aperture ratio can be achieved.
  • the thin film transistor 104 having the semiconductor thin film 113 (FIG. 18) formed of intrinsic amorphous silicon the light leak easily occurs.
  • each thin film transistor 104 (except a part of the source electrode 57 ) can be completely covered with the connecting portion 106 c , considerably high light leak control can be obtained.
  • the auxiliary capacitive electrodes 106 provided at right and left sides of the pixel electrode 105 are connected to each other by the connecting portions 106 c , the auxiliary capacitive electrodes 106 including the connecting portions 106 c are arrayed in a lattice. Accordingly, even if a break occurs anywhere in the auxiliary capacitive electrodes 106 including the connecting portions 106 c , a current path can be ensured and a degree of risk that failure will occur by the break can be considerably reduced.
  • the resistance value of the auxiliary capacitive electrodes 106 is small as compared with the case in which the auxiliary capacitive electrodes 106 are shaped stripe as illustrated in, for example, FIG. 17. This reduces a time constant, so that the liquid crystal responds quickly.
  • the auxiliary capacitive electrodes 106 are connected to counter electrodes formed on the opposing panel and driven in synchronization with the counter electrodes.
  • the counter electrodes are driven in synchronization with 1H signal or 1V signal. For this reason, the resistance value is reduced to lessen the time constant, so that the liquid crystal responds quickly.
  • FIG. 22 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a ninth embodiment of the present invention, similar to FIG. 21.
  • the point different from the case shown in FIG. 21 is that the connecting portions 106 c of the auxiliary capacitive electrodes 106 are formed to be overlapped with the scanning lines 102 and not to be overlapped with the pixel electrodes 105 .
  • a part of the pixel electrode 105 directly opposes to the scanning line 102 via the insulating films.
  • each of the connecting portions 106 c of the auxiliary capacitive electrodes 106 is shaped to be overlapped with the upper portion of each scanning line 102 .
  • the scanning line 102 opposes to the pixel electrode 105 via the gate insulating film 51 , the interlayer insulating film 59 and the overcoat film 123 (FIG. 18). Namely, in each region where the dots are written, the connecting portion 106 c of the auxiliary capacitive electrodes 106 is not provided between the scanning line 102 and the pixel electrode 105 .
  • the scanning line 102 is overlapped with only the part of the pixel electrode 105 via only the insulating films instead of the connecting portion 106 c of the auxiliary capacitive electrode 106 , the electric field between the pixel electrode 105 and the scanning line 102 more increases.
  • the liquid crystal disposed between the part of the pixel electrode 105 and the counter panel is strongly restricted by off-potential of the scanning line 102 overlapping with the upper side portion of the pixel electrode 105 , so that disclination lessens. This makes it possible to reduce the black mask, which is formed on the counter panel to hide disclination, to some degree and increase the aperture ratio.
  • FIG. 23 is a plan view of a thin film transistor panel shown as respective layers being seen through according to a tenth embodiment of the present invention, similar to FIG. 22.
  • a transparent auxiliary capacitive electrode 106 A which is formed of transparent conductive material such as ITO or ZnO, is provided as a lower conductive layer directly below each auxiliary capacitive electrode 106 which is formed on the interlayer insulating film 59 (FIG. 18) and includes the connecting portion 106 c
  • the transparent auxiliary capacitive electrode 106 A is formed up to a slightly inner position than the auxiliary capacitive electrodes 106 including the coupling portions 106 c . Moreover, the transparent auxiliary capacitive electrode 106 A is not formed on the connecting portion between the source electrode 57 of the thin film transistor 104 and the pixel electrode 105 (namely, contact hole 61 in FIG. 18) and the region corresponding to the vicinity thereof.
  • the auxiliary capacitive electrode 106 including the connecting portions 106 c is formed of shielding metal of chromium and molybdenum and the like that are electrically contactable with the transparent auxiliary capacitive electrode 106 A of transparent conductive material such as ITO or ZnO.
  • the transparent auxiliary capacitive electrode 106 A is formed up to the slightly inner position than the auxiliary capacitive electrode 106 including the coupling portions 106 c .
  • the auxiliary capacitive portion is also formed by an overlapping portion of a part of the transparent auxiliary capacitive electrode 106 A which is placed in the inner position than the auxiliary capacitive electrode 106 and the pixel electrode 105 .
  • the transparent auxiliary capacitive electrode 106 A is formed of the transparent conductive material such as ITO or ZnO, no influence is exerted upon the aperture ratio.
  • the size and shape of the transparent auxiliary capacitive electrode 106 A are appropriately selected to make it possible to adjust the auxiliary capacitance without exerting an influence upon the aperture ratio.
  • the transparent auxiliary capacitive electrode 106 A may be formed on the upper surface of the interlayer insulating film 59 including the auxiliary capacitive electrode 106 . Moreover, the transparent auxiliary capacitive electrode 106 A may be formed on the upper surface of an upper interlayer insulating film (not shown) formed on the upper surfaces of the interlayer insulating film 59 and the auxiliary capacitive electrode 106 , so that the transparent auxiliary capacitive electrode 106 A is connected to the auxiliary capacitive electrode 106 through a contact hole formed to the upper interlayer insulating film.
  • the transparent auxiliary capacitive electrode 106 A may be formed under the upper interlayer insulating film and the auxiliary capacitive electrode 106 may be formed on the upper interlayer insulting film, so that the transparent auxiliary capacitive electrode 106 A is connected to the auxiliary capacitive electrode 106 through the contact hole formed to the upper interlayer insulating film.
  • the part of the auxiliary capacitive electrode is formed between the pixel electrodes and the data line via the insulating films. This makes it possible to prevent occurrence of the coupling capacitance between the pixel electrodes and the data line. Accordingly, it is possible to prevent occurrence of the vertical crosstalk.

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TW200424974A (en) 2004-11-16
CN1527117A (zh) 2004-09-08
TWI238370B (en) 2005-08-21
US7545449B2 (en) 2009-06-09
US20060187397A1 (en) 2006-08-24
CN100351690C (zh) 2007-11-28
KR100679975B1 (ko) 2007-02-08

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