US20040056300A1 - Flash memory device and fabricating method therefor - Google Patents

Flash memory device and fabricating method therefor Download PDF

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Publication number
US20040056300A1
US20040056300A1 US10/316,908 US31690802A US2004056300A1 US 20040056300 A1 US20040056300 A1 US 20040056300A1 US 31690802 A US31690802 A US 31690802A US 2004056300 A1 US2004056300 A1 US 2004056300A1
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United States
Prior art keywords
semiconductor substrate
groove
source region
gate
floating gate
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US10/316,908
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English (en)
Inventor
Tae Choi
Jae Kim
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DongbuAnam Semiconductor Inc
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Anam Semiconductor Inc
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Assigned to ANAM SEMICONDUCTOR, INC. reassignment ANAM SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, TAE HO, KIM, JAE YEONG
Priority to US10/679,483 priority Critical patent/US6844232B2/en
Publication of US20040056300A1 publication Critical patent/US20040056300A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel

Definitions

  • the present invention relates to a semiconductor device and a fabricating method therefor; and, more particularly, to a flash memory device having an improved erase efficiency and a fabricating method therefor.
  • a non-volatile memory device does not lose information stored in its memory cells, even when its power is interrupted. This characteristic makes the non-volatile memory device be widely adopted in, e.g., computers, digital cameras, and mobile phones.
  • a flash memory device is one of typical non-volatile memory devices.
  • the flash memory device is a variation of an electrically erasable programmable read only memory (EEPROM) device, whose memory is erased by a sector-by sector bias.
  • EEPROM electrically erasable programmable read only memory
  • the state or data of a memory cell depends on the number of electrons stored in a gate structure of the cell.
  • the cell's data is altered by applying a strong electric field between the gate structure and a source (or drain) to transfer electrons therebetween.
  • the process of removing electrons from the gate structure is called an erase operation, and the process of accumulating electrons therein is called a program operation.
  • the flash memory device is classified into a stack gate or a split gate structure.
  • the stack gate type flash memory is a most commonly used cell in flash memories and includes a control gate for receiving a driving voltage and a floating gate for storing electrons, wherein the control gate is simply stacked on the floating gate.
  • the split gate type flash memory includes a select gate and a floating gate, wherein a portion of the select gate overlaps with the floating gate and the other portion thereof is arranged on a surface of a substrate.
  • FIG. 1 shows a cell array of a typical stack gate type flash memory device.
  • the architecture includes a multiplicity of horizontal word lines “WL 1 -WLm” and a plurality of vertical bit lines “BL 1 -BLi”, “m” and “i” being integers, wherein a memory cell region is defined at each of the intersection regions of the word and the bit lines.
  • Installed at each of the memory cell regions is a cell transistor “T” having a source “S”, a drain “D”, and a gate “G”.
  • the source “S” of each transistor “T” is electrically connected to a common source line “SL”; the drain “D”, to a corresponding bit line; and the gate “G”, to a corresponding word line.
  • FIG. 2 presents a cross-sectional view of the cell transistor “T” shown in FIG. 1 according to a prior art.
  • a source region 7 a and a drain region 7 b respectively serving as the source “S” and the drain “D” are disposed in a semiconductor substrate 2 , on which a gate or tunnel oxide 3 , a floating gate 4 , an inter-gate insulating layer 5 , and a control gate 6 are sequentially disposed.
  • the drain region 7 b is spaced apart from the source region 7 a by a channel interposed therebetween.
  • the floating gate 4 may overlap with opposing end portions of the source region 7 a and the drain region 7 b.
  • a first programming voltage (e.g., 10V) is applied to the control gate 6 via a corresponding word line and a second programming voltage (e.g., 6V) is applied to the drain region 7 b via a corresponding bit line, while the source region 7 a and the semiconductor substrate 2 are grounded.
  • the first and the second programming voltage induce electrons at the channel region close to the drain region 7 b to be injected through the gate oxide 3 into the floating gate 4 and stored therein, thus completing the program operation.
  • a first erasing voltage (e.g., 6V) is applied to the source region 7 a via the source line “SL” (FIG. 1) and a second erasing voltage (e.g., ⁇ 9V) is applied to a corresponding gate line, whereby the electrons stored in the floating gate 4 are removed to the source region 7 a through the tunnel oxide 3 .
  • Raising the erasing voltage or reducing the thickness of the tunnel oxide may provide a higher erase efficiency of the above-explained stack gate cell transistor.
  • such an increased erasing voltage or a reduced thickness of the tunnel oxide deteriorates the durability of the flash memory device.
  • a cell transistor for a flash memory device including: a semiconductor substrate having a groove; a source region disposed in the semiconductor substrate, wherein the groove is recessed into an end portion of the source region; a drain region disposed in the semiconductor substrate to oppose the end portion of the source region; a gate insulating layer disposed on the substrate; and a floating gate, an inter-gate insulating layer, and a control gate sequentially disposed on the gate insulating layer, the floating gate overlapping with each opposing end portion of the source region and the drain region, wherein a portion of the floating gate protrudes to fill the groove in the source region.
  • a method of fabricating a cell transistor including the steps of: forming a groove recessed into a semiconductor substrate; forming a source region in the semiconductor substrate, wherein the source region overlaps with the groove; sequentially forming a gate insulating layer, a floating gate, an inter-gate layer, and a control gate on the semiconductor substrate, wherein the floating gate fills the groove of the semiconductor substrate; and forming a drain region in the semiconductor substrate to thereby fabricate the cell transistor.
  • FIG. 1 presents a schematic array of a stack gate type flash memory device
  • FIG. 2 provides a cross-sectional view of a conventional stack gate type cell transistor
  • FIG. 3 represents a cross-sectional view of a cell transistor of a stack gate type flash memory in accordance with a preferred embodiment of the present invention.
  • FIGS. 4A to 4 J are sequential cross-sectional views illustrating a method for fabricating the cell transistor shown in FIG. 3.
  • FIGS. 3 to 4 a stack gate type flash memory device and a fabricating method therefor in accordance with a preferred embodiment of the present invention will be described in detail.
  • Like numerals represent like parts in the drawings.
  • a cell transistor 10 of the stack gate type flash memory device in accordance with the preferred embodiment of the present invention includes a semiconductor substrate 100 having a groove 108 . Disposed therein are a source region 112 and a drain region 122 defining a channel region therebetween; sequentially disposed thereon are a gate insulating layer 114 , a floating gate 116 a having a tip 116 b , an inter-gate insulating layer 118 a , and a control gate 120 a .
  • the gate insulating layer 114 can be provided in the region right below the floating gate 116 a , wherein the source region 112 and the drain region 122 can be covered with a different insulating layer.
  • the source region 112 and the drain region 122 are positioned to oppose each other at end portions thereof with a channel region interposed therebetween.
  • the groove 108 is provided at the end portion of the source region 112 so that the source region 112 has thereat a greater depth.
  • the floating gate 116 a overlaps with the end portions of the source region 112 and the drain region 122 .
  • the groove 108 is preferably a V-shaped, a U-shaped, or a rectangular groove and the tip 116 b of the floating gate 116 a is of a conformal shape as the groove 108 .
  • the groove 108 is preferably formed to have a depth of about 0.1 ⁇ m to about 0.2 ⁇ m when measured from a top surface of the source region 112 , and a width of about 0.1 ⁇ m to about 0.2 ⁇ m when measured thereon.
  • the floating gate 116 a is preferably positioned to make the source region 112 overlap with an overlap width of about 0.4 ⁇ m to about 0.6 ⁇ m.
  • FIGS. 4A to 4 J a sequential process for fabricating the cell transistor shown in FIG. 3 will be explained.
  • a buffer layer 102 and an etching mask layer 104 are sequentially formed on the semiconductor substrate 100 . It is preferable that the buffer layer 102 and the etching mask layer 104 have different etching selectivities. For example, if the buffer layer 102 is made of silicon oxide, the etching mask layer 104 can be made of silicon nitride.
  • the etching mask layer 104 is photolithographically patterned such that an opening portion 104 a is formed therethrough. A corresponding portion of the buffer layer 102 is exposed through the opening portion 104 a.
  • a spacer 106 is formed on a side wall of the opening portion 104 a by blanket-depositing and etching an insulating material on the etching mask layer 104 and the buffer layer 102 exposed through the opening portion 104 a .
  • the insulating material for the spacers 106 and the etching mask layer 104 may have the same or different etching selectivities. For example, a silicon nitride can be selected for each of them.
  • a width of the exposed portion of the buffer layer 102 is reduced because the spacer 106 covers peripheries thereof in this step, wherein the spacer serves to further reduce the exposed area of the buffer layer 102 . Since the width of the exposed portion of the buffer layer 102 defines the width of the groove 108 shown in FIG. 3, the reduction thereof in this step may help to reduce the cell size.
  • the exposed portion of the buffer layer 102 is removed and a dry etching or a wet etching is applied to the semiconductor substrate 100 such that a groove 108 is formed.
  • the groove 108 may be a V-shaped, a U-shaped or a rectangular groove.
  • the groove 108 is preferably set to have a depth of about 0.1 ⁇ m to about 0.2 ⁇ m and a width of about 0.1 ⁇ m to about 0.2 ⁇ m.
  • the etching mask layer 104 and the spacers 106 are removed.
  • a source dopant is implanted in the semiconductor substrate 100 through a non-covered portion of the buffer layer 102 so that the source region 112 is formed to overlap with the groove 108 at an end portion thereof.
  • a high concentration N-type implantation may be used to form the source region 112 , so that the cell transistor in accordance with the preferred embodiment becomes an N-channel type.
  • An N-type dopant e.g., phosphorous (P) or arsenic (As), is employed for the N-type implantation.
  • the gate insulating layer 114 serving as a tunnel oxide under the floating gate 116 a in FIG. 3 is conformally formed by thermal oxidation to cover an upper surface of the semiconductor substrate 100 . Then, a first conductive layer 116 , another insulating layer 118 , and a second conductive layer 120 are sequentially formed on the gate insulating layer 114 .
  • the first conductive layer 116 has the tip 116 b filling the groove 108 of the semiconductor substrate 100 .
  • Each of the first and the second conductive layer 116 and 120 may be a single or multilayers of doped polysilicon or metal.
  • the insulating layer 118 may be a single or multilayers of silicon oxide, silicon nitride, or a high dielectric constant material, e.g., Ta 2 O 5 .
  • a second photoresist pattern 124 is formed on the second conductive layer 120 to define a gate region of the cell transistor, wherein the second photoresist pattern 124 is positioned over the groove 108 . Then, the first conductive layer 116 , the insulating layer 118 , and the second conductive layer 120 are patterned by using the photoresist pattern 124 used as a mask, so that the floating gate 116 a , the inter-gate insulating layer 118 a , and the control gate 120 a are respectively formed, as shown in FIG. 4I. Because the second photoresist pattern 124 overlays the groove 108 , the control gate 120 a and the floating gate 116 a , each being formed by using the second photoresist pattern 124 , also overlay the end portion of the source region 112 .
  • a drain dopant is implanted in the semiconductor substrate 100 through the gate insulating layer 114 so that the drain region 122 is formed therein.
  • the high concentration N-type implantation may be also used to form the drain region 122 , wherein the N-type dopant, e.g., phosphorous (P) or arsenic (As), is employed therefor.
  • the third photoresist pattern is removed.
US10/316,908 2002-09-19 2002-12-12 Flash memory device and fabricating method therefor Abandoned US20040056300A1 (en)

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KR10-2002-0057111A KR100485485B1 (ko) 2002-09-19 2002-09-19 플래시 메모리 장치의 셀 트랜지스터 및 그 제조 방법
KR2002-57111 2002-09-19

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1571703A3 (en) * 2004-03-04 2005-10-05 Texas Instruments Incorporated Eeprom with etched tunneling window
US9431107B2 (en) * 2012-12-14 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Memory devices and methods of manufacture thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100456702B1 (ko) * 2002-12-05 2004-11-10 삼성전자주식회사 플로팅 게이트를 갖는 비휘발성 기억 셀들 및 그 형성방법
KR100771539B1 (ko) 2005-12-29 2007-10-31 주식회사 하이닉스반도체 리세스 게이트를 갖는 반도체 소자 및 그 제조방법
KR100723437B1 (ko) 2006-05-30 2007-05-30 삼성전자주식회사 반도체 플래시 메모리 소자 및 그 제조 방법
KR100857741B1 (ko) 2006-10-02 2008-09-10 삼성전자주식회사 불휘발성 메모리 소자 및 제조방법
JP2009021305A (ja) * 2007-07-10 2009-01-29 Denso Corp 不揮発性メモリトランジスタ
KR101420695B1 (ko) * 2013-01-16 2014-07-17 계명대학교 산학협력단 지역전계강화 더블 폴리 이이피롬

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EP1571703A3 (en) * 2004-03-04 2005-10-05 Texas Instruments Incorporated Eeprom with etched tunneling window
US7307309B2 (en) 2004-03-04 2007-12-11 Texas Instruments Incorporated EEPROM with etched tunneling window
US9431107B2 (en) * 2012-12-14 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Memory devices and methods of manufacture thereof
US20160359052A1 (en) * 2012-12-14 2016-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Memory Devices and Methods of Manufacture Thereof
US10043919B2 (en) * 2012-12-14 2018-08-07 Taiwan Semiconductor Manufacturing Company Memory devices and methods of manufacture thereof
US10510902B2 (en) 2012-12-14 2019-12-17 Taiwan Semiconductor Manufacturing Company Memory devices and methods of manufacture thereof
US10770598B2 (en) 2012-12-14 2020-09-08 Taiwan Semiconductor Manufacturing Company Memory devices and methods of manufacture thereof
US11251314B2 (en) 2012-12-14 2022-02-15 Taiwan Semiconductor Manufacturing Company Memory devices and methods of manufacture thereof

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KR20040025242A (ko) 2004-03-24
US20040071025A1 (en) 2004-04-15
KR100485485B1 (ko) 2005-04-27
US6844232B2 (en) 2005-01-18
JP2004111892A (ja) 2004-04-08

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