US20040050708A1 - Plating method for PCB - Google Patents

Plating method for PCB Download PDF

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Publication number
US20040050708A1
US20040050708A1 US10/644,036 US64403603A US2004050708A1 US 20040050708 A1 US20040050708 A1 US 20040050708A1 US 64403603 A US64403603 A US 64403603A US 2004050708 A1 US2004050708 A1 US 2004050708A1
Authority
US
United States
Prior art keywords
connection portion
electrolyte layer
substrate
power connection
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/644,036
Other languages
English (en)
Inventor
Yu-Seock Yang
Sung-Gue Lee
Yong-Soon Jang
Hyung-Kun Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
LG Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Electronics Inc filed Critical LG Electronics Inc
Assigned to LG ELECTRONICS INC. reassignment LG ELECTRONICS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, YONG-SOON, KIM, HYUNG-KUN, LEE, SUNG-GUE, YANG, YU-SEOCK
Publication of US20040050708A1 publication Critical patent/US20040050708A1/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Definitions

  • the present invention relates to a printed circuit board and, more particularly, to a plating method for a printed circuit board that is capable of forming a plated layer without a power supply line for gold-plating at a pad.
  • FIG. 1 is a plane view showing a major part of a printed circuit board in accordance with a conventional art
  • FIG. 2 is a sectional view showing the major part of a printed circuit board in accordance with the conventional art.
  • a plurality of printed circuit boards 1 a and 1 b are formed on one substrate 1 and as they are separated, the plurality of printed circuit boards 1 a and 1 b are completely produced.
  • the conventional printed circuit board there are formed at a surface of a base material 8 , a plurality of bonding pads 3 on which a plurality of bonding wires are bonded to be electrically connected to a semiconductor chip and a plurality of ball pads 4 on which a solder ball is attached for connection with another printed circuit board.
  • circuit patterns are formed by a single layer or multi-layer inside the printed circuit board. The bonding pads 3 and the ball pads 4 are electrically connected to the circuit patterns.
  • the bonding pad 3 and the ball pad 4 are gold-plated to heighten a bond strength with a gold wire and solder ball.
  • a power supply line 5 and a plurality of lead-in wires are formed on the surface of the printed circuit board for supplying power to the bonding pad 3 and ball pad 4 , thus to gold-plate on the pad 3 and 4 .
  • the power supply line 5 is formed long with a certain width at the center of the surface of the base material 8 , and the lead-in wires 6 are branched from the power supply line 5 and connected to the bonding pads 3 or the ball pads 4 . Because much current flows in the power supply line 5 , the power supply line 5 is formed wider in its width than the lead-line wires 6 .
  • a process is performed to separate to a plurality of printed circuit boards. That is, cutting along a router cut line 7 by using a router separates printed circuit boards 1 a and 1 b.
  • the plating method for the printed circuit board in accordance with the conventional has the following problems.
  • the lead-in wires 6 to which the bonding pads and ball pads 4 are connected remain at the surface of the completed printed circuit boards 1 a and 1 b , when a semiconductor chip is mounted for use on the printed circuit board, the lead-in wires 6 cause an interference with peripheral circuits or increase a power consumption and serve as an element hindering a signal flow, resulting in degradation of a performance of a product.
  • the lead-in wires are removed by etching method after performing a gold-plating on the bonding pads 3 and the ball pads 4 .
  • an object of the present invention is to provide a plating method for a printed circuit board that is capable of reducing power consumption and improving a performance of a product by providing a printed circuit board with a lead-in wire.
  • a plating method for a printed circuit board including: A plating method for a printed circuit board comprising: a first step of providing a substrate having a plurality of connection pads and circuit patterns connected to the connection pads; a second step of using some of the circuit patterns provided on a surface of the substrate as a power connection portion and connecting the power connection portion to an external power source; a third step of covering a surface of the substrate excepting the connection pads with a plating resistance resist to shield it; a fourth step of supplying power to the connection pad through the power connection portion and forming a gold-plated layer on the connection pad; and a fifth step of making the power connection portion and the external power source to be electrically short.
  • the second step includes: coating a photoresist at the surface of the substrate; removing a portion of the photoresist to expose the connection pad and exposing some of the circuit patterns to form a power connection portion; and coating an electrolyte layer on the surface of the substrate for connecting between the power connection portion and an external power source.
  • the electrolyte layer is formed through an electroless plating method, and the electrolyte layer has a thickness of 0.3 ⁇ 0.7 ⁇ m.
  • the plating resistance resist is coated at the surface of the substrate with the electrolyte layer formed thereon
  • the fifth step includes: removing the electrolyte layer and the plating resistance resist; and coating a photoresist at the surface of the electrolyte layer and the plating resistance resist-removed substrate to cover the power connection portion to make power short.
  • a plating method for a printed circuit board including: a first step of providing a substrate having a plurality of bonding pads and ball pads at both sides thereof and a circuit pattern to which the bonding pads and the ball pads are connected; a second step of using some of the circuit patterns provided at the surface of the substrate as first and second power connection portions and connecting the first power connection portion to an external power source; a third step of covering the surface of the substrate with the ball pad formed thereon with a plating resistance resist to shield it; a fourth step of supplying power to the bonding pad through the first power connection portion to form a gold-plated layer on the bonding pad; a fifth step of making the first power connection portion and the external power source to be electrically short; a sixth step of connecting the second power connection portion to the external power source and coating a plating resistance resist at the surface of the substrate with the ball pad formed thereon to shield it; a seventh step of supplying power to the ball pad through the second power connection portion to form a
  • the second step includes: coating a photoresist at both surfaces of the substrate; removing a portion of the photoresist to expose the bonding pad and the ball pad and exposing some of the circuit patterns to form first and second connection portion; and coating an electrolyte layer at the surface of the substrate where the ball pad is formed in order to connect the first power connection portion to an external power source.
  • the fifth step includes: removing the electrolyte layer and the plating resistance resist; and coating a photoresist at the surface of the electrolyte layer and the plating resistance resist-removed substrate to cover the first power connection portion to make power short.
  • the sixth step includes: forming an electrolyte layer at the surface of the substrate where the bonding pad is formed to electrically connect it to the second power connection portion; and coating a plating resistance resist at a surface of the electrolyte layer.
  • the eighth step includes: removing the plating resistance resist and the electrolyte layer; and covering the second power connection portion with a photoresist to make the second power connection to be short electrically.
  • FIG. 1 is a plane view showing one example of a printed circuit board in accordance with a conventional art
  • FIG. 2 is a perspective view showing the printed circuit board in accordance with the conventional art
  • FIG. 3 is a plane view showing another example of a printed circuit board in accordance with the conventional art
  • FIGS. 4A to 4 L show sequential process of a method for fabricating a circuit pattern of a printed circuit board in accordance with a preferred embodiment of the present invention.
  • FIGS. 5A to 5 E are plane views sequentially shoring a circuit pattern fabrication process of the printed circuit board in accordance with the preferred embodiment of the present invention.
  • FIGS. 4A to 4 L show sequential process of a method for fabricating a circuit pattern of a printed circuit board in accordance with a preferred embodiment of the present invention.
  • a plating method for a printed circuit board of the present invention will now be described with reference to FIGS. 4A to 4 L.
  • a substrate 50 is prepared.
  • the substrate 50 includes an insulation layer 52 formed as at least one or more insulation materials are thermally compressed and a plurality of circuit patterns 54 stacked inside the insulation layer 52 .
  • a metal layer 56 is formed at both surfaces of the insulation layer 52 , and a plurality of through holes 58 are formed to electrically connect the circuit patterns 54 and the metal layers 56 (refer to FIG. 4A).
  • the substrate 50 is fabricated through a fabrication process of a general multi-layer printed circuit board in which circuit patterns are formed on a plurality of insulation plates, which are stacked by plural ones and thermally compressed.
  • a metal-plated layer 60 is formed at the surface of the substrate 50 through a plating process.
  • the metal-plated layer 60 is formed at the surface of the metal layer 56 and at an inner wall of the through hole 58 .
  • the metal-plated layer 60 formed at the surface of the metal layer 56 serves to form circuit patterns 54 and the metal-plated layer 60 formed at the inner wall of the through hole 58 serves to electrically connect the circuit patterns in a follow-up process (refer to FIG. 4B).
  • the metal layer 56 and the metal-plated layer 60 are selectively removed to form a circuit pattern 62 . That is, the circuit patterns 62 are formed at both surfaces of the substrate 50 through a general exposure/development process and an etching process, and some of the circuit patterns 62 are used as a bonding pad 64 electrically connected to a semiconductor chip and some other circuit patterns are used as a ball pad 66 electrically connected to another printed circuit board. In general, the ball pad 66 is formed at the opposite side of the side where the bonding pad 65 is formed.
  • the bonding pad 64 is connected to a gold wire for electrical connection with the semiconductor chip mounted at the printed circuit board, and electrically connected to the circuit pattern 62 formed at the through hole 58 by the connection pattern 68 .
  • a solder ball is attached to the ball pad 66 for connection with a different printed circuit board, and the ball pad 66 is electrically connected to the circuit pattern 62 formed at the through hole 58 by the connection pattern 68 .
  • a photoresist 70 is coated at the surface of the substrate 50 .
  • the photoresist 70 is to protect the circuit patterns 62 and is not coated at the connection pads 64 and 66 making the bonding pad 64 and the ball pad 66 .
  • connection pads 64 and 66 are removed through an additional process to expose the connection pads 64 and 66 .
  • First and second power connection portions 72 and 74 are formed to be used as a path for supplying power to the connection pads 64 and 66 .
  • the first and second power connection portions 72 and 74 are formed by exposing a portion of the circuit pattern 62 by removing a portion of the photoresist 70 . That is, a portion of the circuit pattern 62 formed connected to the through hole 58 is exposed (refer to FIG. 4D).
  • connection pads 64 and 66 A process of forming a gold-plated layer at the connection pads 64 and 66 will now be described.
  • electrolyte layers 76 and 78 are formed at the both surfaces of the substrate 50 to connect the first and second power connection portions 72 and 74 to an external power source.
  • the electrolyte layers 76 and 78 are made of copper and formed through an electroless plating method or sputtering (refer to FIGS. 4E and 5A). Formation of the electrolyte layers 76 and 78 through the electroless plating method is to make the electrolyte layer 76 to be formed well also at the surface of the photoresist 70 .
  • the electrolyte layers 76 and 78 are copper-plated through the electroless plating method and additionally the electrolyte layers 76 and 78 are copper-plated through an electrolytic copper plating method in order to obtain a desired thickness.
  • the electrolyte layers 76 and 78 are preferably formed as thin as possible so as to be easily removed in a follow-up process.
  • the electrolyte layer 76 and 78 having a thickness of 0.3 ⁇ m ⁇ 0.7 ⁇ m.
  • the electrolyte layer 76 of the surface where the bonding pad 64 is formed is removed through an etching method or the like (refer to FIGS. 4G and 5B). At this time, because the plating resistance resist 80 has been coated at the surface where the ball pad 66 is formed, that is, the opposite side of the bonding pad 64 , the electrolyte layer 78 is not removed.
  • the electrolyte layer 78 may be formed only at the surface where the ball pad 66 is formed, while the electrolyte layer 76 may not be formed at the surface where the bonding pad 64 is formed.
  • a gold-plated layer 82 is formed at the surface of the bonding pad 64 (refer to FIG. 4H).
  • the arrow illustrated in FIG. 4H indicates a power supply path and the circuit pattern 62 is formed in a ring shape at the surface of the through hole 58 and electrically connects the first power connection portion 72 and the bonding pad 64 .
  • the plating resistance resist 80 and the electrolyte layer 78 formed at the surface where the ball pad 66 is provided are removed. And then, the first power connection portion 72 is covered with the photoresist 70 to make it electrically short (refer to FIGS. 4I, 5C and 5 D).
  • a gold-plated layer 92 is formed at the ball pad 66 .
  • electrolyte layers 86 and 88 are formed at both surfaces of the above process-completed substrate 50 . Then, the second power connection portion 74 and the electrolyte layer 88 are electrically connected.
  • a plating resistance resist 90 is coated at the surface of the electrolyte layer 88 formed at the side where the bonding pad 64 is provided.
  • the electrolyte layer 86 coated at the surface where the ball pad 66 is provided is removed through an etching method or the like (refer to FIG. 4J).
  • the external power (P) is supplied to the electrolyte layer 88 and applied to the ball pad 66 through the second power connection portion 74 connected to the electrolyte layer 88 and the circuit pattern 62 formed at the through hole 58 and the connection pad 68 .
  • the plating resistance resist 90 and the electrolyte layer 88 are removed and the second power connection portion 74 is covered with the photoresist 70 so that the second power connection portion 74 can be electrically short.
  • the method for fabricating a circuit pattern of a printed circuit board fabricated through the above-described process has the following advantage.
US10/644,036 2002-09-14 2003-08-20 Plating method for PCB Abandoned US20040050708A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020020055977A KR20040024381A (ko) 2002-09-14 2002-09-14 인쇄회로기판의 도금방법
KR55977/2002 2002-09-14

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US20040050708A1 true US20040050708A1 (en) 2004-03-18

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US10/644,036 Abandoned US20040050708A1 (en) 2002-09-14 2003-08-20 Plating method for PCB

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US (1) US20040050708A1 (ko)
KR (1) KR20040024381A (ko)
CN (1) CN1306856C (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070111491A1 (en) * 2005-11-13 2007-05-17 Hsu Jun C Process for electroplating metal layer without plating lines after the solder mask process
CN100455161C (zh) * 2004-12-07 2009-01-21 鸿富锦精密工业（深圳）有限公司 一种印刷电路板设计方法及印刷电路板
CN103046031A (zh) * 2012-12-11 2013-04-17 胜宏科技（惠州）股份有限公司 一种线路板化学镀金方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1310297C (zh) * 2004-06-22 2007-04-11 威盛电子股份有限公司 无电镀条的封装基板及其制作方法
KR100641851B1 (ko) * 2004-10-25 2006-11-03 엘지전자 주식회사 인쇄회로기판의 제조방법
CN101437357B (zh) * 2007-11-14 2010-07-14 英业达股份有限公司 印刷电路板的焊垫结构及其形成方法
CN102268718B (zh) * 2011-07-13 2013-07-10 番禺得意精密电子工业有限公司 输入设备、电镀装置及利用该电镀装置进行电镀的方法
CN114883252B (zh) * 2022-05-26 2024-02-23 业成光电（深圳）有限公司 基板电镀方法、基板、显示面板、显示装置及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567295A (en) * 1994-01-11 1996-10-22 Dell Usa L.P. Method and apparatus for making staggered blade edge connectors
US6132588A (en) * 1996-08-09 2000-10-17 Matsushita Electric Works, Ltd. Method for plating independent conductor circuit
US6376049B1 (en) * 1997-10-14 2002-04-23 Ibiden Co., Ltd. Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole
US6436803B2 (en) * 1996-06-28 2002-08-20 International Business Machines Corporation Manufacturing computer systems with fine line circuitized substrates

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0335594A (ja) * 1989-07-03 1991-02-15 Matsushita Electric Works Ltd 多層プリント配線板の加工方法
JPH04110491A (ja) * 1990-08-31 1992-04-10 Sony Corp 配線基板
JP4129665B2 (ja) * 1999-10-12 2008-08-06 日本サーキット工業株式会社 半導体パッケージ用基板の製造方法
JP2002158423A (ja) * 2000-11-21 2002-05-31 Oki Electric Ind Co Ltd プリント配線板の構造および電解メッキ処理方法
JP2002232154A (ja) * 2001-02-07 2002-08-16 Mitsumi Electric Co Ltd 金めっき基板のめっき用引出し線配線方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567295A (en) * 1994-01-11 1996-10-22 Dell Usa L.P. Method and apparatus for making staggered blade edge connectors
US6436803B2 (en) * 1996-06-28 2002-08-20 International Business Machines Corporation Manufacturing computer systems with fine line circuitized substrates
US6132588A (en) * 1996-08-09 2000-10-17 Matsushita Electric Works, Ltd. Method for plating independent conductor circuit
US6376049B1 (en) * 1997-10-14 2002-04-23 Ibiden Co., Ltd. Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100455161C (zh) * 2004-12-07 2009-01-21 鸿富锦精密工业（深圳）有限公司 一种印刷电路板设计方法及印刷电路板
US20070111491A1 (en) * 2005-11-13 2007-05-17 Hsu Jun C Process for electroplating metal layer without plating lines after the solder mask process
CN103046031A (zh) * 2012-12-11 2013-04-17 胜宏科技（惠州）股份有限公司 一种线路板化学镀金方法

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KR20040024381A (ko) 2004-03-20
CN1494369A (zh) 2004-05-05
CN1306856C (zh) 2007-03-21

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Owner name: LG ELECTRONICS INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, YU-SEOCK;LEE, SUNG-GUE;JANG, YONG-SOON;AND OTHERS;REEL/FRAME:014416/0938

Effective date: 20030714

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION