US20030030123A1 - Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same - Google Patents

Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same Download PDF

Info

Publication number
US20030030123A1
US20030030123A1 US10/214,582 US21458202A US2003030123A1 US 20030030123 A1 US20030030123 A1 US 20030030123A1 US 21458202 A US21458202 A US 21458202A US 2003030123 A1 US2003030123 A1 US 2003030123A1
Authority
US
United States
Prior art keywords
memory device
insulating film
semiconductor memory
conductive layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/214,582
Other languages
English (en)
Inventor
Masayuki Ichige
Kikuko Sugimae
Riichiro Shirota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001244558A external-priority patent/JP4309078B2/ja
Priority claimed from JP2001244557A external-priority patent/JP4266089B2/ja
Application filed by Individual filed Critical Individual
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ICHIGE, MASAYUKI, SHIROTA, RIICHIRO, SUGIMAE, KIKUKO
Publication of US20030030123A1 publication Critical patent/US20030030123A1/en
Priority to US10/891,133 priority Critical patent/US7067872B2/en
Priority to US11/434,059 priority patent/US7563664B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Definitions

  • the present invention relates to a semiconductor memory device equipped with a memory transistor including a floating gate and a control gate and a peripheral transistor for controlling the memory transistor, and to a method of manufacturing the particular semiconductor memory device.
  • a NAND type flash memory which is a kind of nonvolatile memory, comprises a memory transistor in which a floating gate and a control gate are laminated one upon the other and a peripheral transistor is arranged to surround the periphery of the memory transistor.
  • the gate of the peripheral transistor is formed by using an electrode material equal to that of the floating gate of the memory transistor.
  • FIGS. 58A, 58B to 66 A, 66 B are cross sectional views collectively showing a conventional method of manufacturing a semiconductor memory device.
  • FIGS. 58A to 66 A are cross sectional views perpendicular to the element separating region included in the memory cell region.
  • FIGS. 58B to 66 B are cross sectional views perpendicular to the gate electrode in the memory cell region.
  • a first insulating film 12 forming a gate insulating film is formed on a semi-conductor substrate (silicon substrate) 11 , followed by forming a first electrode material layer 13 on the first insulating layer 12 , as shown in FIGS. 58A and 58B.
  • the first electrode material layer 13 is formed of a polycrystalline silicon (polysilicon) into which an impurity is not introduced.
  • a second insulating film 14 is formed on the first electrode material layer 13 , followed by forming an element separating region of an STI (Shallow Trench Isolation) structure consisting of an element separating insulating film 15 such that the element separating insulating film 15 extends through the second insulating film 14 , the first electrode material layer 13 , and the first insulating film 12 into the semiconductor substrate 11 .
  • STI Shallow Trench Isolation
  • the element separating insulating film 15 is partly etched such that the upper surface of the element separating insulating film 15 is positioned lower than the upper surface of the first electrode material layer 13 , followed by peeling off the second insulating film 14 , as shown in FIGS. 59A and 59B.
  • a resist layer 16 a is formed on the first electrode material layer 13 in the PMOS region, as shown in FIGS. 60A and 60B.
  • ion implantation using, for example, phosphorus ions is applied to the first electrode material layer 13 in the memory cell region with the resist layer 16 a used as a mask, followed by applying anneal to the ion-implanted region so as to form N + -type first conductive layers 13 a , 13 b .
  • the reference numeral 13 a shown in FIGS. 60A, 60B denotes the first conductive layer in the memory cell region
  • 60A, 60B denotes the first conductive layer in the NMOS region. It should also be noted that the first conductive layer 13 a in the memory cell region performs the function of the floating gate of the memory transistor. After formation of the N + -type first conductive layers 13 a , 13 b , the resist layer 16 a is removed.
  • a resist layer 16 b is formed on the first conductive layers 13 a , 13 b as shown in FIGS. 61A, 61B.
  • ion implantation using, for example, boron ions is applied to the first electrode material layer 13 in the PMOS region, followed by applying annealing to the ion-implanted region so as to form a P + -type first conductive layer 13 c .
  • the resist layer 16 b is removed.
  • a third insulating film 17 is deposited over the first conductive layers 13 a , 13 b , 13 c and the element separating insulating film 15 , as shown in FIGS. 62A and 62B, followed by depositing a second electrode material layer 18 on the third insulating film 17 .
  • the second electrode material layer 18 is formed of polysilicon into which an impurity is not introduced.
  • a resist layer 19 is formed on the second electrode material layer 18 , followed by patterning the resist layer 19 , as shown in FIGS. 63A, 63B.
  • the patterned resist layer 19 is used as a mask in the next step for removing the second electrode material layer 18 , the insulating film 17 and the first conductive layers 13 a , 13 b , 13 c , thereby forming the gate patterns of the memory transistor and the peripheral transistor.
  • the resist layer 19 is removed, followed by a post-oxidation treatment.
  • an insulating film 22 is formed on the side surface of the gate of the peripheral transistor, as shown in FIGS. 64A, 64B, followed by forming a resist layer 23 on the first insulating film 12 and the second electrode material layer 18 included in the PMOS region.
  • the resist layer 23 thus formed is used as a mask in the subsequent step for introducing, for example, arsenic (As) ions as an impurity by means of ion implantation, followed by diffusing the introduced impurity by annealing.
  • a second conductive layer 18 a forming the control gate of the memory transistor and N + -type source/drain diffusion layers 21 are formed in the memory cell region.
  • a second conductive layer 18 b and N + -type source/drain diffusion layers 24 are formed in the NMOS region.
  • the resist layer 23 is removed.
  • a resist layer 25 is formed on the first insulating film 12 and the second conductive layers 18 a , 18 b in the memory cell region and the NMOS region.
  • ion implantation is performed by using, for example, boron ions as an impurity, followed by applying annealing to the ion-implanted region so as to diffuse the implanted boron ions.
  • a second conductive layer 18 c and P + -type source/drain layers 26 are formed in the PMOS region.
  • the resist layer 25 is removed.
  • the first insulating layer 12 is removed so as to expose the source/drain diffusion layers 21 , 24 and 26 to the outside, as shown in FIGS. 66A and 66B.
  • salicide (Self Aligned Silicide) films 27 a , 27 b , 27 c , 27 d consisting of a metal having a high melting point are formed on the second conductive layers 18 a , 18 b , 18 c and the source/drain diffusion layers 21 , 24 , 26 , respectively.
  • a memory transistor 28 is formed in the memory cell region, and an NMOS transistor 29 and a PMOS transistor 30 are formed in the peripheral circuit region.
  • the salicide film 27 a is formed on the control gate formed on the second conductive layer 18 a , and the salicide film 27 d is also formed on the source/drain diffusion layer 21 .
  • the salicide film 27 d is formed on the source/drain diffusion 21 of the memory cell region, it is possible for the reliability of the device characteristics such as the data retention characteristics and the data program/erase endurance cycle characteristics to be reduced in the flash memory. Also, where the salicide film 27 d is also formed on the source/drain diffusion layer 21 of the memory cell region, a serious problem is brought about that the degree of freedom in terms of the element design of the source-drain of the memory cell device is markedly limited in order to satisfy both the formation of the electrode material and the device operation.
  • CMOS transistors of a dual work function gate in a nonvolatile memory for a low power consumption and in a high performance transistor requiring a high operating speed.
  • the CMOS transistors include a surface channel type NMOS transistor and a surface channel type PMOS transistor. For forming these transistors, an electrode material into which an impurity is not introduced is deposited first.
  • the gate electrode of the dual work function gate structure was formed in the past by separately implanting P-type and N-type impurities by light exposure technology with the N-type gate electrode and the P-type electrode used as masks.
  • the conventional method of forming a gate electrode of the dual work function gate structure requires a large number of process steps and each process step is complex, leading to an increased manufacturing cost of the semiconductor memory device.
  • a semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes: first gate electrodes arranged a first distance apart from each other on a semiconductor substrate; second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate; first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes; second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes; a first insulating film formed on the first diffusion layer; second insulating films formed on the side surfaces of the second gate electrodes; first silicide films formed on the first gate electrodes; second silicide films formed on the second gate electrodes; and third silicide films formed on the second diffusion layers.
  • FIGS. 1A and 1B are cross sectional views collectively showing the construction of a semiconductor memory device according to a first embodiment of the present invention
  • FIGS. 2A, 2B, 3 A, 3 B, 4 A, 4 B, 5 A, 5 B, 6 A, 6 B, 7 A, 7 B, 8 A, 8 B, 9 A, 9 B, 10 A, 10 B, 11 A, 11 B, 12 A, 12 B, 13 A, 13 B, 14 A and 14 B are cross sectional views collectively showing the process of manufacturing a semiconductor memory device according to the first embodiment of the present invention
  • FIGS. 15A and 15B are cross sectional views collectively showing the construction of a semiconductor memory device according to a second embodiment of the present invention.
  • FIGS. 16A, 16B, 17 A, 17 B, 18 A, 18 B, 19 A, 19 B, 20 A, 20 B, 21 A, 21 B, 22 A, 22 B, 23 A, 23 B, 24 A and 24 B are cross sectional views collectively showing the process of manufacturing a semiconductor memory device according to the second embodiment of the present invention
  • FIGS. 25A, 25B, 26 A, 26 B, 27 A, 27 B, 28 A, 28 B, 29 A, 29 B, 30 A, 30 B, 31 A, 31 B, 32 A, 32 B, 33 A, 33 B, 34 A, 34 B, 35 A and 35 B are cross sectional views collectively showing the process of manufacturing a semiconductor memory device according to a third embodiment of the present invention.
  • FIGS. 36A, 36B, 37 A, 37 B, 38 A, 38 B, 39 A and 39 B are cross sectional views collectively showing the process of manufacturing a semiconductor memory device according to a fourth embodiment of the present invention.
  • FIG. 40 is cross sectional view collectively showing the construction of a semiconductor memory device according to a fifth embodiment of the present invention.
  • FIG. 41 is cross sectional view collectively showing the construction of another semiconductor memory device according to the fifth embodiment of the present invention.
  • FIG. 42 is a cross sectional view showing the construction of a semiconductor memory device according to a sixth embodiment of the present invention in a direction perpendicular to the element separating region;
  • FIG. 43 is a cross sectional view showing the construction of a semiconductor memory device according to the sixth embodiment of the present invention in a direction perpendicular to the gate electrode;
  • FIGS. 44, 45, 46 , 47 , 48 , 49 , 50 and 51 are cross sectional views collectively showing the manufacturing process of a semiconductor memory device according to the sixth embodiment of the present invention.
  • FIG. 52 is a graph showing the I-V characteristics of the semiconductor memory device according to the sixth embodiment of the present invention.
  • FIGS. 53, 54, 55 , 56 and 57 are cross sectional views collectively showing the manufacturing process of a semiconductor memory device according to a seventh embodiment of the present invention.
  • FIGS. 58A, 58B, 59 A, 59 B, 60 A, 60 B, 61 A, 61 B, 62 A, 62 B, 63 A, 63 B, 64 A, 64 B, 65 A, 65 B, 66 A and 66 B are cross sectional views collectively showing the conventional manufacturing process of a semiconductor memory device.
  • the first embodiment is directed to an example of the construction where a silicide film is not formed on the diffusion layer of the memory transistor, and all the insulating films between the first and second conductive layers constituting the gates of the peripheral transistor are removed.
  • the first embodiment is directed to a NAND type flash memory.
  • FIGS. 1A and 1B are cross sectional views collectively showing the construction of a semiconductor memory device according to a first embodiment of the present invention. It should be noted that FIG. 1A is a cross sectional view perpendicular to the element separating region of the memory cell, and FIG. 1B is a cross sectional view perpendicular to the gate electrode of the memory cell region.
  • the semiconductor memory device is provided with a memory cell region and a peripheral circuit region consisting of an NMOS region and a PMOS region.
  • a memory cell region In the memory cell region, gates of a memory transistor 28 are formed a first distance X apart from each other, and gates of an NMOS peripheral transistor 29 and a PMOS peripheral transistor 30 are formed a second distance Y, which is larger than the first distance X, apart from each other.
  • the gate of the memory transistor 28 includes a first conductive layer 13 a forming a floating gate and a second conductive layer 18 a forming a control gate.
  • an insulating film 17 is formed between the first and second conductive layers 13 a and 18 a .
  • the gate of the peripheral transistor 29 includes a first conductive layer 13 b and a second conductive layer 18 b .
  • the gate of the peripheral transistor 30 includes a first conductive layer 13 c and a second conductive layer 18 c . It should be noted that an insulating film is not formed between the first conductive layer 13 b and the second conductive layer 18 b . Also, an insulating film is not formed between the first conductive layer 13 c and the second conductive layer 18 c .
  • the clearance between the gates of the memory transistor 28 is filled with an insulating film 22 a , and an insulating film 22 b is formed on each of the side surfaces of the peripheral transistors 29 and 30 .
  • the insulating films 22 a and 22 b are formed simultaneously by the same material.
  • First diffusion layers 21 are formed within the semiconductor substrate (silicon substrate) 11 in a manner to have the gate of the memory transistor 28 sandwiched therebetween.
  • second diffusion layers 24 are formed within the semiconductor substrate 11 in a manner to have the gate of the peripheral transistor 29 sandwiched therebetween.
  • second diffusion layers 26 are formed within the semiconductor substrate 11 in a manner to have the gate of the peripheral transistor 30 sandwiched therebetween.
  • Salicide (Self Aligned Silicide) films 27 a , 27 b , and 27 c are formed on the gate of the memory transistor 28 , on the gates of the peripheral transistors 29 , 30 , and on the second diffusion layers 24 , 26 . It should be noted that a salicide film is not formed on the diffusion layer 21 of the memory transistor 28 .
  • the salicide films 27 a , 27 b , and 27 c are silicide films formed in self-aligned with a gate.
  • the clearance between the gates of the memory transistor 28 is filled with the insulating film 22 a .
  • the clearance noted above it is not absolutely necessary for the clearance noted above to be filled completely with the insulating film 22 a .
  • FIG. 1A shows that the insulating film 22 a is deposited to reach the surface of the gate of the memory transistor.
  • the insulating film 22 a it is not absolutely necessary for the insulating film 22 a to be deposited to reach the surface of the gate of the memory transistor, as far as the surface of the diffusion layer 21 is covered with the insulating film 22 a .
  • the gate of the memory transistor 28 and the gate of the peripheral transistor 29 it is possible for the gate of the memory transistor 28 and the gate of the peripheral transistor 29 to be arranged, for example, a second distance Y apart from each other.
  • FIGS. 2A, 2B to 14 A, 14 B are cross sectional views collectively showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.
  • the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention will now be described with reference to FIGS. 2A, 2B to 14 A, 14 B.
  • a first insulating film 12 forming a gate insulating film is formed on a semiconductor substrate 11 , as shown in FIGS. 2A and 2B.
  • the first insulating film 12 has a thickness of, for example, about 100 ⁇ .
  • a first electrode material layer 13 is formed on the first insulating film 12 .
  • the first electrode material layer 13 consists of polysilicon into which an impurity is not introduced.
  • a second insulating film 14 consisting of silicon nitride is formed on the first electrode material layer 13 .
  • an impurity is introduced into the channel region and the well region by means of ion implantation before formation of the first insulating film 12 in order to control the channel regions of the memory transistor and the peripheral transistor.
  • the second insulating film 14 , the first electrode material layer 13 , the first insulating film 12 and the semiconductor substrate 11 are selectively removed so as to form grooves for element separation.
  • An insulating film 15 for the element separation which consists of, for example, a silicon oxide film, is deposited within the groove for the element separation, followed by planarizing the insulating film 15 for the element separation until the surface of the second insulating film 14 is exposed to the outside.
  • the second insulating film 14 performs the function of a stopper film in planarizing the insulating film 15 for the element separation.
  • an element separating region of an STI (Shallow Trench Isolation) structure which consists of the insulating film 15 for the element separation, is formed.
  • the insulating film 15 for the element separation is partly etched such that the surface of the insulating film 15 for the element separation is positioned lower than the surface of the first electrode material layer 13 , followed by peeling off the second insulating film 14 , as shown in FIGS. 4A and 4B.
  • a resist layer 16 is formed on the first electrode material layer 13 , followed by patterning the resist layer 16 such that the resist layer 16 is left unremoved on only the peripheral circuit region. Then, ion implantation is applied to the first electrode material layer 13 in the memory cell region with the patterned resist layer 16 used as a mask, followed by applying annealing to the ion-implanted region of the first electrode material layer 13 so as to form a first conductive layer 13 a .
  • the ion implantation is performed by using, for example, phosphorus (P) ions as an N-type impurity under the condition that the first conductive layer 13 a has an impurity concentration of, for example, about 2 ⁇ 10 20 cm ⁇ 3 .
  • P phosphorus
  • As arsenic
  • a third insulating film 17 consisting of, for example, an ONO (Oxide Nitride Oxide) film is deposited to cover the first electrode material layer 13 , the first conductive layer 13 a and the insulating film 15 for the element separation, as shown in FIGS. 6A, 6B. Then, the third insulating film 17 in the peripheral circuit region is removed such that the third insulating film 17 is left unremoved in the memory cell region alone.
  • ONO Oxide Nitride Oxide
  • a second electrode material layer 18 is deposited on the third insulating film 17 , the first electrode material layer 13 and the insulating film 15 for the element separation, as shown in FIGS. 7A and 7B. It should be noted that the second electrode material layer 18 is formed of polysilicon into which an impurity is not introduced.
  • a resist layer 19 is formed on the second electrode material layer 18 , followed by patterning the resist layer 19 , as shown in FIGS. 8A and 8B. Then, the first and second electrode material layers 13 , 18 , the first conductive layer 13 a and the third insulating film 17 are removed with the patterned resist layer 19 used as a mask, thereby forming the gate patterns of the memory transistor and the peripheral transistor.
  • the resist layer 19 is removed as shown in FIGS. 9A and 9B. Then, a post-oxidation is performed so as to form an oxide film (not shown) on the gate. Further, a resist layer 20 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 20 such that the resist layer 20 is left unremoved in the peripheral region alone, as shown in FIGS. 10A and 10B. Further, ion implantation is performed with the patterned resist layer 20 used as a mask so as to form source/drain diffusion layers 21 within the semiconductor substrate 11 in the memory cell region. Where the memory transistor consists of an NMOS transistor, P or As is used as the impurity. Then, the resist layer 20 is removed.
  • a fourth insulating film 22 is formed to cover the first insulating film 12 and the second electrode material layer 18 , as shown in FIGS. 11A and 11B.
  • the fourth insulating film 22 is formed to fill completely the clearance between the gates of the memory cell region and not to fill the clearance between the gates of the peripheral circuit region.
  • the thickness A of the fourth insulating film 22 is determined to satisfy formula (1) given below:
  • X represents the distance between the gates of the memory cell region
  • Y represents the distance between the gates of the peripheral circuit region
  • A represents the thickness of the fourth insulating film 22 .
  • the thickness A of the fourth insulating film 22 is set to satisfy the relationship of formula (2) given below:
  • the distance Y between the gates of the peripheral circuit region it is possible for the distance Y between the gates of the peripheral circuit region to be 1.3 to 5.0 times as much as the distance X between the gates of the memory cell region.
  • the gate of the selecting transistor it is possible for the gate of the selecting transistor to be included in the gates of the peripheral circuit region.
  • the fourth insulating film 22 is formed of an oxide film.
  • the fourth insulating film 22 is formed of, for example, a TEOS (Tetra Ethyl Ortho Silicate) film, an ozone TEOS film, an HTO (High Temperature Oxide) film, an SOG (spin On Glass) film, a coating type oxide film, an SA-CVD (Semi Atmospheric—Chemical Vapor Deposition) film, a plasma CVD film, or a PSG (Phosphorus Silicate Glass) film.
  • TEOS Tetra Ethyl Ortho Silicate
  • HTO High Temperature Oxide
  • SOG spin On Glass
  • SA-CVD Semi Atmospheric—Chemical Vapor Deposition
  • plasma CVD or a PSG (Phosphorus Silicate Glass) film.
  • the fourth insulating film 22 is etched back so as to expose the surfaces of the second electrode material layer 18 , the first insulating film 12 or the diffusion layer region of the peripheral transistor, as shown in FIGS. 12A and 12B.
  • a buried insulating film 22 a is formed in the clearance between the gates in the memory cell region, and a side wall insulating film 22 b is formed on the side surface of each of the gates in the peripheral circuit region.
  • a resist layer 23 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 23 such that the resist layer 23 is left unremoved in the PMOS region alone, as shown in FIGS. 13A and 13B. Then, ion implantation using, for example, arsenic (As) ions as an impurity is performed with the patterned resist layer 23 used as a mask under the conditions that the accelerating energy is set at scores of KeV and the dose of the impurity is set at about 10 15 cm ⁇ 2 . In other words, an impurity is introduced into the second electrode material layer 18 in the memory cell region, the second electrode material layer 18 in the NMOS region, and the semiconductor substrate 11 .
  • As arsenic
  • first and second conductive layers 13 b , 18 b and N + -type source/drain diffusion layers 24 are formed in the NMOS region.
  • the first conductive layer 13 b of the NMOS region is formed by diffusing the impurity introduced into the second electrode material layer 18 of the NMOS region into the first electrode material layer 13 of the NMOS region. After formation of the first conductive layer 13 b , etc, referred to above, the resist layer 23 is removed.
  • a resist layer 25 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 25 such that the resist layer 25 is left unremoved in only the memory cell region and the NMOS region. Then, ion implantation using, for example, boron (B) ions as an impurity is performed with the patterned resist layer 25 used as a mask under the conditions that the accelerating energy is set at scores of KeV and the dose of the impurity is set at about 10 15 cm ⁇ 2 . In other words, an impurity is introduced into the second electrode material layer 18 in the PMOS region and into the semiconductor substrate 11 .
  • B boron
  • the introduced impurity is diffused by annealing so as to form first and second conductive layers 13 c , 18 c and P + -type source/drain diffusion layers 26 in the PMOS region.
  • the first conductive layer 13 c of the PMOS region is formed by diffusing the impurity introduced into the second electrode material layer 18 of the PMOS region into the first electrode material layer 13 of the PMOS region. After formation of the first and second conductive layers 13 c , 18 c , etc., the resist layer 25 is removed.
  • the oxide film on the gate is removed so as to expose the surface of the gate to the outside and, at the same time, the first insulating film 12 is removed so as to expose the source/drain diffusion layers 24 , 26 of the peripheral transistor to the outside, as shown in FIGS. 1A and 1B.
  • a film of a metal having a high melting point such as Co (cobalt), Ti (titanium) or Ni (nickel) is deposited to cover the second conductive layers 18 a , 18 b , 18 c , the buried insulating film 22 a , the side wall insulating film 22 b and the source/drain diffusion layers 24 , 26 , followed by applying annealing to the film of the high melting point metal so as to carry out the reaction between the metal having a high melting point and silicon.
  • a metal having a high melting point such as Co (cobalt), Ti (titanium) or Ni (nickel
  • the salicide films 27 a , 27 b , 27 c are formed on the second conductive layer 18 a of the memory cell region, on the second conductive layers 18 b , 18 c of the peripheral circuit region, and on the source/drain diffusion layers 24 , 26 , respectively.
  • the unreacted film of the high melting point metal is removed.
  • the memory transistor 28 in which a salicide film is not formed on the diffusion layer 21 is formed in the memory cell region, and the NMOS transistor 29 and the PMOS transistor 30 in which the salicide films 27 c are formed on the diffusion layers 24 , 26 are formed in the peripheral circuit region.
  • a known technology is employed for depositing an interlayer insulating film (not shown) on the gate electrode, for forming a contact (not shown) consisting of, for example, tungsten (W) within the interlayer insulating film, and for forming a wiring layer (not shown) connected to the contact.
  • the memory transistor 28 it is possible for the memory transistor 28 to be of P-type. In this case, an impurity is introduced into the first and second electrode material layers 13 , 18 of the memory transistor 28 simultaneously with the introduction of an impurity into the first and second electrode material layers 13 , 18 of, for example, the PMOS transistor 30 .
  • the diffusion layers 24 , 26 of the peripheral transistors 29 , 30 can be of an LDD (Lightly Doped Drain) structure or of a DDD (Double Diffused Drain) structure.
  • LDD Lightly Doped Drain
  • DDD Double Diffused Drain
  • FIGS. 12A and 12B It is possible to omit the etch back step shown in FIGS. 12A and 12B.
  • the ion implantation and activating step shown in FIGS. 13A, 13B and 14 A, 14 B is carried out.
  • the buried insulating film 22 a is formed in the clearance between the gates of the memory transistor, with the result that a salicide film is not formed on the diffusion layer 21 and the floating gate of the memory transistor 28 .
  • the characteristics of the memory cell region as a flash memory are not affected by the salicide film formation so as to make it possible to prevent the reliability in the device characteristics of the memory transistor 28 from being lowered by the salicide film formation.
  • the salicide films 27 b , 27 c are formed on the gate and on the diffusion layers 24 , 26 in the peripheral transistors 29 , 30 , respectively.
  • the lowered resistance in each of the gate and the diffusion layers 24 , 26 of the peripheral transistors 29 , 30 controls the delay of the gate and the attenuation of the driving current so as to contribute to the improvement in the performance of the circuit.
  • the lowered resistance in the control gate of the memory transistor 28 permits controlling the voltage drop caused by the resistance of the control gate.
  • the number of divisions of the array can be decreased so as to markedly contribute to the miniaturization of the chip area.
  • the controllability of the cell device can be improved by stabilizing the voltage of the control gate.
  • the salicide film 27 d is not formed on the source/drain diffusion layers 21 in the memory cell region. As a result, even in the case where both the electrode material layer formation and the device operation are to be satisfied, it is possible to avoid the problem that the degree of freedom in the element design of the memory cell is markedly limited.
  • the separation of the first electrode layer 13 is self-aligned with the formation of the element separating region shown in FIGS. 3A, 3B so as to make it possible to miniaturize the cell size.
  • the first embodiment of the present invention makes it possible to manufacture a NAND type flash memory by employing the salicide technology that is typically employed in many cases in the manufacture of a system LSI.
  • the first embodiment of the present invention is highly effective for the manufacture of a mixed chip including a flash memory and a system LSI and requiring high performance and high functionality of the element such as high speed operability of the peripheral control circuit, low power consumption and low driving voltage.
  • the second embodiment is directed to an example that an insulating film having an open portion is formed in the clearance between the first and second conductive layers of the peripheral transistor included in the semiconductor memory device according to the first embodiment of the present invention described above.
  • FIGS. 15A and 15B are cross sectional views collectively showing the construction of a semiconductor memory device according to the second embodiment of the present invention.
  • the semiconductor memory device according to the second embodiment differs from the semiconductor memory device according to the first embodiment in that, in the second embodiment, an insulating film 17 having an open portion is formed between the first conductive layer 13 b and the second conductive layer 18 b included in the peripheral transistor 29 and between the first conductive layer 13 c and the second conductive layer 18 c included in the peripheral transistor 30 .
  • the insulating film 17 is formed simultaneously with formation of the insulating film 17 formed between the first conductive layer 13 a and the second conductive layer 18 a included in the memory transistor 28 .
  • the material of the insulating film 17 formed in each of the peripheral transistors 29 , 30 is equal to that of the insulating film 17 formed in the memory transistor 28 . It is desirable for the open portion 31 of the insulating film 17 to be arranged in the center between the first conductive layer 13 b and the second conductive layer 18 b and in the center between the first conductive layer 13 c and the second conductive layer 18 c .
  • the open portions 31 of the insulating films 17 are intended to permit the first conductive layers 13 b , 13 c to be electrically connected to the second conductive layers 18 b , 18 c , respectively.
  • the number and shape of the open portions 31 are not particularly limited as far as the first conductive layers 13 b , 13 c are electrically connected to the second conductive layers 18 b , 18 c , respectively. It is also possible to form a plurality of open portions 31 in the insulating film 17 .
  • FIGS. 16A, 16B to 21 A, 21 B are cross sectional views collectively showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.
  • the manufacturing method of the semiconductor memory device according to the second embodiment of the present invention will now be described with reference to FIGS. 16A, 16B to 21 A, 21 B.
  • the manufacturing steps similar to those in the manufacturing process of the semiconductor memory device according to the first embodiment will be described briefly such that an emphasis is placed on the manufacturing steps differing from those in the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.
  • a first conductive layer 13 a is formed in the memory cell region as in the first embodiment, as shown in FIGS. 2A, 2B to SA, SB.
  • a third insulating film 17 consisting of, for example, an ONO film is deposited to cover the first electrode material layer 13 , the first conductive layer 13 a and the insulating film 15 for the element separation. Then, the third insulating film 17 in the peripheral circuit region is selectively removed so as to form the open portion 31 .
  • a second electrode material layer 18 is deposited so as to cover the third insulating film 17 , the first electrode material layer 13 , the first conductive layer 13 a and the insulating film 15 for the element separation, as shown in FIGS. 17A and 17B.
  • the second electrode material layer 18 is formed of polysilicon into which an impurity is not introduced.
  • a resist layer 19 is formed on the second electrode material layer 18 , followed by pattering the resist layer 19 , as shown in FIGS. 18A and 18B. Then, the first and second electrode material layers 13 , 18 , the third insulating film 17 and the first conductive layer 13 a are selectively removed by using the patterned resist layer 19 as a mask, thereby forming gate patterns of the memory transistor and the peripheral transistors.
  • the resist layer 19 is removed, followed by a post-oxidation so as to form an oxide film (not shown) on the gate, as shown in FIGS. 19A, 19B.
  • a resist layer 20 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 20 , as shown in FIGS. 20A and 20B.
  • ion implantation is performed by using the patterned resist layer 20 as a mask so as to form N + -type source/drain diffusion layers 21 in the memory cell region of the semiconductor substrate 11 , followed by removing the resist layer 20 .
  • a fourth insulating film 22 is formed to cover the first insulating film 12 and the second electrode material layer 18 in a manner to satisfy the relationship given by formula (1) referred previously, as shown in FIGS. 21A and 21B.
  • the fourth insulating film 22 is etched back so as to expose the surfaces of the second electrode material layer 18 and the first insulating film 12 or the surfaces of the diffusion layer regions of the peripheral transistors, as shown in FIGS. 22A and 22 B.
  • a buried insulating film 22 a is formed in the clearance between the gate electrodes in the memory cell region, and a side wall insulating film 22 b is formed on the side surface of the gate electrode in the peripheral circuit region.
  • a resist layer 23 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 23 , as shown in FIGS. 23A and 23B. Further, ion implantation is performed by using, for example, arsenic (As) ions as an impurity, with the patterned resist layer 23 used as a mask, followed by applying annealing to the ion-implanted regions. As a result, the introduced impurity is diffused so as to form a second conductive layer 18 a in the memory cell region and to form the first and second conductive layers 13 b , 18 b , and the N + -type source/drain diffusion layers 24 in the NMOS region.
  • As arsenic
  • the impurity introduced into the second electrode material layer 18 of the NMOS region is diffused through the open portion 31 of the third insulating film 17 into the first electrode material 13 of the NMOS region so as to form the first conductive layer 13 b in the NMOS region. Then, the resist layer 23 is removed.
  • a resist layer 25 is formed to cover the first insulating film 12 and the second electrode material layer 19 , followed by patterning the resist layer 25 , as shown in FIGS. 24A and 24B. Then, ion implantation is performed by using, for example, boron (B) as an impurity, with the patterned resist layer 25 used as a mask. The introduced impurity is diffused by annealing so as to form the first and second conductive layers 13 c , 18 c and the P + -type source/drain diffusion layers 26 in the PMOS region.
  • the impurity introduced into the second electrode material layer 18 of the PMOS region is diffused through the open portion 31 of the third insulating film 17 into the first electrode material layer 13 of the PMOS region so as to form the first conductive layer 13 c of the PMOS region. Then, the resist layer 25 is removed.
  • the salicide films 27 a , 27 b , 27 c are formed to cover the second conductive layer 18 a in the memory cell region, the second conductive layers 18 b , 18 c in the peripheral circuit region, and the source/drain diffusion layers 24 , 26 of the peripheral circuit region, respectively, as shown in FIGS. 15A and 15B.
  • the third insulating films 17 each having the open portion 31 are formed between the first conductive layer 13 b and the second conductive layer 18 b in the peripheral transistor 29 and between the first conductive layer 13 c and the second conductive layer 18 c in the peripheral transistor 30 . It follows that the edge portion of the gate electrode in the NMOS region is of a three-layer structure including the first conductive layer 13 b , the second conductive layer 18 b and the third insulating film 17 interposed between the first and second conductive layers 13 b and 18 b .
  • the edge portion of the gate electrode in the PMOS region is of a three-layer structure including the first conductive layer 13 c , the second conductive layer 18 c and the third insulating film 17 interposed between the first and second conductive layers 13 c and 18 c .
  • the gate electrode in the memory cell transistor is of a three-layer structure including the first conductive layer 13 a , the second conductive layer 18 a and the third insulating film 17 interposed between the first and second conductive layers 13 a and 18 a . It follows that, concerning the edge portion of the gate electrode to which is applied the gate processing, the peripheral transistors 29 , 30 and the memory transistor 28 are equal to each other in the laminate structure of the gate. It follows that the gate processing can be applied simultaneously to the memory transistor 28 and the peripheral transistors 29 , 30 without changing the etching conditions.
  • the third embodiment which is equal in construction to the second embodiment described above, differs from the second embodiment in that, in the third embodiment, the first electrode material in the memory transistor and the first electrode material in the peripheral transistor, which is equal in the conductivity type to the memory transistor, are rendered conductive simultaneously.
  • FIGS. 25A, 25B to 35 A, 35 B are cross sectional views collectively showing the manufacturing process of a semiconductor memory device according to a third embodiment of the present invention.
  • the manufacturing method of the semiconductor memory device according to the third embodiment of the present invention will now be described with reference to FIGS. 25A, 25B to 35 A, 35 B.
  • the manufacturing steps equal to those in the manufacturing process of the semiconductor memory device according to the first and second embodiments of the present invention will be omitted, and the manufacturing steps differing from those in the first and second embodiments will be described.
  • a first electrode material layer 13 is formed on a first insulating film 12 , followed by forming an insulating film 15 for the element separation as shown in FIGS. 2A, 2B to 4 A, 4 B, as in the first embodiment.
  • a resist layer 16 a is formed on the first electrode material layer 13 , followed by patterning the resist layer 16 a such that the resist layer 16 a is left unremoved on the PMOS region alone, as shown in FIGS. 25A and 25B. Then, ion implantation is performed for implanting impurity ions into the first electrode material layer 13 in the memory cell region and the NMOS region by using the patterned resist layer 16 a as a mask, followed by applying annealing to the first electrode material layer 13 so as to form first conductive layers 13 a , 13 b .
  • the ion implantation is carried out by using, for example, phosphorus (P) as an impurity under the conditions that the accelerating energy is set at scores of KeV and the dose of the impurity is set at about 10 15 cm ⁇ 2 .
  • the reference numeral 13 a shown in FIGS. 25A, 25B denotes the first conductive layer in the memory cell region
  • the reference numeral 13 b shown in FIGS. 25A, 25B denotes the first conductive layer in the NMOS region. Then, the resist layer 16 a is removed.
  • a resist layer 16 b is formed to cover the first electrode material layer 13 and the first conductive layers 13 a , 13 b , followed by patterning the resist layer 16 b such that the resist layer 16 b is left unremoved on only the memory cell region and the NMOS region. Then, impurity ions are introduced into the first electrode material layer 13 of the PMOS region by ion implantation with the patterned resist layer 16 b used as a mask, followed by applying annealing to the first electrode material layer 13 so as to form a first conductive layer 13 c .
  • boron (B) for example, is used as a P-type impurity, and the ion implantation is carried out under the conditions that the accelerating energy is set at scores of KeV and the dose of the impurity is set at about 10 15 cm ⁇ 2 . Then, the resist layer 16 b is removed.
  • a third insulating film 17 consisting of, for example, an ONO film is deposited to cover the first conductive layers 13 a , 13 b , 13 c and the insulating film 15 for the element separation, as shown in FIGS. 27A and 27B. Then, the third insulating film 17 in the peripheral circuit region is selectively removed so as to form an open portion 31 .
  • a second electrode material layer 18 is deposited in a manner to cover the third insulating film 17 , the first conductive layers 13 b , 13 c and the insulating film 15 for the element separation, as shown in FIGS. 28A and 28B.
  • the second electrode material layer 18 is formed of polysilicon into which an impurity is not introduced.
  • a resist layer 19 is formed on the second electrode material layer 18 , followed by patterning the resist layer 18 , as shown in FIGS. 29A, 29B. Further, the second electrode material layer 18 , the third insulating film 17 and the first conductive layers 13 a , 13 b , 13 c are selectively removed by using the patterned resist layer 19 as a mask, thereby forming gate patterns for the memory transistor and the peripheral transistors.
  • the patterned resist layer 19 is removed as shown in FIGS. 30A and 30B, followed by applying a post-oxidation so as to form an oxide film (not shown) on the gate.
  • a resist layer 20 is formed in a manner to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 20 , as shown in FIGS. 31A and 31B.
  • ion implantation is carried out by using the patterned resist layer 20 as a mask so as to form N + -type source/drain diffusion layers 21 in the semiconductor substrate 11 in the memory cell region, followed by removing the patterned resist layer 20 .
  • a fourth insulating film 22 is formed to cover the first insulating film 12 and the second electrode material layer 18 in a manner to satisfy the relationship given by formula (1) referred to previously. Then, the fourth insulating film 22 is etched back so as to expose the surfaces of the second electrode material layer 18 and the first insulating film 12 or the surface of the diffusion layer region of the peripheral transistor to the outside, as shown in FIGS. 33A and 33B. As a result, a buried insulating film 22 a is formed in the clearance between the gate electrodes in the memory cell region, and a side wall insulating film 22 b is formed on the side surface of the gate electrode in the peripheral circuit region.
  • a resist layer 23 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 23 such that the resist layer 23 is left unremoved on the PMOS region, as shown in FIGS. 34A and 34B.
  • an impurity of, for example, arsenic (As) is introduced into the second electrode material layer 18 by means of ion implantation with the patterned resist film 23 used as a mask, followed by applying annealing to the introduced impurity so as to diffuse the impurity.
  • a second conductive layer 18 a is formed in the memory cell region, and a second conductive layer 18 b and N + -type source/drain diffusion layers 24 are formed in the NMOS region. Then, the patterned resist layer 23 is removed.
  • a resist layer 25 is formed to cover the first insulating film 12 and the second electrode material layer 18 , followed by patterning the resist layer 25 such that the resist layer 25 is left unremoved on the memory cell region and the NMOS region, as shown in FIGS. 35A and 35B. Then, ion implantation using, for example, boron (B) as an impurity is performed by using the patterned resist layer 25 as a mask, followed by applying annealing to the introduced impurity so as to diffuse the impurity. As a result, a second conductive layer 18 c and P + -type source/drain diffusion layers 26 are formed in the PMOS region. Then, the patterned resist layer 25 is removed.
  • the salicide films 27 a , 27 b , 27 c are formed on the second conductive layer 18 a in the memory cell region, on the second conductive layers 18 b , 18 c in the peripheral circuit region, and on the source/drain diffusion layers 24 , 26 in the peripheral circuit region, respectively, as in the second embodiment described previously.
  • the first electrode material layers 13 in the memory transistor 28 and the peripheral transistor 29 are simultaneously rendered conductive. It follows that the number of manufacturing process steps can be decreased, and the semiconductor memory device can be manufactured easily.
  • the memory transistor 28 is of P-type, it is desirable to render conductive the first electrode material layer 13 in the memory cell region simultaneously in the step of rendering conductive the first electrode material layer 13 in the PMOS region.
  • the fourth embodiment which is equal in construction to the third embodiment described above, differs from the third embodiment in that, in the fourth embodiment, a conductive material is used in forming first the first electrode material layer.
  • FIGS. 36A, 36B to 39 A, 39 B are cross sectional views collectively showing the manufacturing process of a semiconductor memory device according to the fourth embodiment of the present invention.
  • the manufacturing method of the semiconductor memory device according to the fourth embodiment of the present invention will now be described with reference of FIGS. 36A, 36B to 39 A, 39 B.
  • the manufacturing steps equal to those in the manufacturing process of the semiconductor memory device according to the third embodiment of the present invention will be omitted, and the manufacturing steps differing from those in the third embodiment will be described.
  • a first insulating film 12 forming a gate insulating film is formed on a semiconductor substrate 11 , as shown in FIGS. 36A and 36B. Then, an N + -type first conductive layer 41 into which an impurity has been introduced is formed on the first insulating film 12 , followed by depositing a second insulating film 14 consisting of silicon nitride on the first conductive layer 41 .
  • the second insulating film 14 , the first conductive layer 41 , the first insulating film 12 and the semiconductor substrate 11 are selectively removed so as to form a groove for the element separation, as shown in FIGS. 37A and 37B.
  • an insulating film 15 for the element separation consisting of a silicon oxide film is deposited to fill the groove for the element separation, followed by planarizing the insulating film 15 for the element separation until the surface of the second insulating film 14 is exposed to the outside, thereby forming an element separating region of an STI structure consisting of the insulating film 15 for the element separation.
  • the element separation insulating film 15 is partly etched so as to permit the surface of the element separating insulating film 15 to be positioned lower than the surface of the first conductive layer 41 , followed by peeling off the second insulating film 14 , as shown in FIGS. 38A and 38B.
  • a resist layer 16 is formed on the first conductive layer 41 , followed by patterning the resist layer 16 such that the resist layer 16 is left unremoved on only the memory cell region and the NMOS region.
  • ion implantation is applied to the first conductive layer 41 in the PMOS region with the patterned resist 16 used as a mask, followed by applying annealing so as to form a P + -type first conductive layer 42 .
  • boron (B) for example, is used as a P-type impurity, and the ion implantation is carried out under the conditions that the accelerating energy is set at scores of KeV and the dose of the impurity is set at about 10 15 cm ⁇ 2 .
  • the dose of the impurity in the process step shown in FIGS. 39A, 39B is about twice as high as the dose of the impurity in the first conductive layer 41 . Then, the patterned resist layer 16 is removed.
  • the fifth embodiment is directed to an example of a semiconductor memory device in which a selecting transistor controlling a memory transistor is arranged in the vicinity of the memory transistor.
  • FIGS. 40A, 40B, 41 A and 41 B are cross sectional views each showing the construction of a semiconductor memory device according to the fifth embodiment of the present invention.
  • FIGS. 40A, 40B shows the construction in the case where an insulating film is not formed in the clearance between the first and second conductive layers of the selecting transistor.
  • FIGS. 41A, 41B shows the construction in the case where an insulating film having an open portion is formed in the clearance between the first and second conductive layers of the selecting transistor.
  • the semiconductor memory device according to the fifth embodiment will now be described with reference to FIGS. 40A, 40B, 41 A and 41 B. Concerning the semiconductor memory device according to the fifth embodiment, the description of the construction similar to that of the semiconductor memory device according to any of the first to fourth embodiments described above is omitted and the differing construction alone will be described.
  • a selecting transistor is arranged in the vicinity of the memory transistor in the semiconductor memory device according to the fifth embodiment of the present invention.
  • an insulating film 22 a is formed between the adjacent gates so as to cover the surface of a diffusion layer 21 . Therefore, a salicide film 27 a is formed on each of the gates. However, a salicide film is not formed on the diffusion layer 21 .
  • it is desirable for the gate of the memory transistor and the gate of the selecting transistor to be arranged apart from each other by the first distance X referred to previously.
  • the sixth embodiment is directed to an example that, in forming a PMOS transistor comprising a P-type first conductive layer and an N-type second conductive layer, an electrode material into which an impurity is not injected is used for forming the first conductive layer.
  • FIGS. 42 and 43 are cross sectional views collectively showing a semiconductor memory device according to the sixth embodiment of the present invention. Specifically, FIG. 42 is a cross sectional view perpendicular to the element separating region of the memory cell region. On the other hand, FIG. 43 is a cross sectional view perpendicular to the gate electrode of the memory cell region.
  • the semiconductor memory device comprises a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region.
  • a PMOS transistor 125 in the PMOS region includes P + -type first and second conductive layers 113 c , 116 c formed on a semiconductor substrate 111 , an insulating film 119 having an open portion 120 and formed on the second conductive layer 116 c , and an N + -type third conductive layer 121 c formed on the insulating film 119 and the second conductive layer 116 c .
  • an NMOS transistor 124 in the NMOS region includes N + -type first and second conductive layers 113 b , 116 b formed on the semiconductor substrate 111 , an insulating film 119 having an open portion 120 and formed on the second conductive layer 116 b , and an N + -type third conductive layer 121 b formed on the insulating film 119 and the second conductive layer 116 b .
  • a memory transistor 123 in the memory region includes N + -type first and second conductive layers 113 a , 116 a formed on the semiconductor substrate 111 , an insulating film 119 formed on the second conductive layer 116 a , and an N + -type third conductive layer 121 a formed on the insulating film 119 .
  • the insulating film 119 In the peripheral circuit region described above, it suffices for the insulating film 119 to be present in only the edge portions between the second conductive layer 116 b and the third conductive layer 121 b and between the second conductive layer 116 c and the third conductive layer 121 c . Therefore, it is desirable for the open portion 120 of the insulating film 119 to be positioned in the centers between the second conductive layer 116 b and the third conductive layer 121 b and between the second conductive layer 116 c and the third conductive layer 121 c .
  • the open portion 120 of the insulating film 119 is intended to permit the first and second conductive layers 113 b , 116 b to be electrically connected to the third conductive layer 121 b , and to permit the first and second conductive layers 113 c , 116 c to be electrically connected to the third conductive layer 121 c . Therefore, the number of the open portions 120 and the shape of the open portion 120 are not particularly limited as far as the first conductive layers 113 b , 113 c and the second conductive layers 116 b , 116 b can be electrically connected to the third conductive layers 121 b , 121 c , respectively. Also, it is possible to form a plurality of open portions 120 . Further, it is possible to remove all the insulating films 119 in the peripheral circuit region.
  • the first and second conductive layers 113 a , 116 a perform the function of a floating gate of the memory transistor 123
  • the third conductive layer 121 a performs the function of a control gate of the memory transistor 123 .
  • a PMOS transistor includes a P-type conductive layer.
  • the third conductive layer 121 c of the PMOS transistor 125 according to the sixth embodiment of the present invention is formed of an N + -type conductive layer. Therefore, in order to allow the third conductive layer 121 c to perform sufficiently the function of the gate of the PMOS transistor 125 , it is desirable for each of the first to third conductive layers 113 a , 113 b , 113 c , 116 a , 116 b , 116 c , 121 a , 121 b and 121 b to have an impurity concentration not lower than 1 ⁇ 10 18 cm ⁇ 3 .
  • the third conductive layers 121 b , 121 c in the NMOS region and the PMOS region are of the same conductivity type (N + ), as shown in FIG. 42. Therefore, the third conductive layer 121 b of the NMOS transistor 124 need not be separated from the third conductive layer 121 c of the PMOS transistor 125 on the element separating insulating film 115 . In other words, the third conductive layer 121 b and the third conductive layer 121 c are formed contiguous on the element separating insulating film 115 .
  • FIGS. 44 to 51 are cross sectional views collectively showing the manufacturing process of the semiconductor memory device according to the sixth embodiment of the present invention. The manufacturing process of the semiconductor memory device according to the sixth embodiment will now be described with reference to FIGS. 44 to 51 .
  • a first insulating film 112 forming a gate insulating film is formed on a semiconductor substrate 111 , followed by forming a first electrode material layer 113 on the first insulating film 112 , as shown in FIG. 44.
  • the first electrode material layer 113 is formed of polysilicon into which an impurity is not introduced.
  • a second insulating film 114 such as a silicon nitride film is deposited on the first electrode material layer 113 .
  • the second insulating film 114 , the first electrode material layer 113 , the first insulating film 112 and the semiconductor substrate 111 are selectively removed so as to form a groove for the element separation, as shown in FIG. 45.
  • an element separating insulating film 115 such as an oxide film is deposited within the element separating groove, followed by planarizing the element separating insulating film 115 until the surface of the second insulating film 114 is exposed to the outside.
  • the second insulating film 114 performs the function of a stopper film in planarizing the element separating insulating film 115 .
  • an element separating region of an STI (Shallow Trench Isolation) structure consisting of the element separating insulating film 115 is formed.
  • the second insulating film 114 is peeled off.
  • a second electrode material layer 116 consisting of polysilicon into which an impurity is not injected is formed to cover the first electrode material layer 113 and the element separating insulating film 115 , followed by removing the second electrode material layer 116 until the surface of the element separating insulating film 115 is exposed to the outside.
  • a resist layer 117 is formed to cover the second electrode material layer 116 and the element separating insulating film 115 , followed by patterning the resist layer 117 such that the resist layer 117 is left unremoved on the PMOS regions alone, as shown in FIG. 47.
  • ion implantation is applied to the second electrode material layer 116 in the memory cell region and the NMOS region by using the patterned resist layer 117 as a mask.
  • arsenic (As) or phosphorus (P) is used as an N-type impurity.
  • annealing is applied so as to allow the impurity implanted into the second electrode material layer 116 to be diffused into the first electrode material layer 113 , thereby forming N + -type first conductive layers 113 a , 113 b and second conductive layers 116 a , 116 b . Then, the patterned resist layer 117 is removed.
  • a resist layer 118 is formed to cover the second conductive layers 116 a , 116 b and the element separating insulating film 115 , followed by patterning the resist layer 118 such that the patterned resist layer 118 is left unremoved on only the memory cell region and the NMOS regions, as shown in FIG. 48.
  • ion implantation is applied to the second electrode material layer 116 in the PMOS region by using the patterned resist layer 118 as a mask.
  • boron (B) for example, is used as a P-type impurity.
  • annealing is applied so as to allow the impurity implanted into the second electrode material layer 116 to be diffused into the first electrode material layer 113 , thereby forming P + -type first conductive layer 113 c and second conductive layer 116 c . Then, the patterned resist layer 118 is removed.
  • a third insulating film 119 is deposited to cover the second conductive layers 116 a , 116 b , 116 c and the element separating insulating film 115 , as shown in FIG. 49. Then, the third insulating film 119 in the peripheral circuit region is partly removed so as to form an open portion 120 , as shown in FIG. 50. Incidentally, it is possible to remove entirely the third insulating film 119 in the peripheral circuit region in this step. However, it is desirable to form the open portion 120 so as to permit the third insulating film 119 to remain in the peripheral circuit region, too.
  • a third insulating material layer 121 is deposited to cover the third insulating film 119 and the second conductive layers 116 b , 116 c , as shown in FIG. 51. It should be noted that the third insulating material layer 121 is formed of polysilicon having an N-type impurity implanted thereinto. Then, a metal film 122 consisting of, for example, tungsten silicide (WSi) is formed on the third electrode material layer 121 .
  • WSi tungsten silicide
  • the metal film 122 and the third electrode material layer 121 are selectively removed, as shown in FIGS. 42 and 43, thereby forming the gate patterns of the memory transistor 123 and the peripheral transistors 124 , 125 .
  • FIG. 52 is a graph showing the I-V characteristics of the semiconductor memory device according to the sixth embodiment of the present invention in comparison with the prior art.
  • the I-V characteristics between the P + -gate consisting of the first and second conductive layers 113 c , 116 c in the PMOS transistor 125 and the N + -type gate consisting of the third conductive layer 121 c in the PMOS transistor 125 are evaluated.
  • substantially linear I-V characteristics which is satisfactory, like the prior art, were obtained as shown in FIG. 52.
  • the PMOS transistor 125 includes the P + -type gate and the N + -type gate as in the sixth embodiment, a PN junction is not formed so as to perform sufficiently the function of the gate.
  • a logic circuit having a power source voltage not higher than 1.8 V can be driven directly without internally boosting the CMOS circuit so as to make it possible to lower the power source voltage without increasing the number of circuit elements.
  • the sixth embodiment of the present invention it is possible to form the gate of the NMOS transistor 124 and the gate of the PMOS transistor 125 by using the third electrode material layers 121 of the same conductivity type. In other words, it is unnecessary to implant different impurities by using the light exposure technology for forming the gate of the NMOS transistor 124 and the gate of the PMOS transistor 125 . It follows that a CMOS transistor of the dual word function gate can be manufactured easily.
  • the third electrode material layers 121 of the NMOS and PMOS transistor 124 , 125 as a control gate of the memory transistor 123 without implanting different impurities so as to further facilitate the manufacturing process of the semiconductor memory device.
  • the third insulating film 119 having the open portion 120 is formed between the second conductive layer 116 b and the third conductive layer 121 b and between the second conductive layer 116 c and the third conductive layer 121 c .
  • the edge portion of the gate electrode is of a three-layer structure including the second conductive layer 116 b , the third conductive layer 121 b and the third insulating film 119 interposed between the second and third conductive layers 116 b and 121 b , or of a three-layer structure including the second conductive layer 116 c , the third conductive layer 121 c and the third insulating film 119 interposed between the second and third conductive layers 116 c and 121 c .
  • the gate electrode is of a three-layer structure including the second conductive layer 116 a , the third conductive layer 121 a , and the third insulating film 119 interposed between the second and third conductive layers 116 a and 121 a over the entire regions of the second and third conductive layers 116 a and 121 a . It follows that, concerning the edge portion of the gate electrode to which is applied the gate processing, the gates of the peripheral transistors 124 , 125 and the memory transistor 123 have the same laminate structure. It follows that the gate processing can be performed simultaneously without changing the etching conditions for the memory transistor 123 and the peripheral transistors 124 , 125 .
  • the first electrode material layer 113 can be separated in a self-aligned fashion in forming the element separating region as shown in FIG. 45. It follows that the minimum cell size that can be defined by the minimum size can be realized so as to make it possible to miniaturize the cell size.
  • the present invention is highly effective for a system LSI (logic embedded memory) having a nonvolatile memory and a logic device of high performance peripheral circuit elements mounted together.
  • the seventh embodiment of the present invention is directed to an example that, in forming the PMOS transistor including a P-type first conductive layer and an N-type second conductive layer, an electrode material having an impurity introduced therein is used for forming the first conductive layer.
  • the semiconductor memory device according to the seventh embodiment is equal in the final construction to the semiconductor memory device according to the sixth embodiment. Therefore, the description on the construction of the semiconductor memory device is omitted.
  • FIGS. 53 to 57 are cross sectional views collectively showing the manufacturing process of the semiconductor memory device according to the seventh embodiment of the present invention.
  • the manufacturing process of the semiconductor memory device according to the seventh embodiment will now be described with reference to FIGS. 53 to 57 .
  • the process steps equal to those of the manufacturing process of the semiconductor memory device according to the sixth embodiment will be described briefly, and the differing process steps alone will be described in detail.
  • a first insulating film 112 forming a gate insulating film is formed on a semiconductor substrate 111 , followed by forming a first electrode material layer 131 on the first insulating film 112 , as shown in FIG. 53.
  • the first electrode material layer 131 is formed of polysilicon having an N-type impurity such as phosphorus (P) or arsenic (As) introduced therein.
  • a second insulating film 114 consisting of, for example, a silicon nitride film is deposited on the first electrode material layer 131 .
  • the second insulating film 114 , the first electrode material layer 131 , the first insulating film 112 and the semiconductor substrate 111 are selectively removed so as to form grooves for the element separation, as shown in FIG. 54.
  • an element separating insulating film 115 consisting of, for example, an oxide film is formed to fill the grooves for the element separation, followed by planarizing the element separating insulating film 115 until the surface of the second insulating film 114 is exposed to the outside, thereby forming an element separating region of an STI structure consisting of the element separating insulating film 115 .
  • the second insulating film 114 is peeled off.
  • a second electrode material layer 116 consisting of polysilicon into which an impurity is not introduced is formed to cover the first electrode material layer 131 and the element separating insulating film 115 , as shown in FIG. 55, followed by removing the second electrode material layer 116 until the surface of the element separating insulating film 115 is exposed to the outside.
  • a resist layer 117 is formed to cover the second electrode material layer 116 and the element separating insulating film 115 , followed by patterning the resist layer 117 such that the resist layer 117 is left unremoved on the PMOS region alone, as shown in FIG. 56. Then, annealing is applied by using the patterned resist layer 117 as a mask, thereby allowing the impurity contained in the first electrode material layer 131 to be diffused into the second electrode material layer so as to form N + -type first conductive layers 131 a , 131 b and second conductive layers 116 a , 116 b . Further, the patterned resist layer 117 is removed.
  • a resist layer 118 is formed to cover the second conductive layers 116 a , 116 b and the element separating insulating film 115 , followed by patterning the resist layer 118 such that the resist layer 118 is left unremoved on the memory cell region and the NMOS region, as shown in FIG. 57. Then, ion implantation is applied to the second electrode material layer 116 in the PMOS region by using the patterned resist layer 118 as a mask. The ion implantation is performed by using, for example, boron (B) as a P-type impurity.
  • B boron
  • annealing is applied so as to permit the impurity implanted into the second electrode material layer 116 to be diffused into the first electrode material layer 131 , thereby forming P + -type first conductive layer 131 c and second conductive layer 116 c . Then, the patterned resist layer 118 is removed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
US10/214,582 2001-08-10 2002-08-09 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same Abandoned US20030030123A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/891,133 US7067872B2 (en) 2001-08-10 2004-07-15 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
US11/434,059 US7563664B2 (en) 2001-08-10 2006-05-16 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001-244557 2001-08-10
JP2001-244558 2001-08-10
JP2001244558A JP4309078B2 (ja) 2001-08-10 2001-08-10 半導体装置及びその製造方法
JP2001244557A JP4266089B2 (ja) 2001-08-10 2001-08-10 半導体記憶装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/891,133 Division US7067872B2 (en) 2001-08-10 2004-07-15 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20030030123A1 true US20030030123A1 (en) 2003-02-13

Family

ID=26620425

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/214,582 Abandoned US20030030123A1 (en) 2001-08-10 2002-08-09 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
US10/891,133 Expired - Fee Related US7067872B2 (en) 2001-08-10 2004-07-15 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
US11/434,059 Expired - Fee Related US7563664B2 (en) 2001-08-10 2006-05-16 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/891,133 Expired - Fee Related US7067872B2 (en) 2001-08-10 2004-07-15 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
US11/434,059 Expired - Fee Related US7563664B2 (en) 2001-08-10 2006-05-16 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same

Country Status (2)

Country Link
US (3) US20030030123A1 (ko)
KR (1) KR100600681B1 (ko)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050139904A1 (en) * 2003-12-26 2005-06-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20050157536A1 (en) * 2003-12-01 2005-07-21 Kabushiki Kaisha Toshiba Semiconductor device including nonvolatile memory and method of fabricating the same
US20060197226A1 (en) * 2000-09-26 2006-09-07 Michiharu Matsui Nonvolatile semiconductor memory device having element isolating region of trench type
US20060285375A1 (en) * 2005-06-16 2006-12-21 Kabushiki Kaisha Toshiba Semiconductor memory and method for manufacturing the semiconductor memory
US20070018235A1 (en) * 2003-02-26 2007-01-25 Fumitaka Arai Nonvolatile semiconductor memory device including improved gate electrode
US20080087935A1 (en) * 2006-09-29 2008-04-17 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20220123000A1 (en) * 2020-10-16 2022-04-21 Renesas Electronics Corporation Method of manufacturing semiconductor device
US12137556B2 (en) * 2020-10-16 2024-11-05 Renesas Electronics Corporation Method of manufacturing semiconductor device with improved gate insulation step

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2267784B1 (en) * 2001-07-24 2020-04-29 Cree, Inc. INSULATING GATE AlGaN/GaN HEMT
KR100702307B1 (ko) * 2004-07-29 2007-03-30 주식회사 하이닉스반도체 반도체 소자의 디램 및 그 제조 방법
US20060223267A1 (en) * 2005-03-31 2006-10-05 Stefan Machill Method of production of charge-trapping memory devices
KR100674800B1 (ko) * 2005-04-07 2007-01-26 매그나칩 반도체 유한회사 반도체 소자의 제조방법
KR100669353B1 (ko) * 2005-10-14 2007-01-16 삼성전자주식회사 비휘발성 기억소자 및 그 형성방법
JP2007335750A (ja) * 2006-06-16 2007-12-27 Toshiba Corp 半導体記憶装置
US20080003745A1 (en) * 2006-06-30 2008-01-03 Hynix Semiconductor Inc. Method of manufacturing a flash memory device
JP4364225B2 (ja) * 2006-09-15 2009-11-11 株式会社東芝 半導体装置およびその製造方法
JP2008159614A (ja) * 2006-12-20 2008-07-10 Toshiba Corp 不揮発性半導体メモリ
JP5118341B2 (ja) * 2006-12-22 2013-01-16 株式会社東芝 半導体記憶装置及びその製造方法
US7948021B2 (en) * 2007-04-27 2011-05-24 Kabushiki Kaisha Toshiba Semiconductor memory device and method of fabricating the same
DE102008006961A1 (de) * 2008-01-31 2009-08-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen eines verformten Kanalgebiets in einem Transistor durch eine tiefe Implantation einer verformungsinduzierenden Sorte unter das Kanalgebiet
US20090194810A1 (en) * 2008-01-31 2009-08-06 Masahiro Kiyotoshi Semiconductor device using element isolation region of trench isolation structure and manufacturing method thereof
US7723777B2 (en) * 2008-08-12 2010-05-25 Infineon Technologies Ag Semiconductor device and method for making same
JP2011003833A (ja) * 2009-06-22 2011-01-06 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US20110255335A1 (en) * 2010-04-20 2011-10-20 Alessandro Grossi Charge trap memory having limited charge diffusion
KR101850093B1 (ko) 2011-02-22 2018-04-19 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9536888B2 (en) * 2014-12-23 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method to prevent oxide damage and residue contamination for memory device
US9691780B2 (en) 2015-09-25 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitor in split-gate flash technology
CN108962904B (zh) 2017-05-26 2020-07-14 华邦电子股份有限公司 半导体存储元件的制造方法
US10515977B2 (en) * 2017-07-26 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Boundary design to reduce memory array edge CMP dishing effect
DE102018117235B4 (de) 2017-07-26 2024-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Grenzbereichsentwurf zur reduzierung des cmp-vertiefungseffekts an speichermatrixrändern
JP2021068799A (ja) * 2019-10-23 2021-04-30 キオクシア株式会社 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417051B1 (en) * 1999-03-12 2002-07-09 Kabushiki Kaisha Toshiba Method of manufacturing memory device including insulated gate field effect transistors
US6420754B2 (en) * 2000-02-28 2002-07-16 Hitachi, Ltd. Semiconductor integrated circuit device
US20020149050A1 (en) * 1999-12-03 2002-10-17 Albert Fazio Integrated memory cell and method of fabrication
US6624019B2 (en) * 2000-05-30 2003-09-23 Samsung Electronics Co., Ltd. Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861650A (en) * 1996-08-09 1999-01-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising an FPGA
JPH1174371A (ja) * 1997-08-28 1999-03-16 Sony Corp 半導体装置の製造方法および半導体装置
JP3149937B2 (ja) * 1997-12-08 2001-03-26 日本電気株式会社 半導体装置およびその製造方法
US6215145B1 (en) * 1998-04-06 2001-04-10 Micron Technology, Inc. Dense SOI flash memory array structure
JP2000269366A (ja) * 1999-03-19 2000-09-29 Toshiba Corp 不揮発性半導体メモリ
KR100301816B1 (ko) * 1999-05-27 2001-09-26 김영환 반도체 소자의 실리사이드층 형성 방법
JP4774568B2 (ja) * 1999-10-01 2011-09-14 ソニー株式会社 半導体装置の製造方法
KR100567050B1 (ko) * 1999-11-19 2006-04-04 주식회사 하이닉스반도체 반도체메모리의 실리사이드 형성방법
KR100359766B1 (ko) * 1999-12-31 2002-11-07 주식회사 하이닉스반도체 반도체 소자의 제조 방법
JP2002064157A (ja) 2000-06-09 2002-02-28 Toshiba Corp 半導体メモリ集積回路及びその製造方法
JP2002176114A (ja) 2000-09-26 2002-06-21 Toshiba Corp 半導体装置及びその製造方法
JP2002280463A (ja) 2001-03-16 2002-09-27 Toshiba Corp 半導体装置及びその製造方法
JP3927156B2 (ja) 2003-02-26 2007-06-06 株式会社東芝 不揮発性半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417051B1 (en) * 1999-03-12 2002-07-09 Kabushiki Kaisha Toshiba Method of manufacturing memory device including insulated gate field effect transistors
US20020149050A1 (en) * 1999-12-03 2002-10-17 Albert Fazio Integrated memory cell and method of fabrication
US6420754B2 (en) * 2000-02-28 2002-07-16 Hitachi, Ltd. Semiconductor integrated circuit device
US6624019B2 (en) * 2000-05-30 2003-09-23 Samsung Electronics Co., Ltd. Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7573092B2 (en) 2000-09-26 2009-08-11 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having element isolating region of trench type
US20090221128A1 (en) * 2000-09-26 2009-09-03 Michiharu Matsui Nonvolatile semiconductor memory device having element isolating region of trench type
US7939406B2 (en) 2000-09-26 2011-05-10 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having element isolating region of trench type
US7538380B2 (en) 2000-09-26 2009-05-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having element isolating region of trench type
US20060197226A1 (en) * 2000-09-26 2006-09-07 Michiharu Matsui Nonvolatile semiconductor memory device having element isolating region of trench type
US20070057310A1 (en) * 2000-09-26 2007-03-15 Michiharu Matsui Nonvolatile semiconductor memory device having element isolating region of trench type
US20070057315A1 (en) * 2000-09-26 2007-03-15 Michiharu Matsui Nonvolatile semiconductor memory device having element isolating region of trench type
US7348627B2 (en) 2000-09-26 2008-03-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having element isolating region of trench type
US7521749B2 (en) 2003-02-26 2009-04-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device including improved gate electrode
US7298006B2 (en) 2003-02-26 2007-11-20 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device including improved gate electrode
US20070018235A1 (en) * 2003-02-26 2007-01-25 Fumitaka Arai Nonvolatile semiconductor memory device including improved gate electrode
US20080054340A1 (en) * 2003-02-26 2008-03-06 Fumitaka Arai Nonvolatile semiconductor memory device including improved gate electrode
US20090039412A1 (en) * 2003-12-01 2009-02-12 Kabushiki Kaisha Toshiba Semiconductor device including nonvolatile memory and method of fabricating the same
US20050157536A1 (en) * 2003-12-01 2005-07-21 Kabushiki Kaisha Toshiba Semiconductor device including nonvolatile memory and method of fabricating the same
US7405440B2 (en) 2003-12-26 2008-07-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20050139904A1 (en) * 2003-12-26 2005-06-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20060285375A1 (en) * 2005-06-16 2006-12-21 Kabushiki Kaisha Toshiba Semiconductor memory and method for manufacturing the semiconductor memory
US7795668B2 (en) * 2006-09-29 2010-09-14 Kabushiki Kaisha Toshiba Semiconductor memory device with selective gate transistor
US20080087935A1 (en) * 2006-09-29 2008-04-17 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20220123000A1 (en) * 2020-10-16 2022-04-21 Renesas Electronics Corporation Method of manufacturing semiconductor device
US12137556B2 (en) * 2020-10-16 2024-11-05 Renesas Electronics Corporation Method of manufacturing semiconductor device with improved gate insulation step

Also Published As

Publication number Publication date
US7067872B2 (en) 2006-06-27
US20060202275A1 (en) 2006-09-14
KR100600681B1 (ko) 2006-07-13
KR20030014158A (ko) 2003-02-15
US20040256650A1 (en) 2004-12-23
US7563664B2 (en) 2009-07-21

Similar Documents

Publication Publication Date Title
US7563664B2 (en) Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
US5514889A (en) Non-volatile semiconductor memory device and method for manufacturing the same
KR100583708B1 (ko) 불휘발성 메모리를 갖는 반도체 장치 및 그 제조 방법
US6750525B2 (en) Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure
US6627928B2 (en) Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
US6174758B1 (en) Semiconductor chip having fieldless array with salicide gates and methods for making same
JP4429036B2 (ja) 半導体装置の製造方法
KR100723993B1 (ko) 반도체 메모리 장치와 그 제조 방법
US6518124B1 (en) Method of fabricating semiconductor device
US8325516B2 (en) Semiconductor device with split gate memory cell and fabrication method thereof
US6184083B1 (en) Semiconductor device and method of manufacturing the same
JP2004039866A (ja) 半導体装置及びその製造方法
US6657265B2 (en) Semiconductor device and its manufacturing method
US20090039412A1 (en) Semiconductor device including nonvolatile memory and method of fabricating the same
JP4266089B2 (ja) 半導体記憶装置の製造方法
KR100251229B1 (ko) 노아형 마스크 롬의 개선된 구조 및 그 제조방법
US6602774B1 (en) Selective salicidation process for electronic devices integrated in a semiconductor substrate
JP2003023117A (ja) 半導体集積回路装置の製造方法
JP3317857B2 (ja) 半導体装置及びその製造方法
JPH1084051A (ja) 半導体集積回路装置およびその製造方法
JPH0888360A (ja) 半導体装置及びその製造方法
US6949803B2 (en) Manufacturing process for a high voltage transistor integrated on a semiconductor substrate with non-volatile memory cells and corresponding transistor
JP2002289792A (ja) 半導体装置の製造方法
JPH06236973A (ja) 不揮発性半導体記憶装置の製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ICHIGE, MASAYUKI;SUGIMAE, KIKUKO;SHIROTA, RIICHIRO;REEL/FRAME:013179/0463

Effective date: 20020802

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION