US20020066909A1 - Heterojunction bipolar transistor and method of producing the same - Google Patents

Heterojunction bipolar transistor and method of producing the same Download PDF

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Publication number
US20020066909A1
US20020066909A1 US10/011,514 US1151401A US2002066909A1 US 20020066909 A1 US20020066909 A1 US 20020066909A1 US 1151401 A US1151401 A US 1151401A US 2002066909 A1 US2002066909 A1 US 2002066909A1
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layer
photoresist
forming
sin film
substrate
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Masahiro Tanomura
Hidenori Shimawaki
Yosuke Miyoshi
Fumio Harima
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NEC Compound Semiconductor Devices Ltd
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NEC Corp
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Publication of US20020066909A1 publication Critical patent/US20020066909A1/en
Assigned to NEC COMPOUND SEMICONDUCTOR DEVICES, LTD. reassignment NEC COMPOUND SEMICONDUCTOR DEVICES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Priority to US10/447,934 priority Critical patent/US6924201B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Definitions

  • the present invention relates to a reliable heretojunction bipolar transistor (HBT) and a method of producing the same.
  • Prerequisites with an HBT are reducing capacitance between a base and a collector and lowering offset voltage for enhancing RF (Radio Frequency) performance.
  • a decrease in capacitance between the base and the collector increases gain while a decrease in offset voltage reduces effective ON resistance to thereby increase power efficiency.
  • Another prerequisite is reducing the scatter of RF performance among HBTs.
  • the accuracy of a junction area between the base and the collector is the key to low capacitance between the base and the collector, low offset voltage, and small scatter of RF performance.
  • An accurate junction area is not achievable unless the amount of side etching of the base layer is controlled by promoting accurate processing of an emitter layer that overlies the base layer. While dry etching with high anisotropy is available for promoting accurate processing of the emitter layer, dry etching damages a device and deteriorates the characteristics and reliability of the device. It has therefore been customary to use isotropic dry etching or wet etching.
  • an HBT using GaAs has an emitter layer implemented as an InGaP layer.
  • Photoresist or an oxide film has heretofore been used as a mask for processing an InGaP layer.
  • Such a material used as a mask cannot closely adhere to the InGaP emitter layer and causes the amount of side etching of the emitter layer to be scattered.
  • Japanese Patent Laid-Open Publication No. 2000-124226 uses an SiN film as a mask for processing InGaP. Even this kind of scheme fails to accurately lower offset voltage and capacitance between the base and the collector without any scatter.
  • a method of producing an HBT uses a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order.
  • the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask.
  • the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.
  • a mesa step is formed between the sidewall of the first collector layer and the sidewall of the second collector layer with the etching stopper layer forming a boundary.
  • FIG. 1A is a section showing a conventional HBT with a penthouse
  • FIG. 1B is a section showing the conventional HBT with the penthouse peeled off
  • FIG. 2 is a section showing an HBT embodying the present invention
  • FIGS. 3A through 3H are sections showing a sequence of steps for producing the HBT of the illustrative embodiment
  • FIG. 4 is a section showing an alternative embodiment of the present invention.
  • FIGS. 5A through 5H are sections showing a sequence of steps for producing the HBT of the alternative embodiment
  • FIG. 6 is a section showing another alternative embodiment of the present invention.
  • FIGS. 7A through 7H are sections showing a sequence of steps for producing the HBT of the embodiment shown in FIG. 6.
  • FIG. 1A shows a condition in which a penthouse is produced while FIG. 1B shows a condition in which the penthouse has peeled off.
  • the technology taught in Laid-Open Publication No. 2000-124226 mentioned earlier promotes accurate processing of an InGaP layer and thereby improves control over the amount of side etching of the InGaP layer.
  • FIG. 2000-124226 shows a condition in which the penthouse has peeled off.
  • the side of a base layer 405 and that of a collector layer 403 underlying an InGaP layer 406 are noticeably removed by the second side etching, causing the InGaP layer 406 to form a penthouse A.
  • the penthouse A often peels off during processing, as indicated by a portion B.
  • the surface of the base layer 405 is exposed and causes recombination current to increase thereon, degrading the reliability of the HBT.
  • the amount of side etching that causes the penthouse A to appear is effected mainly by the total thickness of the base layer 405 and collector layer 403 ; the thicker the base layer 405 and collector layer 403 , the greater the scatter of the amount of side etching.
  • Such a scatter brings about a scatter of the junction area between the base layer 405 and the collector layer 403 .
  • This problem is more serious with a power device needing a high breakdown voltage.
  • a power device needs a collector layer as thick as, e.g., 400 nm or above.
  • FIG. 1A There are also shown in FIG. 1A a semi insulative GaAs substrate 401 , a subcollector layer 402 , an emitter gap layer 407 , an emitter electrode 411 , a base electrode 412 , an SiN film 421 , an alloyed layer 422 , and a photoresist PR.
  • the HBT is made up of a semi insulative GaAs substrate 101 , a subcollector layer 102 , a collector layer 103 , a base layer 105 , an emitter layer 106 , an emitter cap layer 107 , a mesa step 109 , an emitter electrode 111 , a base electrode 112 , an SiN film 121 , and an alloyed layer 122 .
  • the semi insulative GaAs substrate 10 is formed of nondoped or Cr-doped GaAs and has low electric resistance.
  • the subcollector layer 102 is an n+-type GaAs layer formed on the GaAs substrate 101 .
  • the collector layer 103 is an n+-type or a nondoped GaAs layer formed on the subcollector layer 102 .
  • the sidewall of the collector layer 103 has a mesa step 109 .
  • the base layer 105 is a p+-type GaAs layer formed on the collector layer 103 .
  • the sidewall of the base layer 105 underlies the emitter layer 106 .
  • the emitter layer 106 is an n-type InGaP layer formed in a preselected region on the base layer 105 .
  • the emitter cap layer 107 is an n-type GaAs or InGaAs layer formed in a preselected region on the emitter layer 106 .
  • the mesa step 109 is formed on the sidewall of the collector layer 103 and serves to reduce the size of the penthouse of the emitter layer 106 .
  • the emitter electrode 111 is a WSi electrode formed on the emitter cap layer 107 .
  • the alloyed layer 122 is formed in a contact hole extending throughout the SiN film 121 and emitter layer 106 , which are laminated on the base layer 105 , and is implemented by Pt and InGaP and Pt and GaAs.
  • the base electrode 112 is an electrode formed in a contact hole extending throughout the SiN film 121 and emitter layer 106 laminated on the alloyed layer 122 .
  • the SiN film 121 is a passivation film extending over a preselected region of the emitter layer 106 , emitter cap layer 107 and emitter electrode 111 .
  • the collector electrode 113 is formed in a preselected region on the subcollector layer 102 .
  • FIGS. 3A through 3H for describing a procedure for producing the HBT shown in FIG. 2.
  • the subcollector layer 102 is formed on the semi insulative GaAs substrate 101 .
  • the collector layer 103 which may be 400 nm to 2,000 nm thick by way of example, is formed on the collector layer 103 .
  • the base layer 105 which may be 40 nm to 100 nm thick by way of example, is formed on the collector layer 103 .
  • the emitter layer 106 which may be 10 nm to 100 nm thick by way of example, is formed on the base layer 105 .
  • the emitter cap layer 107 is formed on the emitter layer 106 , thereby completing a laminate epitaxial wafer.
  • the emitter cap layer 107 is selectively etched out to the surface of the emitter layer 106 by a phosphoric or a sulfuric etchant with the emitter electrode 111 serving as a mask.
  • the SiN film 121 is formed over the entire surface of the laminate to a thickness of, e.g., 10 nm to 200 nm.
  • a PR mask is formed on the SiN film 121 for forming a hole at a preselected position.
  • the SiN film 121 is partly etched out by a hydrofluoric etchant, so that the emitter layer 106 is partly exposed to the outside.
  • the PR mask shown in FIG. 3D is used to form the base electrode 112 by evaporation lift-off.
  • sintering using, e.g., Pt/Ti/Pt/Au is effected from above the emitter layer 106 .
  • the alloyed layer of Pt and InGaP and Pt and GaAs is formed by an alloying technology, electrically connecting the base layer 105 and base electrode 112 .
  • a specific evaporation lift-off method is evaporating, e.g., Pt/Ti/Pt/Au inclusive of the PR mask and then lifting off the electrode material from needless portions together with the PR mask. Alloying may be effected at, e.g., 300° C. after the lift-off. This successfully enhances adhesion of the emitter layer 106 and electrode material to each other.
  • Pt/Ti/Pt/Au is a non-alloy type ohmic electrode that insures reliable ohmic contact and implements an electrode pattern with high resolution.
  • a first PR mask is formed over a preselected region P 1 -P 1 ′ on the base electrode 112 and SiN film 121 .
  • the SiN film 121 is then removed by a hydrofluoric etchant via the PR mask. This is followed by removing the emitter layer 106 by use of a hydrochloric etchant, then removing the base layer 105 by use of a sulfuric etchant, and then removing the collector layer 103 halfway by, e.g., 10 nm and 200 nm.
  • the amount of side etching of the base layer 105 and that of the collector layer 103 respectively correspond to the thickness by which the base layer 105 has been removed and the thickness by which the collector 103 has been removed. Therefore, the collector 103 should preferably be removed by a relatively small thickness in order to reduce the amount of side etching of the base layer 105 and that of the collector layer 103 . This successfully reduces the size of the penthouse of the emitter layer 106 .
  • a second PR mask is formed over preselected regions P 1 ′-P 2 ′ and P 1 -P 2 on the base layer 105 and collector layer 103 .
  • the collector layer 103 is then removed to the surface of the subcollector layer 102 via the second PR mask by use of a phosphoric etchant or a sulfuric etchant.
  • the second PR mask therefore preserves the sidewalls (first sidewalls) of the base layer 105 and collector layer 103 implemented by the first PR mask, so that the penthouse of the emitter layer 106 is prevented from increasing in size.
  • the amount of side etching of the collector layer 103 underlying the second PR mask also corresponds to the thickness by which the collector layer 103 has been removed. It follows that the second PR mask covering the collector layer 103 should preferably extend over a certain width. More specifically, it is desirable to provide each of the regions P 1 ′ and P 2 ′ and P 1 -P 2 with a certain width. This successfully controls the dimension of the second sidewall or lower sidewall of the collector layer 103 implemented by the second PR mask such that the second sidewall does not reach the first sidewall. Consequently, the mesa step 109 whose boundary is the bottom of the second PR mask is formed. If desired, the first and second sidewalls may be formed flush with each other, depending on the relation between the width of the region P 1 ′-P 2 ′ and that of the region P 1 -P 2 and the remaining thickness of the collector layer 103 .
  • the collector electrode 113 is formed by, e.g., AuGe/Ni/Au by using evaporation lift-off.
  • the illustrative embodiment insures an accurate junction area between the base and the collector and thereby accurately reduces offset voltage and capacitance between the base and the collector without any scatter. Further, the illustrative embodiment obstructs the peeling of the InGaP emitter layer.
  • the collector layer 103 is etched out halfway by 10 nm to 200 nm in order to form a mesa step, as described with reference to FIG. 3E. Subsequently, as shown in FIG. 3F, a PR mask different from a PR mask used in the step of FIG. 3E is used to remove the remaining collector layer 103 . It has been customary to use only the first PR mask of FIG. 3E for removing an SiN film, an emitter layer, a base layer and a collector layer and thereby exposing a subcollector layer, as described with reference to FIG. 1A. This, however, cause the emitter layer to form a penthouse due to the side etching of the base layer and collector layer.
  • the side etching is effected mainly by the thickness of the base layer and collector layer.
  • the illustrative embodiment removes the collector layer only by 10 nm to 200 nm and thereby reduces the amount of side etching. This is why the emitter layer does not form a penthouse and the junction area between the base and the collector is scattered little.
  • the penthouse of the emitter layer is apt to come off during process if the emitter layer is as thin as 100 nm or below, as shown in FIG. 1B.
  • the surface of the base layer 105 is exposed with the result that recombination current on the base surface increases and degrades the reliability of the HBT.
  • the penthouse of the InGaP layer is small and peels off little, enhancing the reliability of the transistor.
  • the illustrative embodiment like the previous embodiment includes a semi insulative GaAs substrate 201 , a subcollector layer 202 , a base layer 205 , an emitter layer 206 , an emitter gap layer 207 , a mesa step 209 , an emitter electrode 221 , a base electrode 212 , a first SiN film 221 , and an alloyed layer 222 .
  • the illustrative embodiment additionally includes a first collector layer 203 , a second collector layer 204 , an etching stopper layer 208 , and a second SiN film 223 .
  • the first collector layer 203 is an n-type or a nondoped GaAs layer formed on the subcollector layer 202 .
  • the sidewall of the first collector layer 203 does not include a mesa step and is formed below the etching stopper layer 208 .
  • the second collector layer 204 is an n-type or a nondoped GaAs layer formed in a preselected region on the etching stopper layer 208 .
  • the sidewall of the second collector layer 204 does not include a mesa step and is formed below the emitter layer 206 together with the sidewall of the base layer 205 .
  • the etching stopper layer 208 is formed of InGaP and intervenes between the first and second collector layers 203 and 204 .
  • the edge of the etching stopper layer 208 protrudes from the sidewall of the first collector layer 203 and that of the second collector layer 204 .
  • the sidewall of the first collector layer 203 and that of the second collector layer 204 form mesa a step with the intermediary of the etching stopper layer 208 .
  • the second SiN film 223 is formed on the surfaces of the first SiN film 221 , base electrode 212 , emitter layer 206 , base layer 205 , second collector layer 204 , and etching stopper layer 208 .
  • this embodiment is similar to the previous embodiment.
  • the subcollector layer 202 is formed on the semi insulative GaAs substrate 201 .
  • the first collector layer 203 which may be 400 nm to 2,000 nm thick by way of example, is formed on the subcollector layer 202 .
  • the etching stopper layer 208 is formed on the first collector layer 203 .
  • the second collector layer 204 which may be 10 nm to 200 nm thick, is formed on the etching stopper layer 208 .
  • the base layer 205 which may be 40 nm to 100 nm thick by way of example, is formed on the second collector layer 204 .
  • the emitter layer 206 which may be 10 nm to 100 nm thick by way of example, is formed on the base layer 205 .
  • the emitter cap layer 207 is formed on the emitter layer 206 , completing a laminate epitaxial wafer.
  • WSi is etched via a PR mask to thereby form the emitter electrode 211 .
  • the emitter cap layer 207 is selectively etched to the surface of the emitter layer 206 by a phosphoric or a sulfuric etchant with the emitter mask 211 serving as a mask.
  • the first SiN film 221 is then formed over the entire surface of the laminate with a thickness of 10 nm to 200 nm.
  • a PR mask is formed on the first SiN film 221 for forming a hole at a preselected position.
  • the first SiN film 221 is then partly removed by a hydrofluoric etchant via the PR mask so as to expose part of the emitter electrode 206 .
  • the base electrode 212 is formed via the PR mask of FIG. 5D by using evaporation lift-off. For example, sintering is effected with Pt/Ti/Pt/Au from above the emitter layer 206 .
  • the alloy layer 222 of Pt and InGaP and Pt and GaAs is formed by an alloying technology, thereby electrically connecting the base layer 205 and base electrode 212 .
  • a PR mask is formed in a preselected region P 1 -P 1 ′ on the base electrode 212 and first SiN film 221 .
  • the SiN film 221 is then removed via the PR mask by using a hydrofluoric etchant. This is followed by removing the emitter layer 206 with a hydrochloric etchant, then removing the base layer 205 with a phosphoric or a sulfuric etchant, and then removing the second collector layer 204 to the surface of the etching stopper layer 208 .
  • the amount of side etching of the base layer 205 and that of the second collector layer 204 respectively correspond to the thickness by which the base layer 205 has been removed and the thickness by which the collector layer 204 has been removed. Therefore, the second collector layer 204 should preferably be relatively thin in order to reduce the amount of side etching of the base layer 205 and that of the second collector layer 204 . This desirably reduces the size of the penthouse of the emitter layer 206 .
  • the second SiN film 223 is formed over the entire surface of the laminate.
  • a second PR mask is then formed in a preselected region P 2 -P 2 ′, which is broader than the region P 1 -P 1 ′, on the second SiN film 23 .
  • needless part of the second SiN film 223 is removed via the second PR mask.
  • This is followed by removing the etching stopper layer 208 with a hydrochloric etchant and then removing the first collector layer 203 to the surface of the subcollector layer 202 .
  • the second SiN film 223 and second PR mask preserve the sidewall of the base layer 205 and that of the second collector layer 204 implemented by the first PR mask, thereby preventing the penthouse of the emitter layer 206 from increasing in size.
  • the amount of side etching of the first collector layer 203 which underlies the emitter layer 206 , also corresponds to the thickness by which the first collector layer 203 has been removed. More specifically, the region P 2 -P 2 ′ should preferably have a certain width. In this condition, the sidewall (second sidewall) of the first collector layer 203 implemented by the second PR mask can be prevented from extending inward of the first sidewall. Consequently, the mesa step 209 whose boundary is the stopper layer 208 is formed. Again, the first and second sidewalls may be formed flush with each other, depending on the relation between the width of the region P 2 -P 2 ′ and the thickness of the first collector layer 203 , if desired.
  • the collector electrode 213 is formed by evaporation lift-off using, e.g., AuGe/Ni/Au.
  • the HBT of the illustrative embodiment includes a semi insulative GaAs substrate 301 , a subcollector layer 302 , a base layer 305 , an emitter layer 306 , an emitter cap layer 307 , a mesa step 309 , an emitter electrode 311 , a base electrode 312 , a first SiN film 321 , and an alloyed layer 322 .
  • This embodiment differs from the embodiment of FIG. 2 in that it additionally includes a first collector layer 303 , a second collector layer 304 and a second SiN film 323 and differs from the embodiment of FIG. 4 in that it does not include an etching stopper layer.
  • this embodiment is similar to the embodiment of FIG. 4.
  • the subcollector layer 302 is formed on the semi insulative GaAs substrate 301 .
  • the first collector layer 303 which may be 400 nm to 2,000 nm thick by way of example, is formed on the subcollector layer 302 .
  • the second collector layer 304 which may be 10 nm to 200 nm thick, is formed on the first collector layer 203 .
  • the base layer 305 which may be 40 nm to 100 nm thick by way of example, is formed on the second collector layer 304 .
  • the emitter layer 306 which may be 10 nm to 100 nm thick by way of example, is formed on the base layer 305 .
  • the emitter cap layer 307 is formed on the emitter layer 306 , completing a laminate epitaxial wafer.
  • WSi is etched via a PR mask to thereby form the emitter electrode 311 .
  • the emitter cap layer 307 is selectively etched to the surface of the emitter layer 306 by a phosphoric or a sulfuric etchant with the emitter mask 311 serving as a mask.
  • the first SiN film 321 is then formed over the entire surface of the laminate with a thickness of 10 nm to 200 nm.
  • a PR mask is formed on the first SiN film 321 for forming a hole at a preselected position.
  • the first SiN film 321 is then partly removed by a hydrofIuoric etchant with the PR mask so as to expose part of the emitter electrode 306 .
  • the base electrode 312 is formed via the PR mask of FIG. 7D by using evaporation lift-off. For example, sintering is effected with Pt/Ti/Pt/Au from above the emitter layer 306 .
  • the alloy layer 322 of Pt and InGaP and Pt and GaAs is formed by an alloying technology, thereby electrically connecting the base layer 305 and base electrode 312 .
  • a PR mask is formed in a preselected region P 1 -P 1 ′ on the base electrode 312 and first SiN film 321 .
  • the SiN film 321 is then removed via the PR mask by using a hydrofluoric etchant. This is followed by removing the emitter layer 306 with a hydrochloric etchant, then removing the base layer 305 with a phosphoric or a sulfuric etchant, and then removing the second collector layer 304 .
  • the amount of side etching of the base layer 305 and that of the second collector layer 304 respectively correspond to the thickness by which the base layer 305 has been removed and the thickness by which the collector layer 304 has been removed.
  • the second collector layer 304 should preferably be relatively thin in order to reduce the amount of side etching of the base layer 305 and that of the second collector layer 304 . This desirably reduces the size of the penthouse of the emitter layer 306 .
  • the second SiN film 323 is formed over the entire surface of the laminate.
  • a PR mask is then formed in a preselected region P 2 -P 2 ′ on the second SiN film 323 .
  • needless part of the second SiN film 323 is removed via the above PR mask.
  • This is followed by removing the first collector layer 303 to the surface of the subcollector layer 302 with a phosphoric or a sulfuric etchant.
  • the second SiN film 323 and second PR mask preserve the sidewall of the base layer 305 and that of the second collector layer 304 implemented by the first PR mask, thereby preventing the penthouse of the emitter layer 306 from increasing in size.
  • the amount of side etching of the first collector layer 303 which underlies the emitter layer 306 , also corresponds to the thickness by which the first collector layer 303 has been removed. More specifically, the region P 2 -P 2 ′ should preferably have a certain width. In this condition, the sidewall (second sidewall) of the first collector layer 3203 implemented by the second PR mask can be prevented from extending inward of the first sidewall. Consequently, the mesa step 309 whose boundary is the interface between the first and second collector layers 303 and 304 is formed. Again, the first and second sidewalls may be formed flush with each other, depending on the relation between the width of the region P 2 -P 2 ′ and the thickness of the first collector layer 303 , if desired.
  • the collector electrode 313 is formed by evaporation lift-off using, e.g., AuGe/Ni/Au.
  • the present invention is applicable not only to an HBT but also to other various kinds of transistors.
  • the present invention reduces the size of a penthouse protruding from, e.g., a collector layer sideways outward of the sidewall of an underlying layer.
  • the present invention provides an HBT having an accurate junction area between a base and a collector and thereby accurately reducing offset voltage and capacitance between the base and the collector without any scatter. Further, the HBT of the present invention is reliable because it obstructs the peeling of an InGaP emitter layer and thereby prevents the surface of a base layer from being exposed.

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Cited By (9)

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US20050085044A1 (en) * 2002-01-25 2005-04-21 Axel Hulsmann Method for the production of a hetero-bipolar transistor
US20070059853A1 (en) * 2002-02-15 2007-03-15 Atsushi Kurokawa Method for Manufacturing Semiconductor Device
US7576409B1 (en) 2004-08-20 2009-08-18 Hrl Laboratories, Llc Group III-V compound semiconductor based heterojuncton bipolar transistors with various collector profiles on a common wafer
US7875523B1 (en) 2004-10-15 2011-01-25 Hrl Laboratories, Llc HBT with emitter electrode having planar side walls
US8169001B1 (en) 2004-10-15 2012-05-01 Hrl Laboratories, Llc Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing
US9530708B1 (en) 2013-05-31 2016-12-27 Hrl Laboratories, Llc Flexible electronic circuit and method for manufacturing same
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