CN107958926A - 一种异质结双极晶体管器件中基极基座的返工制作方法 - Google Patents

一种异质结双极晶体管器件中基极基座的返工制作方法 Download PDF

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CN107958926A
CN107958926A CN201711175805.XA CN201711175805A CN107958926A CN 107958926 A CN107958926 A CN 107958926A CN 201711175805 A CN201711175805 A CN 201711175805A CN 107958926 A CN107958926 A CN 107958926A
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谢骞
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Chengdu Hiwafer Technology Co Ltd
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7373Vertical transistors having a two-dimensional base, e.g. modulation-doped base, inversion layer base, delta-doped base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/6631Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318Heterojunction transistors

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Abstract

本发明涉及一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,在基极基座上进行返工程序,包括以下内容:101、采用BP光罩,重新光刻制作出掩膜图形,形成返工BP光阻,开始返工程序;102、进行InGaP侧壁补湿法蚀刻及SiN Nitride侧壁补干法蚀刻,去除侧壁残留;103、去除返工BP光阻,结束返工程序。本发明通过在基极基座上再次使用单层光罩(BP Mask)返工蚀刻工艺,可以快捷去除侧边突出下层GaAs的SiN Nitride及InGap层残留,及时对产品进行补救,避免原工艺流程中返工步骤重复性的原材料浪费问题,且不会影响产品性能。

Description

一种异质结双极晶体管器件中基极基座的返工制作方法
技术领域
本发明涉及半导体制造工艺技术领域,特别是涉及一种异质结双极晶体管器件中基极基座的制作过程中出现工艺残留问题后返工制作的方法。
背景技术
基极基座是异质结双极晶体管器件中介于集极(Collector)与基极(Base)两极的斜坡,其电性影响为BVceo及BVcbo。
目前,基极基座使用双层光罩(BR,BP Mask)蚀刻工艺流程及单层光罩(BP Mask)蚀刻工艺方法,双层光罩(BR,BP Mask)蚀刻工艺流程依次为Emitter Mesa流程、CollectorMetal流程、氮化硅沉积、双层光罩1(BR Mask)光刻流程、氮化硅刻蚀、InGaP蚀刻、去除BR光阻、双层光罩2(BP Mask)光刻流程、主GaAs蚀刻、去除BP光阻,单层光罩(BP Mask)蚀刻工艺方法依次为Emitter Mesa流程、Collector Metal流程、氮化硅沉积、单层光罩(BP Mask)光刻流程、氮化硅刻蚀、InGaP蚀刻、主GaAs蚀刻、去除BP光阻。
其中,因主GaAs湿刻蚀时蚀刻率不稳及工艺窗口较小造成基极基座成品侧边的氮化硅(SiN Nitride)及InGaP层突出,CD(关键尺寸)超过下层GaAs,裸露出来的InGaP和SiN边缘CD过大,容易导致后续蒸镀工艺中金线在BP斜坡上断线,造成其电性可靠度及目检不过关。因此,在出现该工艺异常后,需要采取及时有效的返工方案进行补救。
发明内容
本发明的目的在于提供一种异质结双极晶体管器件中基极基座的返工制作方法,用于去除异质结双极晶体管基极基座刻蚀工艺产生的氮化硅及InGaP层残留问题,以返工出异质结双极晶体管基极基座。
为了实现上述目的,本发明提供了以下技术方案:
本发明提供一种异质结双极晶体管器件中基极基座的返工制作方法,在基极基座上进行返工程序,包括以下内容:
101、采用BP光罩,重新光刻制作出掩膜图形,形成返工BP光阻,开始返工程序;
102、进行InGaP侧壁补湿法蚀刻及SiN Nitride侧壁补干法蚀刻,以去除侧壁残留:先对InGaP边缘侧壁湿法蚀刻出InGaP台面,再对SiN Nitride边缘侧壁干法蚀刻出SiN台面;
103、去除返工BP光阻,结束返工程序。
其中,返工BP光阻的关键尺寸小于基极基座的GaAs基座层的关键尺寸。
进一步地,采用浓盐酸或磷酸对InGaP边缘侧壁湿法蚀刻出InGaP台面。
又进一步地,采用六氟化硫和氧气对SiN Nitride边缘侧壁干法蚀刻出SiN台面。
在上述单层光罩(BP Mask)返工蚀刻工艺中,光刻的关键尺寸比原先未返工时光刻的关键尺寸小,用于去除侧边突出下层GaAs的氮化硅(SiN Nitride)及InGap层残留。
与现有技术相比,本发明具有以下优点:
本发明的一种异质结双极晶体管器件中基极基座的返工制作方法,通过在基极基座上再次使用单层光罩(BP Mask)返工蚀刻工艺,可以快捷去除侧边突出下层GaAs的SiNNitride及InGap层残留,及时对产品进行补救,避免原工艺流程中返工步骤重复性的原材料浪费问题,且不会影响产品性能。
下面通过附图和实施例,对本发明的技术方案做进一步的详细描述。
附图说明
图1为本发明的实施例的流程框图;
图2为本发明的实施例的带有SiN Nitride及InGap层残留的基极基座结构示意图;
图3为图2经光刻后的结构示意图;
图4为图3经蚀刻后的结构示意图;
图5为图4经蚀刻后的结构示意图;
图6为图5经去除返工BP光阻后的结构示意图;
其中,1为返工BP光阻。
具体实施方式
以下结合附图对本发明的实施例进行说明,应当理解,此处所描述的实施例仅用于说明和解释本发明,并不用于限定本发明。
实施例
本实施例提供一种异质结双极晶体管器件中基极基座的返工制作方法,在发现InGaP和SiN台面侧壁的残留问题后,参见图2,在基极基座上进行返工程序,返工制作方法的具体步骤如下,参见图1:
步骤101、采用BP光罩,重新光刻制作出掩膜图形,形成返工BP光阻(返工时的BP光阻)1,开始返工程序,参见图3。
此时,返工时采用比原BP光罩(在制作成品时BP光罩)尺寸较小的返工BP光罩(返工时的BP光罩),制作出返工掩膜图形(返工时的掩膜图形),该返工掩膜图形要小于该基极基座的GaAs基座层(如图2-6所示的BP台面)尺寸,形成的返工BP光阻(BP掩膜)1的关键尺寸小于基极基座的GaAs基座层的关键尺寸。
步骤102、进行InGaP侧壁补湿法蚀刻及SiN Nitride侧壁补干法蚀刻,去除侧壁残留。
此时,先对InGaP边缘侧壁湿法蚀刻出InGaP台面,再对SiN Nitride边缘侧壁干法蚀刻出SiN台面,以去除原InGaP和SiN Nitride层的侧壁残留,参见图4、图5。其中,采用浓盐酸或磷酸对InGaP边缘侧壁湿法蚀刻出InGaP台面;采用六氟化硫和氧气对SiN Nitride边缘侧壁干法蚀刻出SiN台面。
步骤103、去除返工BP光阻,结束返工程序,参见图6。
通过采用比原BP光罩尺寸较小的光罩,重新光刻制作出小尺寸的掩膜图形,再进行InGaP及SiN Nitride侧壁补蚀刻工艺,以去除基极基座的氮化硅Nitride及InGaP层侧边的残留,从工艺返工中最大程度上对产品进行补救。
应当理解,本发明上述实施例及实例,是出于说明和解释目的,并非因此限制本发明的范围。本发明的范围由权利要求项定义,而不是由上述实施例及实例定义。

Claims (5)

1.一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,在基极基座上进行返工程序,包括以下内容:
101、采用BP光罩,重新光刻制作出掩膜图形,形成返工BP光阻,开始返工程序;
102、进行InGaP侧壁补湿法蚀刻及SiN Nitride侧壁补干法蚀刻,去除侧壁残留;
103、去除返工BP光阻,结束返工程序。
2.根据权利要求1所述一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,所述步骤101中,返工BP光阻的关键尺寸小于基极基座的GaAs基座层的关键尺寸。
3.根据权利要求1所述一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,所述步骤102的具体步骤如下:
先对InGaP边缘侧壁湿法蚀刻出InGaP台面,再对SiN Nitride边缘侧壁干法蚀刻出SiN台面。
4.根据权利要求3所述一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,采用浓盐酸或磷酸对InGaP边缘侧壁湿法蚀刻出InGaP台面。
5.根据权利要求3所述一种异质结双极晶体管器件中基极基座的返工制作方法,其特征在于,采用六氟化硫和氧气对SiN Nitride边缘侧壁干法蚀刻出SiN台面。
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US20020066909A1 (en) * 2000-12-04 2002-06-06 Nec Corporation Heterojunction bipolar transistor and method of producing the same
US20040224463A1 (en) * 2003-05-09 2004-11-11 Mchugo Scott A. Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors
CN102201339A (zh) * 2011-05-30 2011-09-28 中国电子科技集团公司第五十五研究所 一种减小磷化铟双异质结双极型晶体管b-c结电容方法
CN106486355A (zh) * 2016-12-20 2017-03-08 成都海威华芯科技有限公司 一种InGaP的湿法刻蚀方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020066909A1 (en) * 2000-12-04 2002-06-06 Nec Corporation Heterojunction bipolar transistor and method of producing the same
US20040224463A1 (en) * 2003-05-09 2004-11-11 Mchugo Scott A. Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors
CN102201339A (zh) * 2011-05-30 2011-09-28 中国电子科技集团公司第五十五研究所 一种减小磷化铟双异质结双极型晶体管b-c结电容方法
CN106486355A (zh) * 2016-12-20 2017-03-08 成都海威华芯科技有限公司 一种InGaP的湿法刻蚀方法

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