US11569424B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US11569424B2
US11569424B2 US17/123,078 US202017123078A US11569424B2 US 11569424 B2 US11569424 B2 US 11569424B2 US 202017123078 A US202017123078 A US 202017123078A US 11569424 B2 US11569424 B2 US 11569424B2
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electrode
gap
semiconductor device
layer
metal layer
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US20210104652A1 (en
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Mitsuaki Oya
Masanori Hiroki
Keimei Masamoto
Shigeo Hayashi
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S41/00—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps
    • F21S41/10—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source
    • F21S41/14—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source characterised by the type of light source
    • F21S41/141—Light emitting diodes [LED]
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S43/00—Signalling devices specially adapted for vehicle exteriors, e.g. brake lamps, direction indicator lights or reversing lights
    • F21S43/10—Signalling devices specially adapted for vehicle exteriors, e.g. brake lamps, direction indicator lights or reversing lights characterised by the light source
    • F21S43/13—Signalling devices specially adapted for vehicle exteriors, e.g. brake lamps, direction indicator lights or reversing lights characterised by the light source characterised by the type of light source
    • F21S43/14—Light emitting diodes [LED]
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21W—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO USES OR APPLICATIONS OF LIGHTING DEVICES OR SYSTEMS
    • F21W2103/00—Exterior vehicle lighting devices for signalling purposes
    • F21W2103/55—Daytime running lights [DRL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to semiconductor devices.
  • LEDs Semiconductor light-emitting elements
  • DRLs daytime running lights
  • HLs headlamps
  • the market is growing for vehicle-mounted light sources including high-power LEDs with at least 1-watt light output, leading to a rapid increase in replacement of halogen lamps and high-intensity discharge (HID) lamps with LEDs.
  • the flip-chip bonding for bonding the semiconductor chip face down to the mounting substrate is known.
  • the semiconductor chip is flipped (turned upside down) so that an electrode of the mounting substrate and an electrode of the semiconductor chip are directly bonded together using a metal bump, meaning that this technique is less dependent on the wire diameter or the wire routing than in the case where the semiconductor chip is bonded to the mounting substrate by a face-up method for wiring the semiconductor chip with its electrode forming surface directed upward; thus, the flip-chip bonding is suitable for highly integrated semiconductor chips with large electric current and therefore is used for vehicle-mounted light sources as a mounting method for high-output applications.
  • Japanese Unexamined Patent Application Publication No. 2011-009429 discloses a technique for densely arranging a plurality of metal bumps between a semiconductor element and a mounting substrate at the time of bonding the semiconductor element and the mounting substrate together for the purpose of improving heat dissipation properties.
  • the present disclosure aims to provide a semiconductor device exceptionally reliable in the long run by reducing mounting damage.
  • a semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer that bonds the first electrode and the second electrode together.
  • the bonding metal layer includes a gap inside.
  • the first electrode includes a p-side electrode and an n-side electrode. A proportion of an area taken up by the gap in a plan view is lower in a region close to a p-n electrode opposed portion than in a region away from the p-n electrode opposed portion.
  • the p-n electrode opposed portion is a portion across which the p-side electrode and the n-side electrode are opposed to each other.
  • the mounting damage can be reduced, and thus it is possible to provide a semiconductor device exceptionally reliable in the long run.
  • FIG. 1 A is a cross-sectional view of a semiconductor device according to Embodiment 1 taken along line IA-IA in FIG. 2 B ;
  • FIG. 1 B is a cross-sectional view of a semiconductor device according to Embodiment 1 taken along line IB-IB in FIG. 2 B ;
  • FIG. 2 A is a cross-sectional view of a semiconductor device according to Embodiment 1 in a T cross section obtained when cut along dashed line T in FIG. 1 B ;
  • FIG. 2 B is a cross-sectional view of a semiconductor device according to Embodiment 1 in an M cross section obtained when cut along dashed line M in FIG. 1 B ;
  • FIG. 2 C is a cross-sectional view of a semiconductor device according to Embodiment 1 in a B cross section obtained when cut along dashed line B in FIG. 1 B ;
  • FIG. 3 A is a diagram illustrating the process of preparing a substrate in a first step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 3 B is a diagram illustrating the process of forming a multilayer semiconductor structure in a first step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 A is a diagram illustrating the process of etching a multilayer semiconductor structure in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 B is a diagram illustrating the process of forming an insulating film in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 C is a diagram illustrating the process of forming an ohmic contact layer and a barrier electrode of a first n-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 D is a diagram illustrating the process of forming a reflective electrode of a first p-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 E is a diagram illustrating the process of forming a barrier electrode of a first p-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 F is a diagram illustrating the process of forming a seed film in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 G is a diagram illustrating the process of forming a resist in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 H is a diagram illustrating the process of forming cover electrodes of a first p-side electrode and a first n-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 4 I is a diagram illustrating the process of removing a resist in a second step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 5 A is a diagram illustrating the process of forming a resist having an opening in a third step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 5 B is a diagram illustrating the process of forming a gold-plated film in a third step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 5 C is a diagram illustrating the process of removing a resist in a third step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 5 D is a diagram illustrating the process of pn isolation of an electrode by removing a portion of a seed film in a third step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 5 E is a diagram illustrating the process of performing heat treatment in a third step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 6 A is a diagram illustrating the process of placing a semiconductor element on a mounting substrate in a fourth step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 6 B is a diagram illustrating the process of mounting a semiconductor element on a mounting substrate and ultrasonically bonding the semiconductor element and the mounting substrate together in a fourth step in a method for manufacturing a semiconductor device according to Embodiment 1;
  • FIG. 7 A is an enlarged view of region VITA in FIG. 5 D ;
  • FIG. 7 B is an enlarged view of region VIIB in FIG. 5 E ;
  • FIG. 7 C illustrates crystal grains resulting from further coarsening of crystal grains in FIG. 7 B ;
  • FIG. 8 illustrates a method for measuring a crystal grain size
  • FIG. 9 illustrates the relationship between the average crystal grain size of a gold-plated film and the hardness of a single-layered gold-plated film
  • FIG. 10 is a timing chart for a bonding process according to Embodiment 1 when mounting a semiconductor element on a mounting substrate;
  • FIG. 11 A is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate before a bonding process for a semiconductor element and the mounting substrate;
  • FIG. 11 B is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate at the start of a bonding process for a semiconductor element and the mounting substrate;
  • FIG. 11 C is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together at the transition from STEP 1 to STEP 2 in FIG. 10 (approximately 100 milliseconds later after the start of the process);
  • FIG. 11 D is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together in the middle of STEP 2 in FIG. 10 (approximately 300 milliseconds later after the start of the process and approximately 200 milliseconds later after the start of ultrasonic vibration);
  • FIG. 11 E is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together at the end of STEP 2 in FIG. 10 (approximately 400 milliseconds later after the start of the process and approximately 300 milliseconds later after the start of ultrasonic vibration);
  • FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429;
  • FIG. 13 is a diagram illustrating the configurations of a semiconductor device according to Embodiment 1 before and after mounting;
  • FIG. 14 A is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 1 of Embodiment 1;
  • FIG. 14 B is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 2 of Embodiment 1;
  • FIG. 14 C is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 3 of Embodiment 1;
  • FIG. 14 D is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 4 of Embodiment 1;
  • FIG. 14 E is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 5 of Embodiment 1;
  • FIG. 14 F is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 6 of Embodiment 1;
  • FIG. 14 G is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 7 of Embodiment 1;
  • FIG. 14 H is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 8 of Embodiment 1;
  • FIG. 14 I is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 9 of Embodiment 1;
  • FIG. 14 J is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 10 of Embodiment 1;
  • FIG. 14 K is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 11 of Embodiment 1;
  • FIG. 14 L is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 12 of Embodiment 1;
  • FIG. 14 M is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 13 of Embodiment 1;
  • FIG. 14 N is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 14 of Embodiment 1;
  • FIG. 14 O is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 15 of Embodiment 1;
  • FIG. 15 is a cross-sectional view illustrating the configurations of a semiconductor device according to Embodiment 2 before and after mounting;
  • FIG. 16 is an enlarged view of the M cross section in (b) in FIG. 15 ;
  • FIG. 17 is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 1 of Embodiment 2;
  • FIG. 18 is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 2 of Embodiment 2;
  • FIG. 19 is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 3 of Embodiment 2 before and after mounting;
  • FIG. 20 is a cross-sectional view illustrating the configurations of a semiconductor device according to Embodiment 3 before and after mounting;
  • FIG. 21 is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 1 of Embodiment 3 after mounting;
  • FIG. 22 is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 2 of Embodiment 3 after mounting.
  • FIG. 23 is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 3 of Embodiment 3 after mounting.
  • FIG. 1 A and FIG. 1 B are cross-sectional views of semiconductor device 1 according to Embodiment 1.
  • FIG. 2 A is a cross-sectional view of semiconductor device 1 in a T cross section obtained when cut along dashed line T in FIG. 1 B .
  • FIG. 2 B is a cross-sectional view of semiconductor device 1 in an M cross section obtained when cut along dashed line M in FIG. 1 B .
  • FIG. 2 C is a cross-sectional view of semiconductor device 1 in a B cross section obtained when cut along dashed line B in FIG. 1 B . Note that FIG.
  • FIG. 1 A is a cross-sectional view taken along line IA-IA in FIG. 2 B and FIG. 1 B is a cross-sectional view taken along line IB-IB in FIG. 2 B .
  • each of dashed lines T, M, B indicates a plane perpendicular to the thickness direction (height direction) of bonding metal layer 30 .
  • Dashed line M indicates a plane passing through gap 33 and is located between dashed line T and dashed line B.
  • semiconductor device 1 As illustrated in FIG. 1 A and FIG. 1 B , semiconductor device 1 according to Embodiment 1 includes semiconductor element 10 , mounting substrate 20 , and bonding metal layer 30 for bonding semiconductor element 10 and mounting substrate 20 together.
  • Semiconductor element 10 is disposed on mounting substrate 20 . Specifically, semiconductor element 10 is bonded to mounting substrate 20 via bonding metal layer 30 and is thus mounted on mounting substrate 20 .
  • semiconductor element 10 is a light-emitting diode (LED) chip.
  • LED light-emitting diode
  • semiconductor device 1 is a semiconductor light-emitting device including the LED chip.
  • Semiconductor element 10 includes semiconductor multilayer structure 11 and first electrode E 1 provided on semiconductor multilayer structure 11 .
  • semiconductor element 10 includes, as first electrode E 1 , first p-side electrode 12 and first n-side electrode 13 formed on semiconductor multilayer structure 11 .
  • Each of first p-side electrode 12 and first n-side electrode 13 is made up of at least two layers including a surface layer made of gold in contact with bonding metal layer 30 .
  • first p-side electrode 12 and first n-side electrode 13 may be collectively referred to as first electrode E 1 when there is no need to differentiate these electrodes.
  • first electrode E 1 represents at least one of first p-side electrode 12 and first n-side electrode 13 .
  • Semiconductor multilayer structure 11 includes substrate 11 a , n-type semiconductor layer 11 b (first conductivity-type semiconductor layer), active layer 11 c , and p-type semiconductor layer 11 d (second conductivity-type semiconductor layer).
  • N-type semiconductor layer 11 b , active layer 11 c , and p-type semiconductor layer 11 d constitute a semiconductor layered body in contact with substrate 11 a and are stacked in the stated order from substrate 11 a .
  • n-type semiconductor layer 11 b , active layer 11 c , and p-type semiconductor layer 11 d are stacked on substrate 11 a in the stated order in a direction away from substrate 11 a.
  • First p-side electrode 12 and first n-side electrode 13 are formed on semiconductor multilayer structure 11 .
  • First p-side electrode 12 is formed on p-type semiconductor layer 11 d .
  • First n-side electrode 13 is formed on n-type semiconductor layer 11 b .
  • first n-side electrode 13 is formed in an exposed region that is a portion of n-type semiconductor layer 11 b exposed by removing a portion of each of p-type semiconductor layer 11 d and active layer 11 c.
  • oxide film 14 is formed on semiconductor multilayer structure 11 as an insulating film.
  • First p-side electrode 12 is formed on p-type semiconductor layer 11 d exposed in an opening of oxide film 14
  • first n-side electrode 13 is formed on n-type semiconductor layer 11 b exposed in an opening of oxide film 14 .
  • First p-side electrode 12 includes reflective electrode 12 a , barrier electrode 12 b , seed layer 12 c , and cover electrode 12 d stacked sequentially from semiconductor multilayer structure 11 .
  • reflective electrode 12 a , barrier electrode 12 b , seed layer 12 c , and cover electrode 12 d are stacked on semiconductor multilayer structure 11 in the stated order.
  • reflective electrode 12 a which is a metal film that reflects light from active layer 11 c of semiconductor multilayer structure 11 , is disposed in contact with p-type semiconductor layer 11 d (second conductivity-type semiconductor layer) of semiconductor multilayer structure 11 .
  • First n-side electrode 13 includes ohmic contact layer 13 a , barrier electrode 13 b , seed layer 13 c , and cover electrode 13 d stacked sequentially from semiconductor multilayer structure 11 .
  • cover electrodes 12 d , 13 d are surface layers made of gold in contact with bonding metal layer 30 .
  • cover electrodes 12 d , 13 d are gold-plated films formed using seed layers 12 c , 13 c as undercoat layers.
  • Mounting substrate 20 includes substrate 21 and second electrode E 2 provided on substrate 21 .
  • mounting substrate 20 includes, as second electrode E 2 , second p-side electrode 22 and second n-side electrode 23 formed on one surface of substrate 21 .
  • Each of second p-side electrode 22 and second n-side electrode 23 is a lead-out electrode for passing an electric current to semiconductor element 10 .
  • Second p-side electrode 22 is bonded to first p-side electrode 12 of semiconductor element 10 via bonding metal layer 30 .
  • second n-side electrode 23 is bonded to first n-side electrode 13 of semiconductor element 10 via bonding metal layer 30 .
  • second p-side electrode 22 and second n-side electrode 23 may be collectively referred to as second electrode E 2 when there is no need to differentiate these electrodes.
  • second electrode E 2 represents at least one of second p-side electrode 22 and second n-side electrode 23 .
  • Bonding metal layer 30 bonds semiconductor element 10 and mounting substrate 20 together.
  • bonding metal layer 30 joins semiconductor element 10 and mounting substrate 20 together.
  • bonding metal layer 30 connects first electrode E 1 provided on semiconductor multilayer structure 11 and second electrode E 2 provided on substrate 21 .
  • bonding metal layer 30 includes first bonding metal layer 31 and second bonding metal layer 32 .
  • First bonding metal layer 31 is located between first p-side electrode 12 of semiconductor element 10 and second p-side electrode 22 of mounting substrate 20 and bonds first p-side electrode 12 and second p-side electrode 22 together.
  • Second bonding metal layer 32 is located between first n-side electrode 13 of semiconductor element 10 and second n-side electrode 23 of mounting substrate 20 and bonds first n-side electrode 13 and second n-side electrode 23 together.
  • First bonding metal layer 31 and second bonding metal layer 32 include the same material.
  • each of first bonding metal layer 31 and second bonding metal layer 32 is formed of a gold-plated film.
  • Gap 33 is present surrounded by bonding metal layer 30 along the perimeter. Specifically, gap 33 is present in bonding metal layer 30 in such a manner as to be embedded in bonding metal layer 30 without contacting first electrode E 1 or second electrode E 2 . In the present embodiment, gap 33 is present in first bonding metal layer 31 , does not contact first p-side electrode 12 or first n-side electrode 13 , and is located in the vicinity of a center portion of first bonding metal layer 31 in the thickness direction. Gap 33 is a hollow cavity in the present embodiment. Thus, gap 33 is a layer of air, meaning that air exists in gap 33 .
  • gap 33 extends linearly along the outer side of first electrode E 1 in a plan view of bonding metal layer 30 . Specifically, gap 33 is parallel to the outer side of first electrode E 1 . In the present embodiment, gap 33 is formed in a grid pattern. As illustrated in FIG. 1 A , height H of gap 33 may be at least 10% of the height of bonding metal layer 30 . Note that the upper limit of height H of gap 33 is not particularly limited and, for example, may be 90%.
  • bonding metal layer 30 is formed as a result of a plurality of metal bumps between semiconductor element 10 and mounting substrate 20 being connected to each other when semiconductor element 10 is mounted on mounting substrate 20 .
  • gap 33 is formed inside bonding metal layer 30 .
  • gap 33 is formed when semiconductor element 10 is mounted on mounting substrate 20 via the plurality of metal bumps.
  • the method for manufacturing semiconductor device 1 according to Embodiment 1 includes: a first step ( FIG. 3 A and FIG. 3 B ) for forming semiconductor multilayer structure 11 of semiconductor element 10 ; a second step ( FIG. 4 A to FIG. 4 I ) for forming the first electrode of semiconductor element 10 ; a third step ( FIG. 5 A to FIG. 5 E ) for forming metal bump 30 Y on semiconductor element 10 ; and a fourth step ( FIG. 6 A and FIG. 6 B ) for mounting semiconductor element 10 on mounting substrate 20 by flip-chip bonding.
  • FIG. 3 A and FIG. 3 B are diagrams illustrating the flow for forming semiconductor multilayer structure 11 of semiconductor element 10 .
  • substrate 11 a is prepared first.
  • a wafer made of GaN GaN substrate
  • substrate 11 a is used for substrate 11 a as a light-transmissive substrate formed of a semiconductor.
  • n-type semiconductor layer 11 b , active layer 11 e , and p-type semiconductor layer 11 d are sequentially stacked on substrate 11 a by the metalorganic vapor-phase epitaxy (MOVPE) to form semiconductor multilayer structure 11 .
  • MOVPE metalorganic vapor-phase epitaxy
  • n-type semiconductor layer 11 b is an n-type nitride semiconductor layer (for example, a GaN layer)
  • active layer 11 e is a nitride semiconductor light-emitting layer
  • p-type semiconductor layer 11 d is p-type nitride semiconductor layer.
  • the nitride semiconductor light-emitting layer constituting active layer 11 e contains at least Ga and N and an appropriate amount of In is added thereto as necessary so that a desired light-emission wavelength can be obtained.
  • active layer 11 c is an InGaN layer, and the composition ratio of In is set so that active layer 11 c has a light-emission peak wavelength of 450 nm.
  • first electrode E 1 (first p-side electrode 12 , first n-side electrode 13 ) of semiconductor element 10 is formed according to the flow illustrated in FIG. 4 A to FIG. 4 I .
  • FIG. 4 A to FIG. 4 I are diagrams illustrating the flow for forming first electrode E 1 of semiconductor element 10 .
  • dry etching is performed to remove p-type semiconductor layer 11 d , active layer 11 c , and a portion of n-type semiconductor layer 11 b from semiconductor multilayer structure 11 formed in the first step described above, and thus a portion of n-type semiconductor layer 11 b is exposed from p-type semiconductor layer 11 d and active layer 11 c .
  • This makes it possible to form an exposed region in a portion of n-type semiconductor layer 11 .
  • oxide film 14 is deposited as an insulating film on the entire upper surface of semiconductor multilayer structure 11 including the exposed region of n-type semiconductor layer 11 b.
  • a resist is applied to oxide film 14 , an opening is formed in the resist by photolithography at a position corresponding to the exposed region of n-type semiconductor layer 11 b , and oxide film 14 in the opening of the resist is removed by etching using hydrofluoric acid.
  • an n-side electrode forming material for forming first n-side electrode 13 of first electrode E 1 is deposited by the electron-beam (EB) evaporation, the resist and an excess of the n-side electrode forming material are removed by the resist lift-off process, and thus a portion of first n-side electrode 13 is formed in a region from which oxide film 14 has been removed, as illustrated in FIG. 4 C .
  • EB electron-beam
  • n-side electrode forming material an Al layer (having a thickness of 0.3 ⁇ m) that is to become ohmic contact layer 13 a and a Ti layer (having a thickness of 0.1 ⁇ m) that is to become barrier electrode 13 b are deposited in ascending order of distance from n-type semiconductor layer 11 b .
  • first n-side electrode 13 laminated layers of ohmic contact layer 13 a formed of the Al layer and barrier electrode 13 b formed of the Ti layer can be formed.
  • the Al layer of the first n-side electrode 13 directly stacked on n-type semiconductor layer 11 b functions as an ohmic contact layer for n-type semiconductor layer 11 b .
  • the material of the ohmic contact layer can be, for example, Ti, V, Al, or an alloy containing at least one of these metals.
  • the Ti layer used in barrier electrode 13 b functions as a barrier for preventing reaction between the lower layer, i.e., the Al layer, and the upper layer i.e., an Au layer, to be formed in a subsequent step.
  • a resist is applied so as to cover first n-side electrode 13 and oxide film 14 , an opening is formed in the resist of p-type semiconductor layer 11 d by photolithography, and oxide film 14 in the opening of the resist is removed by etching using hydrofluoric acid.
  • a p-side electrode forming material for forming first p-side electrode 12 of first electrode E 1 is deposited by the EB evaporation, the resist and an excess of the p-side electrode forming material are removed by the resist lift-off process, and thus reflective electrode 12 a , which is a portion of first p-side electrode 12 , is formed in a region on p-type semiconductor layer 11 d from which oxide film 14 has been removed, as illustrated in FIG. 4 D .
  • reflective electrode 12 a (p-side electrode forming material) formed of an Ag layer
  • an Ag layer having a thickness of 0.2 ⁇ m is deposited.
  • reflective electrode 12 a is formed apart from oxide film 14 .
  • reflective electrode 12 a is formed so as to expose p-type semiconductor layer 11 d between reflective electrode 12 a and oxide film 14 .
  • a metal film made of a metal material having a high reflectivity and including Ag, Al, and Rh may be used as reflective electrode 12 a in order to reflect light from active layer 11 c .
  • the method for depositing reflective electrode 12 a is not limited to the EB evaporation and may be sputtering.
  • barrier electrode 12 b is formed so as to cover an upper surface and side surfaces of reflective electrode 12 a .
  • a Ti layer having a thickness of 0.8 ⁇ m is formed by sputtering as barrier electrode 12 b .
  • Ti, Ni, Pt, TiW, or the like may be used in order to protect reflective electrode 12 a .
  • barrier electrode 12 b is formed so as to cover p-type semiconductor layer 11 d exposed between oxide film 14 and reflective electrode 12 a and an end of oxide film 14 that is located on n-type semiconductor layer 11 b.
  • seed film 12 S is formed by the EB evaporation on the entire surface of the wafer having barrier electrode 12 b of first p-side electrode 12 and barrier electrode 13 b of first n-side electrode 13 formed thereon.
  • Seed film 12 S which is a metal film that is to become seed layer 12 c of first p-side electrode 12 and seed layer 13 c of first n-side electrode 13 , is used as a gold-plated undercoat electrode.
  • seed film 12 S is laminated layers of the Ti layer and the Au layer stacked in a direction away from barrier electrodes 12 b , 13 b.
  • resist 15 is formed on seed film 12 S in a boundary region between barrier electrode 12 b corresponding to first p-side electrode 12 and barrier electrode 13 b corresponding to first n-side electrode 13 .
  • cover electrodes 12 d , 13 d which are gold-plated films, are formed by metal deposition resulting from electroplating over seed film 12 S as an undercoat electrode.
  • Cover electrode 12 d is formed on seed film 12 S on barrier electrode 12 b
  • cover electrode 13 d is formed on seed film 12 S on barrier electrode 13 b .
  • a non-cyanic Au plating solution having a plating temperature of 50° C. is used, and the rate of deposition is set to 0.5 ⁇ m/min; thus, the gold-plated films having a thickness of 1.0 ⁇ m are formed as cover electrodes 12 d , 13 d.
  • cover electrodes 12 d , 13 d are used as cover electrodes 12 d , 13 d in order to improve resistance to corrosion.
  • cover electrode 12 encapsulates barrier electrode 12 b
  • cover electrode 13 d encapsulates barrier electrode 13 b .
  • oxide film 14 is located between cover electrode 12 d and cover electrode 13 d on the semiconductor multilayer structure 11 side.
  • resist 15 is removed.
  • resist 15 on seed film 12 S is removed using an organic solvent or the like.
  • FIG. 5 A to FIG. 5 E are diagrams illustrating the flow for forming metal bump 30 Y on semiconductor element 10 .
  • Metal bump 30 Y described below includes: a first bump on the p side that corresponds to first p-side electrode 12 ; and a second bump on the n side that corresponds to first n-side electrode 13 .
  • the first bump is formed on first p-side electrode 12
  • the second bump is formed on first n-side electrode 13 .
  • metal bump 30 Y is a gold-plated bump formed by gold-plating.
  • Metal bump 30 Y includes a plurality of metal layers and has a laminated structure in which at least two layers of gold-plated films having different crystal grain sizes are stacked.
  • a method for forming metal bump 30 Y will be described in detail.
  • a resist for photolithography is applied so as to cover the entire surfaces of cover electrodes 12 d , 13 d , and the resist is cured by approximately 20-minute heat treatment at 140° C.
  • opening 16 a is formed in resist 16 in a predetermined region of first electrode E 1 in which metal bump 30 Y is to be formed.
  • a plurality of openings 16 a are formed by photolithography in resist 16 in predetermined regions of cover electrode 12 d of first p-side electrode 12 and cover electrode 13 d of first n-side electrode 13 in which metal bumps 30 Y are to be formed.
  • nine total metal bumps 30 Y are illustrated as a schematic diagram, but there are actually cases where nine or more metal bumps 30 Y are formed.
  • semiconductor element 10 in semiconductor element 10 according to the present embodiment that is 800 ⁇ m square and 100 ⁇ m thick, approximately 1,000 metal bumps 30 Y each in the shape of a rectangular prism having an upper rectangular surface with a side length of 25 ⁇ m may be formed.
  • the size, the shape, the number, etc., of metal bumps 30 Y are not particularly limited and may be individually and specifically set according to the size of semiconductor element 10 and the area, the shape, etc., of each of first electrode E 1 and second electrode E 2 , for example.
  • the number of metal bumps 30 Y may be less than nine or may be a few tens or a few hundreds.
  • gold-plated film 30 X which is to become metal bump 30 Y, is formed by metal deposition in opening 16 a of resist 16 that results from gold electroplating. Specifically, gold-plated films 30 X are simultaneously formed on cover electrode 12 d of first p-side electrode 12 and cover electrode 13 d of first n-side electrode 13 that are exposed in openings 16 a of resist 16 .
  • a non-cyanic Au plating solution having a plating temperature of 50° C. is used, and the rate of deposition is set to 0.5 ⁇ m/min; thus, gold-plated film 30 X having a height (thickness) of 8 ⁇ m is formed.
  • the crystal structure of gold-plated film 30 X immediately after formation is an aggregate of fine crystal grains overall.
  • resist 16 is removed.
  • resist 16 is removed using an organic solvent or the like.
  • the plurality of gold-plated films 30 X each in the shape of a rectangular prism are formed in predetermined regions on cover electrode 12 d of first p-side electrode 12 and cover electrode 13 d of first n-side electrode 13 .
  • the distance between adjacent gold-plated films 30 X is the distance between adjacent metal bumps 30 Y and is set to such a level that adjacent metal bumps 30 Y contact each other when semiconductor element 10 is mounted on mounting substrate 20 .
  • the distance between adjacent gold-plated films 30 is, for example, 6 ⁇ m.
  • seed film 12 S on oxide film 14 located between barrier electrode 12 b of first p-side electrode 12 and barrier electrode 13 b of first n-side electrode 13 is removed.
  • the upper layer, i.e., the Au layer, of seed film 12 S is removed using an iodine solution, and then the lower layer, i.e., the Ti layer, of seed film 12 S is removed using dilute hydrofluoric acid, resulting in exposure of oxide film 14 .
  • first electrode E 1 divided as first p-side electrode 12 , which has a laminated structure of reflective electrode 12 a , barrier electrode 12 b , seed layer 12 c , and cover electrode 12 d
  • first n-side electrode 13 which has a laminated structure of ohmic contact layer 13 a , barrier electrode 13 b , seed layer 13 c , and cover electrode 13 d , can be formed.
  • metal bump 30 Y including two layers, namely, first layer 30 a and second layer 30 b , with the same composition, but different crystal grain sizes can be obtained.
  • first layer 30 a which is close to semiconductor multilayer structure 11 , has a larger crystal grain size than the crystal grain size of second layer 30 b , which is far from semiconductor multilayer structure 11 .
  • the crystal grain size of crystals included in first layer 30 a of metal bump 30 Y is equal to the crystal grain size of crystals included in cover electrodes 12 d , 13 d.
  • semiconductor element 10 including first electrode E 1 having the plurality of metal bumps 30 Y formed thereon can be obtained.
  • semiconductor element 10 including first p-side electrode 12 having the plurality of metal bumps 30 Y formed thereon and first n-side electrode 13 having metal bump 30 Y formed thereon can be obtained.
  • the plurality of metal bumps 30 Y are arranged in a matrix.
  • the distance between the plurality of metal bumps 30 Y is set to such a level that adjacent metal bumps 30 Y contact each other by the process of mounting semiconductor element 10 on mounting substrate 20 .
  • FIG. 7 A is an enlarged view of region VIIA in FIG. 5 D .
  • FIG. 7 B is an enlarged view of region VIIB in FIG. 5 E .
  • FIG. 7 C illustrates crystal grains resulting from further coarsening of crystal grains in FIG. 7 B .
  • FIG. 7 A to FIG. 7 C each illustrate a region corresponding to single gold-plated film 30 X or metal bump 30 Y on first p-side electrode 12 of first electrode E 1 and a portion of cover electrode 12 d of first p-side electrode 12 that is located below said single gold-plated film 30 X or metal bump 30 Y.
  • FIG. 7 A illustrates a cross section of gold-plated film 30 X immediately after formation of gold-plated film 30 X. As illustrated in FIG. 7 A , gold-plated film 30 X immediately after formation is an aggregate of fine crystal grains overall.
  • the heat treatment conditions (one-hour heat treatment at 150° C.) for forming metal bump 30 Y in the present embodiment are not conditions for coarsening gold-plated film 30 X up to the tip thereof by recrystallization as illustrated in FIG. 7 C , but are conditions for stopping the coarsening of the crystal grains along the way in gold-plated film 30 X as illustrated in FIG. 7 B .
  • metal bump 30 Y which has substantially two-layer structure when classified by the crystal grain size, is formed.
  • metal bump 30 Y including: first layer 30 a located close to first p-side electrode 12 and having coarsened crystal grains; and second layer 30 b located opposite to first p-side electrode 12 and having relatively small crystal grains is formed.
  • the one-hour heat treatment at 150° C. causes gold-plated film 30 X formed on first n-side electrode 13 to change into two layers having different crystal grain sizes, resulting in formation of metal bump 30 Y including: first layer 30 a located close to first n-side electrode 13 and having coarsened crystal grains; and second layer 30 b located opposite to first n-side electrode 13 and having relatively small crystal grains, as illustrated in FIG. 7 B .
  • metal bump 30 Y includes first layer 30 a and second layer 30 b having different metal crystal grain sizes. Specifically, in metal bump 30 Y, the average crystal grain size of the crystals included in first layer 30 a is larger than the average crystal grain size of the crystals included in second layer 30 b.
  • the relationship between the crystal grain size and the hardness of a metal will be described.
  • the hardness increases as the crystal grain size is reduced.
  • the hardness is reduced as the crystal grain size increases. This is because the hardness of a metal depends on the amount of plastic deformation of the metal that occurs when a load is placed thereon, and the amount of plastic deformation is affected by obstacles against multiplication and migration of dislocation, slip plane length and metal crystal orientation.
  • the slip plane of metal crystals is fixed in a specific direction of a crystal lattice; when stress is exerted, slip occurs in that direction, causing plastic deformation of the metal.
  • a metal crystalline body having a large crystal grain size has a long slip line and when stress is exerted, the stress is concentrated on crystal boundaries, and thus plastic deformation is likely to occur around the crystal boundaries. This means that the metal crystalline body having a large crystal grain size is soft.
  • an individual grain of a metal crystalline body having a small crystal grain size has a short slip plane and when stress is exerted, there are many slip planes that do not match the direction of the stress. Therefore, such crystals serve as resistance to reduce slip, lowering the likelihood of the plastic deformation of the metal. This means that the metal crystalline body having a small crystal grain size is hard.
  • the above relationship between the crystal grain size and the hardness is also true for a gold-plated film. Specifically, there is a negative correlation between the crystal grain size and the hardness of metal bump 30 Y including gold-plated film 30 X. In other words, as the average crystal grain size of the crystals included in gold-plated film 30 X increases, the hardness is reduced.
  • first layer 30 a has crystal grains coarsened due to recrystallization with heat as a result of the heat treatment of gold-plated film 30 X.
  • first layer 30 a which includes crystals having a relatively large average crystal grain size, is softer than second layer 30 b , which includes crystals having a relatively small average crystal grain size.
  • a method for measuring the crystal grain sizes of gold-plated film 30 X and metal bump 30 Y used in the present embodiment will be described below.
  • a cross section of gold-plated film 30 X or metal bump 30 Y is formed using a focused ion beam (FIB), then the intercept method is applied to an observation region observed in a scanning ion microscopy image (SIM image) from a scanning microscope, and thus the crystal grain size is measured.
  • FIB focused ion beam
  • a straight line (the dashed-dotted line in FIG. 8 ) is drawn on observation region L ⁇ L, and assuming that the number of grain boundaries crossing the straight line is number n of crystals, average crystal grain sizes d of gold-plated film 30 X and metal bump 30 Y in the horizontal and height directions are determined.
  • the horizontal direction is parallel to the upper surfaces of cover electrodes 12 d , 13 d
  • the height direction is perpendicular to the upper surfaces of cover electrodes 12 d , 13 d .
  • metal bump 30 Y including first layer 30 a and second layer 30 b having different crystal grain sizes has the cross section illustrated in FIG. 7 B .
  • the crystal grain sizes of metal bump 30 Y are measured by the above-described method; the average crystal grain size of first layer 30 a in the horizontal direction is 8 ⁇ m, the average crystal grain size of second layer 30 b in the horizontal direction is 1 ⁇ m, the average crystal grain size of first layer 30 a in the height direction is 3 ⁇ m, and the average crystal grain size of second layer 30 b in the height direction is 2 ⁇ m.
  • FIG. 9 illustrates the relationship between the average crystal grain size of a gold-plated film and the hardness of a single-layered gold-plated film.
  • a gold-plated films having a thickness of 10 ⁇ m was prepared using a non-cyanic Au plating solution having a plating temperature of 50° C. by setting the rate of deposition to 0.5 ⁇ m/min.
  • the average crystal grain size is controlled by changing the heat treatment conditions for the single-layered gold-plated film; the relationship between the average crystal grain size of the gold-plated film after the heat treatment and the hardness of the single-layered gold-plated film before the heat treatment was monitored.
  • the average crystal grain size of the gold-plated film was measured using the above-described method for measuring a crystal grain size. In this case, the average crystal grain size in the horizontal direction was measured.
  • the hardness was measured through the Vickers hardness test. Note that in the following description, unless otherwise noted, the average crystal grain size represents the average crystal grain size in the horizontal direction.
  • the hardness increases as the average crystal grain size of the crystals included in the gold-plated film is reduced. Conversely, the hardness is reduced as the average crystal grain size of the crystals included in the gold-plated film increases.
  • the hardness of the gold-plated film is reduced with an increase in the average crystal grain size of the gold-plated film, and increases with a decrease in the average crystal grain size of the gold-plated film.
  • first layer 30 a having an average crystal grain size of 8 ⁇ m is approximately 0.8 GPa.
  • the hardness of the gold-plated film is approximately 1.9 GPa.
  • second layer 30 b having an average crystal grain size of 1 ⁇ m is approximately 1.9 GPa.
  • the average crystal grain sizes are compared, and a film having a larger crystal grain size becomes a soft layer while a film having a smaller crystal grain size becomes a hard layer.
  • a gold-plated film having an average crystal grain size of 8 ⁇ m (first layer 30 a ) is softer than a gold-plated film having an average crystal grain size of 1 ⁇ m (second layer 30 b ).
  • FIG. 6 A and FIG. 6 B are diagrams illustrating the flow for mounting semiconductor element 10 on mounting substrate 20 via metal bumps 30 Y by flip-chip bonding.
  • mounting substrate 20 on which semiconductor element 10 is to be mounted is prepared.
  • substrate 21 having second p-side electrode 22 and second n-side electrode 23 formed thereon as second electrode E 2 is prepared as mounting substrate 20 .
  • substrate 21 is a ceramic substrate made from a sintered body of AlN.
  • Second p-side electrode 22 and second n-side electrode 23 which are gold-plated films, were formed using a non-cyanic Au plating solution.
  • a seed layer divided by second p-side electrode 22 and second n-side electrode 23 may be formed between substrate 21 and second p-side and n-side electrodes 22 , 23 .
  • semiconductor element 10 having metal bumps 30 Y formed thereon in advance is prepared, and holing metal tube 40 of a mounter picks up and carries semiconductor element 10 by vacuum suction in such a manner that the metal bump 30 Y side faces mounting substrate 20 .
  • holing metal tube 40 of a mounter picks up and carries semiconductor element 10 by vacuum suction in such a manner that the metal bump 30 Y side faces mounting substrate 20 .
  • 800 ⁇ m square and 100 ⁇ m thick semiconductor element 10 is used.
  • metal bump 30 Y of semiconductor element 10 and second electrode E 2 (second p-side electrode 22 and second n-side electrode 23 ) of mounting substrate 20 are brought into contact with each other and heated to approximately 200° C. in this state, and ultrasonic vibration is applied to mounting substrate 20 in the horizontal direction (the direction of arrow Y in the figure; the second direction) for 200 milliseconds while a 30N load is placed on mounting substrate 20 in the vertical direction (the direction of arrow X in the figure; the first direction) using holding metal tube 40 ; thus, metal bump 30 Y and second electrode E 2 (second p-side electrode 22 and second n-side electrode 23 ) of mounting substrate 20 are ultrasonically bonded together.
  • FIG. 10 is a timing chart for a bonding process according to Embodiment 1 when mounting semiconductor element 10 on mounting substrate 20 .
  • the horizontal axis represents time
  • the vertical axis represents a load. Note that in the horizontal axis, time on the negative side of 0 milliseconds represents a point in time before the start of the processing, and 0 milliseconds represents the point in time of the start of the processing.
  • the load gradually increases in the period of 100 milliseconds (STEP 1 ) after the start of the bonding process for semiconductor element 10 and mounting substrate 20 .
  • STEP 1 no ultrasonic waves are applied, but only the load is placed.
  • STEP 2 ultrasonic waves are applied while the load is maintained at a constant level.
  • Semiconductor element 10 and mounting substrate 20 are ultrasonically bonded via metal bump 30 Y through such a bonding process illustrated in the timing chart.
  • FIG. 11 A to FIG. 11 E illustrate cross sections of portions of semiconductor element 10 and mounting substrate 20 that are bonded together, specifically, portions of two adjacent metal bump 30 Y and the second electrode of mounting substrate 20 that are bonded together, at a point in time before the start of the bonding process for semiconductor element 10 and mounting substrate 20 and 0 milliseconds, 100 milliseconds, 300 milliseconds, and 400 milliseconds after the start of the bonding process.
  • FIG. 11 A to FIG. 11 E illustrate only the bonded portions on second p-side electrode 22 of second electrode E 2 of mounting substrate 20 , the same is true for the bonded portions on second n-side electrode 23 of second electrode E 2 .
  • FIG. 11 A illustrates metal bumps 30 Y and second electrode E 2 of mounting substrate 20 before the bonding process for semiconductor element 10 and mounting substrate 20 .
  • the crystal grains of gold (Au) included in first layer 30 a and second layer 30 b of each metal bump 30 Y have approximately the same grain size in each layer.
  • metal bumps 30 Y have the same shape, specifically, the shape of a rectangular prism.
  • FIG. 11 B illustrates metal bumps 30 Y and second electrode E 2 of mounting substrate 20 at the start (0 milliseconds) of the bonding process for semiconductor element 10 and mounting substrate 20 .
  • FIG. 11 B illustrates the state where the tip surface of metal bump 30 Y formed on semiconductor element 10 is brought into contact with second electrode E 2 of mounting substrate 20 .
  • first layer 30 a and second layer 30 b of each metal bump 30 Y have approximately the same grain size as in FIG. 11 A .
  • STEP 1 in FIG. 10 the process in STEP 1 in FIG. 10 is performed. Specifically, in STEP 1 , a load (mounting load) is placed on semiconductor element 10 and mounting substrate 20 , between which the plurality of metal bumps 30 Y are sandwiched, in a direction perpendicular to the principal surface of mounting substrate 20 .
  • the load gradually increases in STEP 1 . Accordingly, as the load is placed, entire first layer 30 a , which is relatively softer than second layer 30 b , is deformed and spread horizontally. At this time, second layer 30 b , which is relatively harder than first layer 30 a , is not deformed, but maintains approximately the same shape as that before the start of the process. As a result, the shape of each metal bump 30 Y becomes an approximate wide top shape with horizontally spreading first layer 30 a , as illustrated in FIG. 11 C . Note that the second electrode (second p-side electrode 22 and second n-side electrode 23 ) of mounting substrate 20 maintains the same surface shape as that before the start of the process.
  • first layers 30 a of adjacent metal bumps 30 Y come into contact with each other.
  • second layers 30 b of adjacent metal humps 30 Y are not in contact with each other.
  • FIG. 11 C illustrates metal bumps 30 Y and second electrode E 2 of mounting substrate 20 that are bonded together at the transition from STEP 1 to STEP 2 in FIG. 10 (approximately 100 milliseconds later after the start of the process).
  • the load increases from load 0 N to load 30 N in the form of a linear function in a 100-millisecond period in STEP 1 in the present embodiment, this is not limiting.
  • STEP 2 as illustrated in FIG. 11 D , a predetermined load is placed on semiconductor element 10 and mounting substrate 20 , between which metal bumps 30 Y are sandwiched, in a direction perpendicular to the principal surface of mounting substrate 20 (the direction of arrow X in the figure), and ultrasonic waves are applied in a direction horizontal to the principal surface of mounting substrate 20 (the direction of arrow Y in the figure).
  • ultrasonic vibration is applied in the state where the same load as the last load in STEP 1 is placed on semiconductor element 10 and mounting substrate 20 between which the plurality of metal bumps 30 Y are sandwiched.
  • FIG. 11 D illustrates metal bumps 30 Y and second electrode E 2 of mounting substrate 20 that are bonded together in the middle of STEP 2 in FIG. 10 (approximately 300 milliseconds later after the start of the process and approximately 200 milliseconds later after the start of the ultrasonic vibration).
  • metal bump 30 Y vibrates in the direction horizontal to mounting substrate 20 , and the interface at which second layer 30 b of metal bump 30 Y and second electrode E 2 of mounting substrate 20 are in contact is heated by friction, leading to solid-phase bonding and integration of metal bump 30 Y and second electrode E 2 of mounting substrate 20 .
  • the ultrasonic vibration with the load being placed causes metal bump 30 Y to rub against second electrode E 2 , and thus a portion at the interface between metal bump 30 Y and second electrode E 2 is recrystallized.
  • each metal bump 30 Y is approximately in the shape of an hourglass with entire first layer 30 a spreading horizontally and a portion of second layer 30 b that is bonded to second electrode E 2 spreading horizontally, as illustrated in FIG. 11 E .
  • each metal bump 30 Y has a constricted shape with a center portion narrowing along the entire perimeter.
  • adjacent metal bumps 30 Y come into contact with each other not only in first layers 30 a , but also partially in second layers 30 b , as illustrated in FIG. 11 E .
  • portions of second layers 30 b of adjacent metal humps 30 Y that are bonded to second electrode E 2 come into contact with each other.
  • FIG. 11 E illustrates metal bumps 30 Y and second electrode E 2 of mounting substrate 20 that are bonded together at the end of STEP 2 in FIG. 10 (approximately 400 milliseconds later after the start of the process and approximately 300 milliseconds later after the start of the ultrasonic vibration).
  • third layer 30 c is formed in a portion of second layer 30 b of metal bump 30 Y as a layer including coarsened Au crystal grains resulting from integration of the Au crystal grains from second layer 30 b and the Au crystal grains from second electrode E 2 .
  • metal bump 30 Y in which first layer 30 a and third layer 30 c have greater widths (diameters) than second layer 30 b is formed, first layers 30 a of adjacent metal bumps 30 Y are connected to each other, and third layers 30 c of adjacent metal bumps 30 Y are connected to each other.
  • the plurality of metal bumps 30 Y formed between semiconductor element 10 and mounting substrate 20 are coupled to each other, not at center portions, but at upper and lower portions only, resulting in bonding metal layer 30 having hollow gap 33 .
  • bonding metal layer 30 in semiconductor device 1 is a metal layer obtained by deforming and integrating the plurality of metal bumps 30 Y.
  • bonding metal layer 30 is formed by connecting first layers 30 a of metal bumps 30 Y to each other and connecting third layers 30 c of metal bumps 30 Y to each other, as illustrated in FIG. 11 E .
  • Gap 33 inside bonding metal layer 30 is a hollow region formed as a result of second layers 30 b of metal bumps 30 Y failing to be connected to each other.
  • FIG. 12 is a cross-sectional view illustrating a method for manufacturing conventional semiconductor device 100 disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429.
  • FIG. 13 is a diagram illustrating the configurations of semiconductor device 1 according to Embodiment 1 before and after mounting.
  • (a) is a cross-sectional view in which semiconductor element 10 has not yet been mounted on mounting substrate 20
  • (b) is a cross-sectional view in which semiconductor element 10 has already been mounted on mounting substrate 20 .
  • conventional semiconductor device 100 is manufactured by bonding, via the plurality of metal bumps 300 Y, semiconductor element 10 including semiconductor multilayer structure 11 and first electrode E 1 and mounting substrate 20 including substrate 21 and second electrode E 2 .
  • semiconductor element 10 having the plurality of metal bumps 300 Y formed thereon is mounted on mounting substrate 20 .
  • the mounting load is locally concentrated on contact surface S 1 between first electrode E 1 of semiconductor element 10 and metal bumps 300 Y and the mounting substrate, and the mounting load is locally concentrated on contact surface S 2 between second electrode E 2 of mounting substrate 20 and metal bumps 300 Y.
  • This may result in damage to each of first electrode E 1 of semiconductor element 10 and second electrode E 2 of mounting substrate 20 due to metal bumps 300 Y, causing a risk of electrode failures of first electrode E 1 and second electrode E 2 .
  • bonding metal layer 30 is formed so as to include gap 33 inside, as illustrated in FIG. 13 .
  • the plurality of metal bumps 30 are deformed in such a manner that upper portions of adjacent metal bumps 30 Y come into contact with each other, lower portions of adjacent metal bumps 30 Y come into contact with each other, and hollow gap 33 is left, as illustrated in FIG. 11 A to FIG. 11 E referred to above.
  • This makes it possible to evenly distribute the load for mounting that is placed on each of the entire surface of first electrode E 1 of semiconductor element 10 and the entire surface of second electrode E 2 of mounting substrate 20 .
  • semiconductor device 1 With semiconductor device 1 according to the present embodiment, mounting damage due to electrode failures of first electrode E 1 and second electrode E 2 can be reduced; therefore, it is possible to provide semiconductor device 1 exceptionally reliable in the long run.
  • gap 33 inside bonding metal layer 30 extends linearly along the outer side of first electrode E 1 of semiconductor element 10 .
  • gap 33 of bonding metal layer 30 extends along the outer side of first electrode E 1 of semiconductor element 10 , it is considered that the plurality of metal bumps 30 Y, which become bonding metal layer 30 , have been arranged neatly in a matrix before mounting.
  • metal bumps 30 Y are arranged neatly in a matrix, the load for mounting that is placed on the entire surface of each of first electrode E 1 and second electrode E 2 can be evenly distributed as compared to the case where metal bumps 30 Y are arranged at random. Accordingly, localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 can be made small, and thus it is possible to reduce damage to first electrode E 1 and second electrode E 2 that may be caused by metal bumps 30 Y.
  • gap 33 extends along the outer side of first electrode E 1 . It is sufficient that gap 33 generally extend along the outer side of first electrode E 1 ; for example, even if the outer side of first electrode E 1 are not perfectly linear with small dents in a part of the outer side, linear gap 33 can be described as extending along the outer side of first electrode E 1 . In other words, as long as gap 33 extends along the outer side of first electrode E 1 from a broad perspective, such a situation is included in the concept of gap 33 extending along the outer side of first electrode E 1 .
  • gap 33 inside bonding metal layer 30 is parallel to the outer side of first electrode E 1 .
  • metal bumps 30 Y having the same width have been arranged neatly in a matrix before bonding.
  • the load for mounting that is placed on the entire surface of each of first electrode E 1 and second electrode E 2 can be evenly distributed as compared to the case where metal bumps 30 Y having different widths are arranged. Accordingly, localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 can be made small, and thus it is possible to reduce damage to first electrode E 1 and second electrode E 2 that may be caused by metal bumps 30 Y.
  • height H of gap 33 inside bonding metal layer 30 is at least 10% of the height of bonding metal layer 30 .
  • the height of gap 33 is set to at least 10% of the height of bonding metal layer 30 as mentioned above, the size of gap 33 can be maintained to some extent. With this, the load for mounting can be effectively distributed, and thus it is possible to effectively reduce localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 .
  • FIG. 14 A to FIG. 14 O are cross-sectional views each illustrating a portion of a cross section in the M cross section in FIG. 13 [AFTER MOUNTING].
  • gap 33 inside bonding metal layer 30 is a continuous void, but this is not limiting.
  • gap 33 A inside bonding metal layer 30 may include a plurality of voids 33 a in the form of dots (spots).
  • gap 33 A may include first direction void L 1 made up of a plurality of voids 33 a arranged linearly along a first direction (for example, the row direction).
  • first direction void L 1 is made up of the plurality of voids 33 a arranged in a straight line.
  • the plurality of voids 33 a included in gap 33 B may have different shapes, as illustrated in FIG. 14 B .
  • the plurality of voids 33 a are not required to be continuous; each of the plurality of voids 33 a may be partially in the form of a line, a dot, or the like.
  • gaps 33 A, 33 B in first direction void L 1 extend linearly along the outer side of first electrode E 1 .
  • gaps 33 A, 33 B are in the form of a dashed line and are parallel to one outer side of first electrode E 1 .
  • gap 33 C inside bonding metal layer 30 may have first direction void L 1 that is one continuous void, as illustrated in FIG. 14 C .
  • gap 33 C extends linearly along the outer side of first electrode E 1 .
  • gap 33 C in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 .
  • an end of gap 33 C may be exposed from the outer side of first electrode E 1 .
  • gap 33 inside bonding metal layer 30 is made up of voids in the form of two orthogonal straight lines, but this is not limiting.
  • gap 33 D inside bonding metal layer 30 may be made up of two or more orthogonal straight lines, as illustrated in FIG. 14 D .
  • gap 33 D may include: first direction void L 1 formed linearly along the first direction; and second direction void L 2 formed linearly along a second direction (for example, the column direction) different from the first direction.
  • first direction void L 1 is in the form of a straight line along the first direction
  • second direction void L 2 is in the form of a straight line along the second direction that is orthogonal to the first direction.
  • gap 33 D extends linearly along the outer side of first electrode E 1 .
  • gap 33 D in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 .
  • Gap 33 D in second direction void L 2 is in the form of a straight line and is parallel to another outer side of first electrode E 1 .
  • gap 33 D includes a plurality of lines of gaps at a fixed interval. Specifically, gap 33 D in first direction void L 1 forms two or more lines at a fixed interval. Gap 33 D in second direction void L 2 forms two or more lines at a fixed interval.
  • first direction in first direction void L 1 and the second direction in second direction void L 2 are orthogonal in FIG. 14 D , this is not limiting as long as the first direction and the second direction intersect with each other.
  • the plurality of voids in the form of straight lines included in first direction void L 1 and the plurality of voids in the form of straight lines included in second direction void L 2 are not required to be all in the same direction (in other words, in parallel), but some of the plurality of voids in the form of straight lines may extend in a different direction.
  • gap 33 D is made up of the plurality of voids formed along both the first and second directions, but this is not limiting.
  • gap 33 E may be made up of a plurality of voids formed along only one of the first and second directions, as illustrated in FIG. 14 E .
  • an end of gap 33 D may be exposed from the outer side of first electrode E 1 . All the ends of gap 33 D may be exposed from the outer side of first electrode E 1 , or some of the ends of gap 33 D may be exposed from the outer side of first electrode E 1 .
  • gap 33 E includes only first direction void L 1 made up of voids in the form of straight lines extending in the first direction.
  • a portion of gap 33 E may include a plurality of voids 33 a having a width different from the width of a straight portion, as illustrated in FIG. 14 E .
  • the voids in the form of straight lines may include a portion having a different width.
  • gap 33 E extends linearly along the outer side of first electrode E 1 .
  • gap 33 E in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 .
  • gap 33 E includes a plurality of lines of gaps at a fixed interval.
  • gap 33 E in first direction void L 1 forms two or more lines at a fixed interval.
  • an end of gap 33 E may be exposed from the outer side of first electrode E 1 . All the ends of gap 33 E may be exposed from the outer side of first electrode E 1 , or some of the ends of gap 33 E may be exposed from the outer side of first electrode E 1 .
  • gaps 33 D, 33 E are a combination of voids in the form of straight lines, but this is not limiting.
  • gap 33 F may be made up of a plurality of voids 33 a aligned in the form of dots, as illustrated in FIG. 14 F .
  • gap 33 F may include: first direction void L 1 made up of a plurality of voids 33 a arranged linearly along the first direction; and second direction void L 2 made up of a plurality of voids 33 a arranged linearly along the second direction that is orthogonal to the first direction.
  • each of first direction void L 1 and second direction void L 2 is made up of the plurality of voids 33 a arranged in a straight line.
  • gap 33 F extends linearly along the outer side of first electrode E 1 .
  • gap 33 F in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 .
  • Gap 33 F in second direction void L 2 is in the form of a straight line and is parallel to another outer side of first electrode E 1 .
  • gap 33 F includes a plurality of lines of gaps at a fixed interval. Specifically, gap 33 F in first direction void L 1 forms two or more lines at a fixed interval. Gap 33 F in second direction void L 2 forms two or more lines at a fixed interval.
  • the plurality of lines of first line voids L 1 and the plurality of lines of second line voids L 2 are each present at the fixed interval, but this is not limiting; only either the plurality of rows of first line voids L 1 or the plurality of columns of second line voids L 2 may be present at the fixed interval, as with gap 33 G illustrated in FIG. 14 G . Note that in the case of gap 33 G illustrated in FIG. 14 G , only the plurality of lines of first direction voids L 1 are present at the fixed interval.
  • All the plurality of voids 33 a included in gap 33 F are in the form of dots as illustrated in FIG. 14 F , but this is not limiting; the plurality of voids 33 a included in gap 33 H may have different shape, as illustrated in FIG. 14 H .
  • the plurality of voids 33 a are not required to be continuous; each of the plurality of voids 33 a may be partially in the form of a line, a dot, or the like.
  • Bonding metal layer 30 according to Embodiment 1 described above is formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a rectangular prism, as illustrated in FIG. 2 B , but this is not limiting.
  • bonding metal layer 30 may be formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a circular column, as illustrated in FIG. 14 I to FIG. 14 M .
  • bonding metal layer 30 in FIG. 14 I to FIG. 14 K is formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a circular column and aligned in a grid pattern.
  • metal bump 30 Y in the shape of a circular column is formed of a gold-plated film in the shape of a circle having a diameter of 25 ⁇ m as seen from the top with a height of 8 ⁇ m.
  • gap 33 I may be made up of voids in a grid pattern of two orthogonal straight lines, as illustrated in FIG. 14 I . Note that also in FIG. 14 I , gap 33 I extends linearly along the outer side of first electrode E 1 . Specifically, gap 33 I in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap 33 I in second direction void L 2 is in the form of a straight line and is parallel to another outer side of first electrode E 1 .
  • Gap 33 J may be made up of a plurality of voids, as illustrated in FIG. 14 J . Note that also in FIG. 14 J , gap 33 J extends linearly along the outer side of first electrode E 1 . Specifically, gap 33 I in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap 33 J in second direction void L 2 is in the form of a plurality of dots and is parallel to another outer side of first electrode E 1 .
  • Gap 33 K may be made up of voids 33 a in the form of a plurality of dots aligned in a matrix, as illustrated in FIG. 14 K . Note that also in FIG. 14 K , gap 33 K extends linearly along the outer side of first electrode E 1 . Specifically, in FIG. 14 K , first direction gap L 1 and second direction gap L 2 are made up of the plurality of voids 33 a arranged in the form of a dashed line. Gap 33 K in first direction void L 1 is parallel to one outer side of first electrode E 1 , and gap 33 K in second direction void L 2 is parallel to another outer side of first electrode E 1 .
  • Bonding metal layer 30 may be formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a circular column and aligned in a staggered pattern, as illustrated in FIG. 14 L and FIG. 14 M .
  • gap 33 L may be made up of voids in a staggered grid pattern, as illustrated in FIG. 14 L .
  • gap 33 L extends linearly along the outer side of first electrode E 1 .
  • gap 33 L in first direction void L 1 is in the form of a straight line and is parallel to one outer side of first electrode E 1 .
  • Gap 33 L in second direction void L 2 is in the form of a dashed line and is parallel to another outer side of first electrode E 1 .
  • Gap 33 M may be made up of voids 33 a in the form of a plurality of dots aligned in a matrix, as illustrated in FIG. 14 M . Note that also in FIG. 14 M , gap 33 M extends linearly along the outer side of first electrode E 1 . Specifically, in FIG. 14 M , first direction gap L 1 and second direction gap L 2 are made up of the plurality of voids 33 a arranged in the form of a dashed line. Gap 33 M in first direction void L 1 is parallel to one outer side of first electrode E 1 , and gap 33 M in second direction void L 2 is parallel to another outer side of first electrode E 1 .
  • bonding metal layer 30 is formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a circular column, but this is not limiting.
  • bonding metal layer 30 may be formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a hexagonal column, as illustrated in FIG. 14 N and FIG. 14 O .
  • bonding metal layer 30 in FIG. 14 N and FIG. 14 O is formed by deforming and integrating the plurality of metal bumps 30 Y each in the shape of a hexagonal column and aligned in a staggered pattern.
  • gap 33 N may be made up of voids in a staggered grid pattern, as illustrated in FIG. 14 N . Note that also in FIG. 14 N , gap 33 N extends linearly along the outer side of first electrode E 1 . Specifically, gap 33 N in first direction void L 1 is in the form of a dashed line and is parallel to one outer side of first electrode E 1 .
  • Gap 33 O may be made up of voids 33 a in the form of a plurality of dots, as illustrated in FIG. 14 O . Note that also in FIG. 14 O , gap 33 O extends linearly along the outer side of first electrode E 1 . Specifically, first direction gap L 1 is made up of the plurality of voids 33 a arranged in the form of a dashed line. Gap 33 O in first direction void L 1 is parallel to one outer side of first electrode E 1 .
  • gap 33 I to gap 33 O include a plurality of lines of gaps at a fixed interval. Specifically, gap 33 I to gap 33 O in at least one of first direction void L 1 and second direction void L 2 form two or more lines at a fixed interval.
  • gap 33 D to gap 33 O are parallel to the outer side of first electrode E 1 and form two or more lines at a fixed interval, as illustrated in FIG. 14 D to FIG. 14 O , it is considered that metal bumps 30 Y having the same shape have been arranged neatly in a repeating pattern.
  • metal bumps 30 Y having the same shape are arranged neatly in a repeating pattern, the load for mounting that is placed on the entire surface of each of first electrode E 1 and second electrode E 2 can be evenly distributed as compared to the case where metal bumps 30 Y having different shapes are arranged. Accordingly, localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 can be made small, and thus it is possible to reduce damage to first electrode E 1 and second electrode E 2 that may be caused by metal bumps 30 Y.
  • semiconductor device 1 for example, in the case of applying a plating bump technique with high design flexibility for the thickness and the bonding area, it is possible to lessen damage to first electrode E 1 of semiconductor element 10 and second electrode E 2 of mounting substrate 20 at the time of mounting semiconductor element 10 on mounting substrate 20 by flip-chip bonding. This makes it possible to reduce mounting damage including electrode failures such as damage or peeling of first electrode E 1 and second electrode E 2 at the time of mounting semiconductor element 10 on mounting substrate 20 . Thus, semiconductor device 1 exceptionally reliable in the long run can be obtained.
  • Such semiconductor device 1 exceptionally reliable in the long run is suitable as a compact, highly integrated vehicle-mounted light source with large electric current.
  • FIG. 15 is a cross-sectional view illustrating the configurations of semiconductor device 2 according to Embodiment 2 before and after mounting.
  • (a) is a cross-sectional view in which semiconductor element 10 has not yet been mounted on mounting substrate 20
  • (b) is a cross-sectional view in which semiconductor element 10 has already been mounted on mounting substrate 20 .
  • the left diagram is a cross-sectional view taken along line X-X in the right diagram.
  • the outer side of first electrode E 1 of semiconductor element 10 is a straight line only, but, as illustrated in FIG. 15 , in semiconductor device 2 according to the present embodiment, the outer side of first electrode E 1 of semiconductor element 10 at least partially includes a curved section.
  • the outer side of first p-side electrode 12 includes arc-shaped curved sections at four corners, and the outer sides of four island-shaped first n-side electrodes 13 on the first p-side electrode 12 side include arc-shaped curved sections.
  • first electrode E 1 With the outer side of first electrode E 1 being bent in a curve as mentioned above, electric field concentration can be less than that with first electrode E 1 being bent at a right angle. Accordingly, electric current concentration can be reduced.
  • semiconductor device 2 at the time of mounting semiconductor element 10 having the plurality of metal bumps 30 Y formed thereon on mounting substrate 20 , the plurality of metal bumps 30 Y are deformed and integrated to form bonding metal layer 30 including gap 33 inside, as in semiconductor device 1 according to Embodiment 1 described above.
  • first electrode E 1 of semiconductor element 10 and second electrode E 2 of mounting substrate 20 it is possible to evenly distribute the load for mounting that is placed on first electrode E 1 of semiconductor element 10 and second electrode E 2 of mounting substrate 20 , and thus localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 at the time of mounting can be made small. As a result, it is possible to reduce damage to first electrode E 1 and second electrode E 2 that may be caused by metal bumps 30 Y. Accordingly, with semiconductor device 2 according to the present embodiment, mounting damage due to electrode failures of first electrode E 1 and second electrode E 2 can be reduced; therefore, it is possible to provide semiconductor device 2 exceptionally reliable in the long run.
  • FIG. 16 is an enlarged view of the M cross section in (b) in FIG. 15 .
  • the proportion of the area taken up by gap 33 in a plan view is lower in a region close to p-n electrode opposed portion PN across which first p-side electrode 12 and first n-side electrode 13 are opposed to each other than in a region away from p-n electrode opposed portion PN.
  • the region close to p-n electrode opposed portion PN is a region located at distance D of between 50 ⁇ m and 100 ⁇ m, inclusive, from p-n electrode opposed portion PN in the present embodiment.
  • the amount of heat generated at p-n electrode opposed portion PN is largest; with p-n electrode opposed portion PN as a reference, a region located at distance D of between 50 ⁇ m and 100 ⁇ m, inclusive, from p-n electrode opposed portion PN becomes a heat-concentrated region.
  • gap 33 in a region close to p-n electrode opposed portion PN having a low area proportion is that metal bump 30 Y present in the region close to p-n electrode opposed portion PN, which becomes a heat-concentrated region, is large in size, resulting in high heat conduction.
  • gap 33 inside bonding metal layer 30 is a combination of voids in the form of straight lines, but this is not limiting.
  • gap 33 may be made up of a plurality of voids 33 a aligned in the form of dots, as illustrated in FIG. 17 .
  • Gap 33 illustrated in FIG. 17 is formed by deforming metal bumps 30 Y more heavily than when forming gap 33 illustrated in FIG. 16 .
  • gap 33 may be formed into the shape of a dot instead of a line.
  • first electrode E 1 includes four first n-side electrodes 13 in the form of islands, but this is not limiting.
  • first n-side electrode 13 may be provided along the entire perimeter of the electrode forming surface of semiconductor element 10 so as to surround entire first p-side electrode 12 , as illustrated in FIG. 18 .
  • first n-side electrode 13 in such a pattern may be used in another embodiment.
  • FIG. 19 is a cross-sectional view illustrating semiconductor device 2 A according to the variation of Embodiment 2.
  • (a) is a cross-sectional view in which semiconductor element 10 has not yet been mounted on mounting substrate 20
  • (b) is a cross-sectional view in which semiconductor element 10 has already been mounted on mounting substrate 20 .
  • the left diagram is a cross-sectional view taken along line X-X in the right diagram.
  • the outer side of first electrode E 1 of semiconductor element 10 at least partially includes a curved section, as in semiconductor device 2 illustrated in FIG. 15 .
  • gap 33 inside bonding metal layer 30 extends linearly along the outer side of first electrode E 1 in a plan view of bonding metal layer 30 .
  • gap 33 is in the form of an arc-shaped curve and extends along the curved section provided on the outer side at a corner of first p-side electrode 12 .
  • gap 33 of bonding metal layer 30 extends along the outer side of first electrode E 1 of semiconductor element 10 , it is considered that the plurality of metal bumps 30 Y, which become bonding metal layer 30 , have been arranged neatly before mounting.
  • metal bumps 30 Y are arranged neatly, the load for mounting that is placed on the entire surface of each of first electrode E 1 and second electrode E 2 can be evenly distributed as compared to the case where metal bumps 30 Y are arranged at random. Accordingly, localized stress that metal bumps 30 Y give to first electrode E 1 and second electrode E 2 can be made small, and thus it is possible to reduce damage to first electrode E 1 and second electrode E 2 that may be caused by metal bumps 30 Y.
  • semiconductor device 2 A exceptionally reliable in the long run can be obtained.
  • FIG. 20 is a cross-sectional view illustrating the configurations of semiconductor device 3 according to Embodiment 3 before and after mounting.
  • (a) is a cross-sectional view in which semiconductor element 10 has not yet been mounted on mounting substrate 20
  • (b) is a cross-sectional view in which semiconductor element 10 has already been mounted on mounting substrate 20 .
  • the left diagram is a cross-sectional view taken along line X-X in the right diagram.
  • semiconductor device 3 according to the present embodiment is different from semiconductor device 2 according to Embodiment 2 described above in that gap 33 inside bonding metal layer 30 has a different shape in a plan view. Specifically, in semiconductor device 3 according to the present embodiment, gap 33 is at least partially radial in shape in a plan view of bonding metal layer 30 .
  • gap 33 is made up of a plurality of voids in the form of straight lines radially extending from a center portion of one side of first p-side electrode 12 of first electrode E 1 toward the opposite side.
  • bonding metal layer 30 is formed by deforming the plurality of metal bumps 30 Y so as to include gap 33 inside, as in semiconductor device 2 according to Embodiment 2 described above. Accordingly, mounting damage due to electrode failures of first electrode E 1 and second electrode E 2 can be reduced; therefore, it is possible to provide semiconductor device 3 exceptionally reliable in the long run.
  • gap 33 is at least partially radial in shape. With this, at the time of sealing entire semiconductor device 30 using resin, gap 33 can be easily filled with the resin. This means that gap 33 may be at least partially filled with resin 34 as in semiconductor device 3 A illustrated in FIG. 21 .
  • gap 33 is made up of radial voids
  • the supplied drops of resin 34 infiltrate into gap 33 radially from one point at which ends of the plurality of radial voids are gathered.
  • the distance of infiltration of resin 34 can be made shortest, meaning that the occurrence of incomplete filling of gap 33 with resin 34 can be reduced and all the voids included in gap 33 can be easily filled with resin 34 , as in semiconductor device 3 A illustrated in FIG. 21 .
  • resin 34 can be thermally cured, for example, by one-hour heating at 150° C.
  • Resin 34 which fills gap 33 may have thermal conductivity higher than the thermal conductivity of air.
  • a silicone rein can be used a resin 34 .
  • microparticles having high thermal conductivity or light-reflective microparticles may be dispersed in resin 34 .
  • titanium oxide (TiO 2 ) microparticles can be used as light-reflective microparticles having high thermal conductivity.
  • gap 33 is made up of the plurality of voids in the form of straight lines radially extending from the center portion of one side of first p-side electrode 12 , but this is not limiting.
  • gap 33 may be made up of a plurality of voids in the form of straight lines radially extending in every direction from the center portion of first p-side electrode 12 , as illustrated in FIG. 22 .
  • the proportion of the area taken up by gap 33 is lower in a region close to p-n electrode opposed portion PN than in a region away from p-n electrode opposed portion PN. With this, it is possible to improve heat dissipation properties, and thus semiconductor device 3 yet more exceptionally reliable in the long run can be obtained.
  • gap 33 may include a void branching from a portion of a plurality of radially extending voids or some or all of the plurality of radially extending voids in gap 33 may be curved.
  • first electrode E 1 of semiconductor element 10 is configured in such a manner that the electrode area of first p-side electrode 12 is larger than the electrode area of first n-side electrode 13 , but this is not limiting. Specifically, the electrode area of first n-side electrode 13 may be larger than the electrode area of first p-side electrode 12 . However, in the case where semiconductor element 10 is a LED chip, the p-side tends to have a higher temperature than the n-side, and thus the electrode area of first p-side electrode 12 may be set larger than the electrode area of first n-side electrode 13 .
  • gap 33 formed inside bonding metal layer 30 is present in only first bonding metal layer 31 among first bonding metal layer 31 and second bonding metal layer 32 , but this is not limiting.
  • gap 33 may be present in both first bonding metal layer 31 and second bonding metal layer 32 or may be present in only second bonding metal layer 32 among first bonding metal layer 31 and second bonding metal layer 32 .
  • the plurality of metal bumps 30 Y for forming gap 33 the plurality of metal bumps 30 Y may be provided on only the p side as in each of the above embodiments, but the plurality of metal bumps 30 Y may be provided on both the n side and the p side or may be provided on only the n side.
  • gaps 33 , 33 A to 330 are not particularly limited.
  • the vertical positions of gaps 33 , 33 A to 33 O are not particularly limited.
  • the voids in each place may be in layers in the thickness direction of bonding metal layer 30 .
  • LED chip is exemplified as semiconductor element 10 in each of the above embodiments, this is not limiting; other solid-state light-emitting elements such as a laser element may be used.
  • semiconductor element 10 is not limited to a light-emitting element.
  • semiconductor element 10 may be a power semiconductor element such as a compound field effect transistor using GaN, SiC, or the like.
  • the semiconductor device according to the present disclosure is exceptionally reliable in the long run and is useful for various devices including vehicle-mounted application.

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US20230146321A1 (en) 2023-05-11
US12087897B2 (en) 2024-09-10
JP6754921B1 (ja) 2020-09-16
US20210104652A1 (en) 2021-04-08
JPWO2020121793A1 (ja) 2021-02-15
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EP3872876A1 (fr) 2021-09-01
CN113506849B (zh) 2022-07-08
CN113506849A (zh) 2021-10-15
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JP6788146B2 (ja) 2020-11-18
EP3872876B1 (fr) 2023-06-14

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