TWI750316B - 1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法 - Google Patents

1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法 Download PDF

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TWI750316B
TWI750316B TW107104758A TW107104758A TWI750316B TW I750316 B TWI750316 B TW I750316B TW 107104758 A TW107104758 A TW 107104758A TW 107104758 A TW107104758 A TW 107104758A TW I750316 B TWI750316 B TW I750316B
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fin
shaped
active region
mandatory
field effect
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TW107104758A
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TW201935619A (zh
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李國興
盛義忠
薛勝元
康智凱
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聯華電子股份有限公司
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Priority to US15/912,526 priority patent/US10580883B2/en
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Abstract

一種形成強制性鰭狀堆疊反向器的方法，包含有下述步驟。首先，提供一基底，其中基底包含一第一鰭狀結構、一第二鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區，且第一鰭狀結構、第二鰭狀結構以及第三鰭狀結構並排排列。接著，進行一移除主動區內鰭狀結構製程，移除在第一主動區中的至少一部分的第二鰭狀結構。接續，形成一第一閘極，沿一第二方向跨設第一主動區中的第一鰭狀結構以及第三鰭狀結構。本發明更提供以此方法形成的一1-1強制性鰭狀堆疊反向器。

Description

1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器 的方法
本發明是關於一種強制性堆疊反向器及其形成方法，尤指一種1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法。
近年金屬氧化物半導體場效電晶體MOSFET(Metal Oxide Semiconductor Field Effect Transistor)係作為大尺寸積體電路的主要構成要素。因應積體電路尺寸微縮的要求，亦尋求更小尺寸的金屬氧化物半導體場效電晶體的製備方法。然而，當金屬氧化物半導體場效電晶體的縮小化能遵循特定規則達成時，隨著各種技術的更替亦產生各種問題，其中包括難以同時抑制金屬氧化物半導體場效電晶體的短通道效應並確保對於金屬氧化物半導體場效電晶體的高電流驅動力。因而，更嘗試其他例如能提升以往積體電路中金屬氧化物半導體場效電晶體的積極度的方法。
本發明提出一種1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法，其移除部分主動區內的鰭狀結構，以使強制性鰭狀堆疊反向器能 形成於更小面積的主動區中。
本發明提供一種形成強制性鰭狀堆疊反向器的方法，包含有下述步驟。首先，提供一基底，其中基底包含一第一鰭狀結構、一第二鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區，且第一鰭狀結構、第二鰭狀結構以及第三鰭狀結構並排排列。接著，進行一移除主動區內鰭狀結構製程，移除在第一主動區中的至少一部分的第二鰭狀結構。接續，形成一第一閘極，沿一第二方向跨設第一主動區中的第一鰭狀結構以及第三鰭狀結構。
本發明提供一種1-1強制性鰭狀堆疊反向器，包含有一基底以及一第一閘極。基底包含一第一鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區，以及一第四鰭狀結構以及一第六鰭狀結構沿第一方向跨設一第二主動區，其中第一鰭狀結構、第三鰭狀結構、第四鰭狀結構以及第六鰭狀結構並排排列。接續，一第一閘極沿一第二方向跨設第一主動區中的第一鰭狀結構以及第三鰭狀結構，以及第二主動區中的第四鰭狀結構以及第六鰭狀結構。
基於上述，本發明提供一種1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法，其先在基底中形成複數個鰭狀結構，此些鰭狀結構包含一第一鰭狀結構、一第二鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區；接著再進行一移除主動區內鰭狀結構製程，移除在第一主動區中的第二鰭狀結構；之後再形成一第一閘極跨設此些鰭狀結構，如此一來則可在更小面積的主動區中形成1-1強制性鰭狀堆疊反向器。
10:遮罩層
20:絕緣結構
110:基底
112、112b、112c:鰭狀結構
112a、112a’:第一鰭狀結構
112b、112b’:第二鰭狀結構
112b’’:第二鰭狀凹槽
112c、112c’:第三鰭狀結構
112d、112d’:第四鰭狀結構
112e、112e’:第五鰭狀結構
112e’’:第五鰭狀凹槽
112f、112f’:第六鰭狀結構
112g、112h、112i、112j、112k、112l、112m、112n:犧牲鰭狀結構
112g’、112h’、112i’、112i’’、112j’、112j’’、112k’、112l’、112m’、R:鰭狀凹槽
120:第一閘極
120a’、120b’、120c’:相對位置
130:金屬內連線結構
AA’、BB’、CC’、aa’、bb’、cc’:線段
d1:第一方向
d2:第二方向
E1:第一主動區
E2:第二主動區
F、F1、F2、G:1-1強制性堆疊反向器
h1、h2:高度
M1:第一鰭狀場效電晶體
M2:第二鰭狀場效電晶體
M3:第三鰭狀場效電晶體
M4:第四鰭狀場效電晶體
P1:移除主動區外鰭狀結構製程
P2:鰭狀結構切割製程
P3:移除主動區內鰭狀結構製程
P4:閘極切割製程
V:通孔
w1、w2:寬度
第1-5圖係繪示本發明一實施例之形成強制性鰭狀堆疊反向器的方法之俯視示意圖及剖面示意圖。
第6圖係繪示本發明一實施例之1-1強制性堆疊反向器之俯視示意圖。
第7圖係繪示本發明一實施例之1-1強制性堆疊反向器之尺寸示意圖。
第1-5圖係繪示本發明一實施例之形成強制性鰭狀堆疊反向器的方法之俯視示意圖及剖面示意圖，其中第1-5圖之左圖為形成強制性鰭狀堆疊反向器的方法之俯視示意圖，而第1-5圖之右圖為形成強制性鰭狀堆疊反向器的方法沿左圖之線段AA’、線段BB’、CC’線段、aa’線段、bb’線段、cc’線段之剖面示意圖。如第1圖所示，提供一基底110。基底110例如是一矽基底、一含矽基底(例如SiC)、一三五族基底(例如GaN)、一三五族覆矽基底(例如GaN-on-silicon)、一石墨烯覆矽基底(graphene-on-silicon)、一矽覆絕緣(silicon-on-insulator，SOI)基底或一含磊晶層之基底等半導體基底。基底110包含複數個鰭狀結構112沿一第一方向d1並排排列且互相平行，其中鰭狀結構112可包含一第一鰭狀結構112a、一第二鰭狀結構112b以及一第三鰭狀結構112c跨設基底110的一第一主動區E1，以及可包含一第四鰭狀結構112d、一第五鰭狀結構112e以及一第六鰭狀結構112f跨設基底110的一第二主動區E2。鰭狀結構112更包含複數個犧牲鰭狀結構112g/112h/112i/112j/112k/112l/112m/112n沿第一方向d1於第一主動區E1及第二主動區E2外，但犧牲鰭狀結構112g/112h/112i/112j/112k/112l/112m/112n的個數非限於此，犧牲鰭狀結構112g/112h/112i/112j/112k/112l/112m/112n的個數可為一個或多個。複數個閘極將於後續製程中形成，在此以虛線標示閘極與第一主動區E1、第二主動區E2及鰭狀 結構112的相對位置120a’/120b’/120c’。形成鰭狀結構112的方法可包含沈積並圖案化而形成一遮罩層10，再蝕刻暴露出的基底110而形成鰭狀結構112，但本發明不以此為限。
如第2圖所示，進行一移除主動區外鰭狀結構製程P1，完全移除六條犧牲鰭狀結構112g/112h/112i/112j/112k/112l。在一實施例中，進行移除主動區外鰭狀結構製程P1時亦移除部分的基底110，而在原犧牲鰭狀結構112g/112h/112i/112j/112k/112l下方形成鰭狀凹槽112g’/112h’/112i’/112j’/112k’/112l’，但本發明不以此為限。第2圖之虛線部分表示主動區外鰭狀結構製程P1移除的區域，意即第一主動區E1及第二主動區E2外的犧牲鰭狀結構112g/112h/112i/112j/112k/112l區域。在本實施例中，主動區外鰭狀結構製程P1僅沿著第一方向d1切割犧牲鰭狀結構112g/112h/112i/112j/112k/112l。
如第3圖所示，在進行移除主動區外鰭狀結構製程P1之後，進行一鰭狀結構切割製程P2，移除第一主動區E1及第二主動區E2外的部份的第一鰭狀結構112a、第二鰭狀結構112b、第三鰭狀結構112c、第四鰭狀結構112d、第五鰭狀結構112e以及第六鰭狀結構112f。在一較佳實施例中，除了移除部份的第一鰭狀結構112a、第二鰭狀結構112b、第三鰭狀結構112c、第四鰭狀結構112d、第五鰭狀結構112e以及第六鰭狀結構112f之外，鰭狀結構切割製程P2亦切割第一主動區E1及第二主動區E2外並圍繞第一主動區E1及第二主動E2的鰭狀結構112。在本實施例中，由於犧牲鰭狀結構112h/112i/112j/112k/112l已在進行移除主動區外鰭狀結構製程P1時移除，故鰭狀結構切割製程P2僅移除犧牲鰭狀結構112m，而僅留下跨設第一主動區E1及第二主動區E2的部份的一第一鰭狀結構112a’、一第二鰭 狀結構112b’、一第三鰭狀結構112c’、一第四鰭狀結構112d’、一第五鰭狀結構112e’以及一第六鰭狀結構112f’，並形成鰭狀凹槽112i’’/112j’’/112m’。換言之，進行鰭狀結構切割製程P2，則會形成至少一鰭狀凹槽R沿第一方向d1位於第一主動區E1以及第二主動區E2之間，或者形成鰭狀凹槽R圍繞第一主動區E1以及第二主動區E2。第3圖之虛線部分表示第一主動區E1及第二主動E2外鰭狀結構切割製程P2的切割區域，此切割區域部分重疊主動區外鰭狀結構製程P1移除的切割區域。
如第4圖所示，進行一移除主動區內鰭狀結構製程P3，移除在第一主動區E1中的第二鰭狀結構112b’及第二主動E2的第五鰭狀結構112e’，而形成一第二鰭狀凹槽112b’’位於第一主動區E1中的第一鰭狀結構112a’以及第三鰭狀結構112c’之間，以及一第五鰭狀凹槽112e’’位於第二主動區E2中的第四鰭狀結構112d’以及第六鰭狀結構112f’之間。在本實施例中，移除主動區內鰭狀結構製程P3僅沿著第一方向d1切割鰭狀結構，但本發明不限於此。
如第5圖所示，在進行移除主動區內鰭狀結構製程P3之後，填入一絕緣結構20於第一鰭狀結構112a’、第三鰭狀結構112c’、第四鰭狀結構112d’以及第六鰭狀結構112f’之間。因而，第一主動區E1以及第二主動區E2之間填入絕緣結構20，而隔絕第一主動區E1以及第二主動區E2。絕緣結構20可例如為一淺溝渠絕緣(shallow trench isolation,STI)結構，其例如以一淺溝渠絕緣(shallow trench isolation,STI)製程形成，但本發明不以此為限。
承上，本發明即可以前述之進行主動區內鰭狀結構製程P3的方法，而分別在第一主動區E1以及第二主動區E2中形成1-1強制性堆疊反向器。第6圖係 繪示本發明一實施例之1-1強制性堆疊反向器之俯視示意圖。如第6圖所示，在填入絕緣結構20之後，即可形成一第一閘極120沿一第二方向d2跨設第一主動區E1中的第一鰭狀結構112a’以及第三鰭狀結構112c’，以及沿第二方向d2跨設第二主動區E2中的第四鰭狀結構112d’以及第六鰭狀結構112f’。之後，可進行一閘極切割製程P4，以切斷二1-1強制性堆疊反向器F1/F2相連的第一閘極120。然後，可再形成一金屬內連線結構130並進行一金屬內連線結構切割製程P5，以切斷1-1強制性鰭狀堆疊反向器F1/F2之間的金屬內連線結構130。而後，可在金屬內連線結構130中形成複數個通孔V，並再接續後續製程，在此不贅述。因而，第一鰭狀結構112a’可為一第一鰭狀場效電晶體M1的一鰭狀結構，第三鰭狀結構112c’為一第二鰭狀場效電晶體M2的一鰭狀結構，第四鰭狀結構112d’為一第三鰭狀場效電晶體M3的一鰭狀結構，且第六鰭狀結構112f’為一第四鰭狀場效電晶體M4的一鰭狀結構。較佳者，第一鰭狀場效電晶體M1以及第二鰭狀場效電晶體M2具有一第一導電型，第三鰭狀場效電晶體M3以及第四鰭狀場效電晶體M4具有一第二導電型，而第一導電型不同於第二導電型，但本發明不以此為限。
第7圖係繪示本發明一實施例之1-1強制性鰭狀堆疊反向器之尺寸示意圖。如第7圖所示，本發明則可將左圖現今一1-1強制性鰭狀堆疊反向器G，其佈局面積例如具有一高度h1(例如1152奈米)以及一寬度w1(例如180奈米)縮小為右圖本發明之1-1強制性鰭狀堆疊反向器F，其佈局面積例如具有一高度h2(例如576奈米)以及一寬度w2(例如180奈米)，但本發明不以此為限。
綜上所述，本發明提供一種1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法，其先在基底中形成複數個鰭狀結構，此些鰭狀結構包含一第一鰭狀結構、一第二鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一 第一主動區；再進行一移除主動區內鰭狀結構製程，移除在第一主動區中的第二鰭狀結構；之後再形成一第一閘極跨設此些鰭狀結構，如此一來則可在更小面積的主動區中形成1-1強制性鰭狀堆疊反向器，因而縮小了1-1強制性鰭狀堆疊反向器裝置的尺寸。
再者，在進行移除主動區內鰭狀結構製程之前，可先進行一主動區外鰭狀結構製程或/及一鰭狀結構切割製程。主動區外鰭狀結構製程可移除第一主動區外的至少一犧牲鰭狀結構，而鰭狀結構切割製程則可移除第一主動區外的至少一部份的第一鰭狀結構、第二鰭狀結構以及第三鰭狀結構，或者第一主動區外圍繞第一主動區的鰭狀結構，以形成所區之鰭狀結構佈局。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
110:基底
112a’:第一鰭狀結構
112b’’:第二鰭狀凹槽
112c’:第三鰭狀結構
112d’:第四鰭狀結構
112e’’:第五鰭狀凹槽
112f’:第六鰭狀結構
d1:第一方向
E1:第一主動區
E2:第二主動區
P3:移除主動區內鰭狀結構製程
AA’、BB’、CC’、aa’、bb’、cc’:線段

Claims (18)

  1. 一種形成強制性鰭狀堆疊反向器的方法，包含有：提供一基底，其中該基底包含一第一鰭狀結構、一第二鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區，且該第一鰭狀結構、該第二鰭狀結構以及該第三鰭狀結構並排排列；進行一移除主動區內鰭狀結構製程，移除在該第一主動區中的至少一部分的該第二鰭狀結構；在進行該移除主動區內鰭狀結構製程之後，填入一絕緣結構於該第一鰭狀結構以及該第三鰭狀結構之間；以及形成一第一閘極，沿一第二方向跨設該第一主動區中的該第一鰭狀結構以及該第三鰭狀結構。
  2. 如申請專利範圍第1項所述之形成強制性鰭狀堆疊反向器的方法，其中該第一鰭狀結構包含一第一鰭狀場效電晶體的一鰭狀結構，且該第三鰭狀結構包含一第二鰭狀場效電晶體的一鰭狀結構。
  3. 如申請專利範圍第2項所述之形成強制性鰭狀堆疊反向器的方法，其中該第一鰭狀場效電晶體以及該第二鰭狀場效電晶體具有相同導電型。
  4. 如申請專利範圍第1項所述之形成強制性鰭狀堆疊反向器的方法，其中該基底包含一第四鰭狀結構、一第五鰭狀結構以及一第六鰭狀結構沿該第一方向跨設一第二主動區，且該第四鰭狀結構、該第五鰭狀結構以及該第六鰭狀結構並排排列。
  5. 如申請專利範圍第4項所述之形成強制性鰭狀堆疊反向器的方法，更包含：在進行該移除主動區內鰭狀結構製程，移除在該第一主動區中的至少一部分的該第二鰭狀結構同時，移除在該第二主動區中的至少一部分的該第五鰭狀結構，且該第一閘極同時跨設該第一主動區以及該第二主動區。
  6. 如申請專利範圍第5項所述之形成強制性鰭狀堆疊反向器的方法，其中該第一鰭狀結構包含一第一鰭狀場效電晶體的一鰭狀結構，該第三鰭狀結構包含一第二鰭狀場效電晶體的一鰭狀結構，該第四鰭狀結構包含一第三鰭狀場效電晶體的一鰭狀結構，且該第六鰭狀結構包含一第四鰭狀場效電晶體的一鰭狀結構。
  7. 如申請專利範圍第6項所述之形成強制性鰭狀堆疊反向器的方法，其中該第一鰭狀場效電晶體以及該第二鰭狀場效電晶體具有一第一導電型，該第三鰭狀場效電晶體以及該第四鰭狀場效電晶體具有一第二導電型，而該第一導電型不同於該第二導電型。
  8. 如申請專利範圍第1項所述之形成強制性鰭狀堆疊反向器的方法，其中該移除主動區內鰭狀結構製程沿著該第一方向切割鰭狀結構。
  9. 如申請專利範圍第1項所述之形成強制性鰭狀堆疊反向器的方法，其中該基底包含至少一犧牲鰭狀結構沿該第一方向於該第一主動區外。
  10. 如申請專利範圍第9項所述之形成強制性鰭狀堆疊反向器的方法，在 進行該移除主動區內鰭狀結構製程之前，更包含：進行一移除主動區外鰭狀結構製程，完全移除至少一該犧牲鰭狀結構。
  11. 如申請專利範圍第10項所述之形成強制性鰭狀堆疊反向器的方法，其中該移除主動區外鰭狀結構製程沿著該第一方向切割鰭狀結構。
  12. 如申請專利範圍第10項所述之形成強制性鰭狀堆疊反向器的方法，在進行該移除主動區外鰭狀結構製程之後，更包含：進行一鰭狀結構切割製程，移除該第一主動區外的至少一部份的該第一鰭狀結構、該第二鰭狀結構以及該第三鰭狀結構。
  13. 如申請專利範圍第12項所述之形成強制性鰭狀堆疊反向器的方法，其中該鰭狀結構切割製程切割該第一主動區外並圍繞該第一主動區的鰭狀結構。
  14. 一種1-1強制性鰭狀堆疊反向器，包含有：一基底，其中該基底包含一第一鰭狀結構以及一第三鰭狀結構沿一第一方向跨設一第一主動區，一第二鰭狀凹槽位於該第一主動區中的該第一鰭狀結構以及該第三鰭狀結構之間，以及一第四鰭狀結構以及一第六鰭狀結構沿該第一方向跨設一第二主動區，一第五鰭狀凹槽位於該第二主動區中的該第四鰭狀結構以及該第六鰭狀結構之間，其中該第一鰭狀結構、該第三鰭狀結構、該第四鰭狀結構以及該第六鰭狀結構並排排列；以及一第一閘極，沿一第二方向跨設該第一主動區中的該第一鰭狀結構以及該第三鰭狀結構，以及該第二主動區中的該第四鰭狀結構以及該第六鰭狀結構。
  15. 如申請專利範圍第14項所述之1-1強制性鰭狀堆疊反向器，其中該第一鰭狀結構包含一第一鰭狀場效電晶體的一鰭狀結構，該第三鰭狀結構包含一第二鰭狀場效電晶體的一鰭狀結構，該第四鰭狀結構包含一第三鰭狀場效電晶體的一鰭狀結構，且該第六鰭狀結構包含一第四鰭狀場效電晶體的一鰭狀結構。
  16. 如申請專利範圍第15項所述之1-1強制性鰭狀堆疊反向器，其中該第一鰭狀場效電晶體以及該第二鰭狀場效電晶體具有一第一導電型，該第三鰭狀場效電晶體以及該第四鰭狀場效電晶體具有一第二導電型，而該第一導電型不同於該第二導電型。
  17. 如申請專利範圍第14項所述之1-1強制性鰭狀堆疊反向器，更包含：鰭狀凹槽圍繞該第一主動區以及該第二主動區。
  18. 如申請專利範圍第14項所述之1-1強制性鰭狀堆疊反向器，更包含：至少一鰭狀凹槽沿該第一方向位於該第一主動區以及該第二主動區之間。
TW107104758A 2018-02-09 2018-02-09 1-1強制性鰭狀堆疊反向器及形成強制性鰭狀堆疊反向器的方法 TWI750316B (zh)

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