TWI749442B - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TWI749442B TWI749442B TW109100303A TW109100303A TWI749442B TW I749442 B TWI749442 B TW I749442B TW 109100303 A TW109100303 A TW 109100303A TW 109100303 A TW109100303 A TW 109100303A TW I749442 B TWI749442 B TW I749442B
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- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
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Abstract
一種半導體封裝,其包括基板、顯示單元、驅動電路和至少一記憶體。基板具有顯示區和周邊區。顯示單元設置於顯示區中。驅動電路設置於周邊區中且與顯示單元電性連接。記憶體設置於周邊區中且與驅動電路電性連接。驅動電路與記憶體彼此相互間隔開來。
Description
本發明是有關於一種封裝結構,且特別是有關於一種半導體封裝。
隨著顯示技術不斷的進步,高操作速度之驅動器的需求也逐漸增加,因此發展出各種半導體封裝以使驅動器具有高積集度的積體電路(IC)。舉例來說,一般用於驅動顯示單元之半導體封裝可為覆晶玻璃(Chip On Glass,COG)、捲帶式晶片封裝(Tape Carrier Package,TCP)或晶粒軟膜封裝(Chip On Film,COF)。近來,隨著使用者對於顯示器之影像品質(如影像解析度、色彩飽和度等)的要求越來越高,驅動器所需要處理的資料也越來越多,因此,顯示畫面可能會因為處理資料所需時間過長而產生畫面延遲所導致之缺陷。
本發明提供一種半導體封裝,其可具有高操作速度、低功耗和良好的製程彈性(process flexibility)。
本發明的半導體封裝,其包括基板、顯示單元、驅動電路和至少一記憶體。基板具有顯示區和周邊區。顯示單元設置於顯示區中。驅動電路設置於周邊區中且與顯示單元電性連接。記憶體設置於周邊區中且與驅動電路電性連接。驅動電路與至少一記憶體彼此相互間隔開來。
依照本發明的一實施例所述,在上述的半導體封裝中,記憶體可藉由基板的配線結構與驅動電路電性連接。
依照本發明的一實施例所述,在上述的半導體封裝中,記憶體可藉由行動產業處理器介面(MIPI)與驅動電路電性連接。
依照本發明的一實施例所述,在上述的半導體封裝中,至少一記憶體可包括彼此相互間隔開來的多個記憶體。
依照本發明的一實施例所述,在上述的半導體封裝中,顯示區和周邊區可配置於相同的水平高度處。
依照本發明的一實施例所述,在上述的半導體封裝中,顯示區和周邊區可配置於不同的水平高度處。
依照本發明的一實施例所述,上述的半導體封裝中,周邊區可配置在顯示區之下,顯示單元與驅動電路和記憶體可重疊。
依照本發明的一實施例所述,上述的半導體封裝更包括主板,其可分別與記憶體和驅動電路電性連接。
依照本發明的一實施例所述,上述的半導體封裝更包括控制電路,其可設置於周邊區中且分別與驅動電路和主板電性連接。
依照本發明的一實施例所述,在上述的半導體封裝中,控制電路與記憶體和驅動電路可間隔開來。
依照本發明的一實施例所述,上述的半導體封裝中,控制電路可包括邏輯積體電路、類比積體電路或其組合。
依照本發明的一實施例所述,上述的半導體封裝中,基板可包括軟性基板或硬性基板。
依照本發明的一實施例所述,在上述的半導體封裝中,驅動電路可包括源極驅動電路。
依照本發明的一實施例所述,在上述的半導體封裝中,記憶體可包括靜態隨機存取記憶體(SRAM)、虛擬靜態隨機存取記憶體(pseudo-SRAM)、動態隨機存取記憶體(DRAM)、快閃記憶體(Flash)、電子可抹除可程式化唯讀記憶體(EEPROM)或其組合。
依照本發明的一實施例所述,在上述的半導體封裝中,顯示單元可包括液晶顯示器(LCD)、有機發光二極體(OLED)、Mini-LED顯示器或Micro-LED顯示器。
基於上述,在本發明的半導體封裝中,記憶體和驅動電路皆設置在基板的周邊區中且兩者彼此電性連接,如此可使得驅動電路能夠負荷合巨量的圖像資料,致使半導體封裝具有高操作速度和低功耗的特性,以符合高解析度/高畫質的顯示單元對於畫面更新率(frame rate)的要求。
另一方面,由於驅動電路和記憶體可分別經由不同的製程製造後,再將兩者安置在基板的周邊區中。如此一來,在驅動電路和記憶體的製程可以分開的情況下,此二者在製造上具有良好的製程彈性(process flexibility)。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而,本發明亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件,以下段落將不再一一贅述。
應當理解,當諸如元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者也可存在中間元件。若當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,則不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接,而「電性連接」或「耦合」可為二元件間存在其它元件。本文中所使用的「電性連接」可包括物理連接(例如有線連接)及物理斷接(例如無線連接)。舉例來說,電性連接可以包含如上所述之有線連接的一般連接,或者是例如經由行動產業處理器介面(Mobile Industry Processor Interface,MIPI)之連接的介面連接。
本文使用的「約」、「近似」或「實質上」包括所提到的值和在所屬技術領域中具有通常知識者能夠確定之特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,「約」可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的「約」、「近似」或「實質上」可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。
使用本文中所使用的用語僅為闡述例示性實施例,而非限制本揭露。在此種情形中,除非在上下文中另有解釋,否則單數形式包括多數形式。
圖1是依照本發明一實施例的半導體封裝的剖面示意圖。圖2是依照本發明另一實施例的半導體封裝的剖面示意圖。圖5是依照本發明一實施例的半導體封裝的驅動電路、記憶體和顯示單元的訊號連接示意圖。
請參照圖1和圖2,半導體封裝100、200包括基板SUB、顯示單元DU、驅動電路DC和至少一記憶體M。
基板SUB可具有顯示區DR和周邊區PR。基板SUB可為硬性基板或軟性基板。舉例來說,硬性基板可為玻璃,而軟性基板可為聚醯亞胺(polyimide,PI),但本發明不以此為限。
請參照圖1和圖2,顯示單元DU設置於顯示區DR中。顯示單元DU可包括液晶顯示器(LCD)、有機發光二極體(OLED)、Mini-LED顯示器或Micro-LED顯示器。在一些實施例中,顯示單元DU可包括陣列排列於基板SUB上的多個畫素單元以及彼此交錯的多條訊號線(例如資料線和掃描線)。每一個畫素單元可包括主動元件以及發光單元或畫素電極。主動元件可包括閘極、源極和汲極,其中閘極可與對應的訊號線(例如掃描線)電性連接;源極可與對應的訊號線(例如資料線)電性連接;而汲極可與對應的發光單元或畫素電極電性連接。
驅動電路DC和記憶體M設置於周邊區PR中且彼此相互間隔開來,其中記憶體M與驅動電路DC電性連接,而驅動電路DC與顯示單元DU電性連接。如此一來,記憶體M可作為畫面緩衝器(frame buffer)來暫存圖像資料(如圖5所示),使得驅動電路DC(例如源極驅動電路)能夠負荷從主板(例如微控制器(MCU)或是微控制器整合動態隨機存取記憶體(MCU/DRAM))傳來的巨量圖像資料,致使半導體封裝100、200具有高操作速度和低功耗的特性,以符合高解析度/高畫質的顯示單元DU對於畫面更新率(frame rate)的要求。
除此之外,驅動電路DC屬於高壓半導體元件;而記憶體M的操作電壓與一般邏輯電路的電壓相當,故兩者在製程設計需求上有不同的限制,將兩者的製程整合在一起有一定的難度。因此,在驅動電路DC和記憶體M彼此相互間隔開來的情況下,驅動電路DC和記憶體M可分別經由不同的製程製造後,再安置於基板SUB的周邊區PR中,如此可使得半導體封裝100、200具有良好的製程彈性,且此種半導體封裝方式也可讓驅動電路DC和記憶體M(二者的製程)具有良好的製程彈性。
記憶體M可包括靜態隨機存取記憶體(SRAM)、虛擬靜態隨機存取記憶體(pseudo-SRAM)、動態隨機存取記憶體(DRAM)、快閃記憶體(Flash)、電子可抹除可程式化唯讀記憶體(EEPROM)或其組合。驅動電路DC可包括源極驅動電路。
在一些實施例中,記憶體M可藉由基板SUB的配線結構與驅動電路DC電性連接,但本發明不以此為限。在另一些實施例中,記憶體M也可通藉由動產業處理器介面(MIPI)與驅動電路DC電性連接。基於上述,由於記憶體M和驅動電路DC皆設置在基板SUB的周邊區PR中,且記憶體M和驅動電路DC可藉由MIPI或是基板SUB中的配線結構彼此電性連接,而驅動電路DC也可藉由MIPI或是基板SUB中的配線結構來與顯示單元DU電性連接。如此一來,可省略用於將驅動電路DC連接至外部記憶體元件的匯流排線(bus line),不僅提升了圖像資料的傳輸速度亦可簡化製程。
另一方面,現今行動裝置的功能愈來愈多元,晶片與周邊元件間的互連介面也更為繁複,所以如上所提到之介面連接(例如MIPI)相形重要。在開發行動裝置、網通設備時,通常會因為智慧手機、平板電腦內置晶片間介面不相容,導致設計介面電路需經多重轉換訊號,不僅徒增成本,且晶片內傳輸效能低落也直接影響網通設備的射頻(RF)無線通訊傳輸表現。基於MIPI聯盟推行的MIPI介面之規範要求,產品開發者不只可以強化裝置內部晶片的連結整合設計,也能透過標準化介面進而減低晶片整合線路複雜度、節省介面轉換元件數量,進而節省料件成本、加速推進產品研發時程。透過MIPI規範的標準介面,在智慧裝置的功能模組即可使用迎合市場主流的高速化傳輸介面,進而進行功能整合。
在一些實施例中,如圖1所示,在基板SUB為硬性基板的情況下,顯示區DR和周邊區PR可配置於相同的水平高度處,但本發明不以此為限。在另一些實施例中,如圖2所示,基板SUB可為軟性基板,顯示區DR和周邊區PR可配置於不同的水平高度處。舉例來說,周邊區PR可配置於顯示區DR之下,如此可使得半導體封裝200的顯示面板具有窄邊框的設計。除此之外,在驅動電路DC可藉由MIPI或是基板SUB中的配線結構來電性連接至顯示單元DU的情況下,可省略用於將驅動電路DC(位於顯示面板的背面)電性連接至顯示單元DU(位於顯示面板的正面)的連接構件,例如軟性電路板(FPC)、連接墊或匯流排線等,因此相較於COF的封裝方式,半導體封裝200的顯示面板具有更窄的邊框設計。在本實施例中,顯示單元DU可與驅動電路DC和記憶體M重疊。
在本實施例中,半導體封裝100、200可包括主板(main board)MB,其可分別與記憶體M和驅動電路DC電性連接。也就是說,主板MB可將的訊號傳遞至週邊區PR中之記憶體M和/或驅動電路DC。主板MB可例如是印刷電路板(printed circuit board,PCB)或軟性印刷電路板(flexible printed circuit board,FPCB)。
圖3是依照本發明又一實施例的半導體封裝的剖面示意圖,其中半導體封裝300與半導體封裝100大致相似,其不同之處在於半導體封裝300更包括了控制電路CC,故相同或相似元件使用相同或相似標號,其餘構件之連接關係、材料及其製程已於前文中進行詳盡地描述,故於下文中不再重複贅述。圖4是依照本發明再一實施例的半導體封裝的剖面示意圖,其中半導體封裝400與半導體封裝200大致相似,其不同之處在於半導體封裝400更包括了控制電路CC,故相同或相似元件使用相同或相似標號,其餘構件之連接關係、材料及其製程已於前文中進行詳盡地描述,故於下文中不再重複贅述。
請參照圖3和圖4,半導體封裝300、400可選擇性地包括控制電路CC,其設置於周邊區PR中且分別與驅動電路DC和主板MB電性連接。在一些實施例中,控制電路CC可藉由基板SUB中的配線結構來分別與驅動電路DC和主板MB電性連接,但本發明不以此為限。在另一些實施例中,控制電路CC也可藉由行動產業處理器介面(MIPI)來分別與驅動電路DC和主板MB電性連接。在本實施例中,控制電路CC可與記憶體M和驅動電路DC間隔開來。控制電路CC可包括數位(邏輯)積體電路和類比積體電路。應注意的是,圖3和圖4是以半導體封裝300、400具有1個控制電路CC作為示範性實施例來進行說明,但本發明不以此為限。在其他實施例中,記控制電路CC可為多個。
綜上所述,在上述實施例的半導體封裝中,記憶體和驅動電路皆設置在基板的周邊區中且兩者彼此電性連接,如此可使得驅動電路能夠負荷合巨量的圖像資料,致使半導體封裝具有高操作速度和低功耗的特性,以符合高解析度/高畫質的顯示單元對於畫面更新率(frame rate)的要求。
另一方面,由於驅動電路和記憶體可分別經由不同的製程製造後,再將兩者安置在基板的周邊區中。如此一來,在驅動電路和記憶體的製程可以分開的情況下,此二者在製造上具有良好的製程彈性(process flexibility)。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200、300、400:半導體封裝
SUB:基板
DU:顯示單元
DC:驅動電路
CC:控制電路
M、M1、M2:記憶體
DR:顯示區
PR:周邊區
MB:主板
圖1是依照本發明一實施例的半導體封裝的剖面示意圖。
圖2是依照本發明另一實施例的半導體封裝的剖面示意圖。
圖3是依照本發明又一實施例的半導體封裝的剖面示意圖。
圖4是依照本發明再一實施例的半導體封裝的剖面示意圖。
圖5是依照本發明一實施例的半導體封裝的驅動電路、記憶體和顯示單元的訊號連接示意圖。
200:半導體封裝
SUB:基板
DU:顯示單元
DC:驅動電路
M、M1、M2:記憶體
DR:顯示區
PR:周邊區
MB:主板
Claims (13)
- 一種半導體封裝,包括:基板,具有顯示區和周邊區;顯示單元,設置於所述顯示區中;驅動電路,設置於所述周邊區中且與所述顯示單元電性連接;以及至少一記憶體,設置於所述周邊區中且直接地與所述驅動電路電性連接,其中所述驅動電路與所述至少一記憶體彼此相互間隔開來;主板,分別直接地與所述至少一記憶體和所述驅動電路電性連接;控制電路,設置於所述周邊區中且分別與所述驅動電路和所述主板電性連接。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一記憶體藉由所述基板的配線結構與所述驅動電路電性連接。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一記憶體藉由行動產業處理器介面(MIPI)與所述驅動電路電性連接。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一記憶體包括彼此相互間隔開來的多個記憶體。
- 如申請專利範圍第1項所述的半導體封裝,其中所述顯示區和所述周邊區配置於相同的水平高度處。
- 如申請專利範圍第1項所述的半導體封裝,其中所述顯示區和所述周邊區配置於不同的水平高度處。
- 如申請專利範圍第6項所述的半導體封裝,其中所述周邊區配置在所述顯示區之下,所述顯示單元與所述驅動電路和所述至少一記憶體重疊。
- 如申請專利範圍第1項所述的半導體封裝,其中所述控制電路與所述至少一記憶體和所述驅動電路間隔開來。
- 如申請專利範圍第1項所述的半導體封裝,其中所述控制電路包括邏輯積體電路、類比積體電路或其組合。
- 如申請專利範圍第1項所述的半導體封裝,其中所述基板包括軟性基板或硬性基板。
- 如申請專利範圍第1項所述的半導體封裝,其中所述驅動電路包括源極驅動電路。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一記憶體包括靜態隨機存取記憶體(SRAM)、虛擬靜態隨機存取記憶體(pseudo-SRAM)、動態隨機存取記憶體(DRAM)、快閃記憶體(Flash)、電子可抹除可程式化唯讀記憶體(EEPROM)或其組合。
- 如申請專利範圍第1項所述的半導體封裝,其中所述顯示單元包括液晶顯示器(LCD)、有機發光二極體(OLED)、Mini-LED顯示器或Micro-LED顯示器。
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TW109100303A TWI749442B (zh) | 2020-01-06 | 2020-01-06 | 半導體封裝 |
CN202010074748.1A CN113077739B (zh) | 2020-01-06 | 2020-01-22 | 半导体封装 |
US16/796,911 US11086360B2 (en) | 2020-01-06 | 2020-02-20 | Semiconductor package |
KR1020200037749A KR102402572B1 (ko) | 2020-01-06 | 2020-03-27 | 반도체 패키지 |
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CN113077739A (zh) | 2021-07-06 |
US20210208632A1 (en) | 2021-07-08 |
US11086360B2 (en) | 2021-08-10 |
KR102402572B1 (ko) | 2022-05-26 |
KR20210089064A (ko) | 2021-07-15 |
CN113077739B (zh) | 2023-12-19 |
TW202127594A (zh) | 2021-07-16 |
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