CN113077739A - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
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- CN113077739A CN113077739A CN202010074748.1A CN202010074748A CN113077739A CN 113077739 A CN113077739 A CN 113077739A CN 202010074748 A CN202010074748 A CN 202010074748A CN 113077739 A CN113077739 A CN 113077739A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 230000015654 memory Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract description 32
- 230000003068 static effect Effects 0.000 claims description 5
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 15
- 238000013461 design Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Abstract
一种半导体封装,其包括基板、显示单元、驱动电路和至少一内存。基板具有显示区和周边区。显示单元设置于显示区中。驱动电路设置于周边区中且与显示单元电性连接。内存设置于周边区中且与驱动电路电性连接。驱动电路与内存彼此相互间隔开来。
Description
技术领域
本发明是有关于一种封装结构,且特别是有关于一种半导体封装。
背景技术
随着显示技术不断的进步,高操作速度的驱动器的需求也逐渐增加,因此发展出各种半导体封装以使驱动器具有高集成度的集成电路(IC)。举例来说,一般用于驱动显示单元的半导体封装可为覆晶玻璃(Chip On Glass,COG)、卷带式芯片封装(Tape CarrierPackage,TCP)或芯片软膜封装(Chip On Film,COF)。近来,随着用户对于显示器的影像质量(如影像分辨率、色彩饱和度等)的要求越来越高,驱动器所需要处理的数据也越来越多,因此,显示画面可能会因为处理数据所需时间过长而产生画面延迟所导致的缺陷。
发明内容
本发明提供一种半导体封装,其可具有高操作速度、低功耗和良好的制造工艺弹性(process flexibility)。
本发明的半导体封装,其包括基板、显示单元、驱动电路和至少一内存。基板具有显示区和周边区。显示单元设置于显示区中。驱动电路设置于周边区中且与显示单元电性连接。内存设置于周边区中且与驱动电路电性连接。驱动电路与至少一内存彼此相互间隔开来。
依照本发明的一实施例所述,在上述的半导体封装中,内存可通过基板的配线结构与驱动电路电性连接。
依照本发明的一实施例所述,在上述的半导体封装中,内存可通过移动行业处理器接口(MIPI)与驱动电路电性连接。
依照本发明的一实施例所述,在上述的半导体封装中,至少一内存可包括彼此相互间隔开来的多个内存。
依照本发明的一实施例所述,在上述的半导体封装中,显示区和周边区可配置于相同的水平高度处。
依照本发明的一实施例所述,在上述的半导体封装中,显示区和周边区可配置于不同的水平高度处。
依照本发明的一实施例所述,上述的半导体封装中,周边区可配置在显示区之下,显示单元与驱动电路和内存可重叠。
依照本发明的一实施例所述,上述的半导体封装还包括主板,其可分别与内存和驱动电路电性连接。
依照本发明的一实施例所述,上述的半导体封装还包括控制电路,其可设置于周边区中且分别与驱动电路和主板电性连接。
依照本发明的一实施例所述,在上述的半导体封装中,控制电路与内存和驱动电路可间隔开来。
依照本发明的一实施例所述,上述的半导体封装中,控制电路可包括逻辑集成电路、模拟集成电路或其组合。
依照本发明的一实施例所述,上述的半导体封装中,基板可包括柔性基板或硬性基板。
依照本发明的一实施例所述,在上述的半导体封装中,驱动电路可包括源极驱动电路。
依照本发明的一实施例所述,在上述的半导体封装中,内存可包括静态随机存取内存(SRAM)、虚拟静态随机存取内存(pseudo-SRAM)、动态随机存取内存(DRAM)、闪存(Flash)、电可擦除可编程只读存储器(EEPROM)或其组合。
依照本发明的一实施例所述,在上述的半导体封装中,显示单元可包括液晶显示器(LCD)、有机发光二极管(OLED)、Mini-LED显示器或Micro-LED显示器。
基于上述,在本发明的半导体封装中,内存和驱动电路皆设置在基板的周边区中且两者彼此电性连接,如此可使得驱动电路能够负荷巨量的图像数据,致使半导体封装具有高操作速度和低功耗的特性,以符合高分辨率/高画质的显示单元对于画面更新率(frame rate)的要求。
另一方面,由于驱动电路和内存可分别经由不同的制造工艺制造后,再将两者安置在基板的周边区中。如此一来,在驱动电路和内存的制造工艺可以分开的情况下,此二者在制造上具有良好的制造工艺弹性(process flexibility)。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1是依照本发明一实施例的半导体封装的剖面示意图。
图2是依照本发明另一实施例的半导体封装的剖面示意图。
图3是依照本发明又一实施例的半导体封装的剖面示意图。
图4是依照本发明再一实施例的半导体封装的剖面示意图。
图5是依照本发明一实施例的半导体封装的驱动电路、内存和显示单元的信号连接示意图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而,本发明也可以各种不同的形式体现,而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的组件,以下段落将不再一一赘述。
应当理解,当诸如组件被称为在另一组件“上”或“连接到”另一组件时,其可以直接在另一组件上或与另一组件连接,或者也可存在中间组件。若当组件被称为“直接在另一组件上”或“直接连接到”另一组件时,则不存在中间组件。如本文所使用的,“连接”可以指物理和/或电性连接,而“电性连接”或“耦合”可以指两个组件间存在其它组件。本文中所使用的“电性连接”可包括物理连接(例如有线连接)及物理断接(例如无线连接)。举例来说,电性连接可以包含如上所述的有线连接的一般连接,或者是例如经由移动行业处理器接口(Mobile Industry Processor Interface,MIPI)的连接的接口连接。
本文使用的“约”、“近似”或“实质上”包括所提到的值和本领域技术人员能够确定的特定值的可接受的偏差范围内的平均值,考虑到所讨论的测量和与测量相关的误差的特定数量(即,测量系统的限制)。例如,“约”可以表示在所述值的一个或多个标准偏差内,或±30%、±20%、±10%、±5%内。再者,本文使用的“约”、“近似”或“实质上”可依光学性质、蚀刻性质或其它性质,来选择较可接受的偏差范围或标准偏差,而可不用一个标准偏差适用全部性质。
使用本文中所使用的用语仅为阐述例示性实施例,而非限制本公开。在此种情形中,除非在上下文中另有解释,否则单数形式包括多数形式。
图1是依照本发明一实施例的半导体封装的剖面示意图。图2是依照本发明另一实施例的半导体封装的剖面示意图。图5是依照本发明一实施例的半导体封装的驱动电路、内存和显示单元的信号连接示意图。
请参照图1和图2,半导体封装100、200包括基板SUB、显示单元DU、驱动电路DC和至少一内存M。
基板SUB可具有显示区DR和周边区PR。基板SUB可为硬性基板或柔性基板。举例来说,硬性基板可为玻璃,而柔性基板可为聚酰亚胺(polyimide,PI),但本发明不以此为限。
请参照图1和图2,显示单元DU设置于显示区DR中。显示单元DU可包括液晶显示器(LCD)、有机发光二极管(OLED)、Mini-LED显示器或Micro-LED显示器。在一些实施例中,显示单元DU可包括数组排列于基板SUB上的多个像素单元以及彼此交错的多条信号线(例如数据线和扫描线)。每一个像素单元可包括主动组件以及发光单元或像素电极。主动组件可包括栅极、源极和漏极,其中栅极可与对应的信号线(例如扫描线)电性连接;源极可与对应的信号线(例如数据线)电性连接;而漏极可与对应的发光单元或像素电极电性连接。
驱动电路DC和内存M设置于周边区PR中且彼此相互间隔开来,其中内存M与驱动电路DC电性连接,而驱动电路DC与显示单元DU电性连接。如此一来,内存M可作为画面缓冲器(frame buffer)来暂存图像数据(如图5所示),使得驱动电路DC(例如源极驱动电路)能够负荷从主板(例如微控制器(MCU)或是微控制器整合动态随机存取内存(MCU/DRAM))传来的巨量图像数据,致使半导体封装100、200具有高操作速度和低功耗的特性,以符合高分辨率/高画质的显示单元DU对于画面更新率(frame rate)的要求。
除此之外,驱动电路DC属于高压半导体组件;而内存M的操作电压与一般逻辑电路的电压相当,因此两者在制造工艺设计需求上有不同的限制,将两者的制造工艺整合在一起有一定的难度。因此,在驱动电路DC和内存M彼此相互间隔开来的情况下,驱动电路DC和内存M可分别经由不同的制造工艺制造后,再安置于基板SUB的周边区PR中,如此可使得半导体封装100、200具有良好的制造工艺弹性,且此种半导体封装方式也可让驱动电路DC和内存M(二者的制造工艺)具有良好的制造工艺弹性。
内存M可包括静态随机存取内存(SRAM)、虚拟静态随机存取内存(pseudo-SRAM)、动态随机存取内存(DRAM)、闪存(Flash)、电可擦除可编程只读存储器(EEPROM)或其组合。驱动电路DC可包括源极驱动电路。
在一些实施例中,内存M可通过基板SUB的配线结构与驱动电路DC电性连接,但本发明不以此为限。在另一些实施例中,内存M也可通过移动行业处理器接口(MIPI)与驱动电路DC电性连接。基于上述,由于内存M和驱动电路DC皆设置在基板SUB的周边区PR中,且内存M和驱动电路DC可通过MIPI或是基板SUB中的配线结构彼此电性连接,而驱动电路DC也可通过MIPI或是基板SUB中的配线结构来与显示单元DU电性连接。如此一来,可省略用于将驱动电路DC连接至外部内存组件的总线线(bus line),不仅提升了图像数据的传输速度也可简化制造工艺。
另一方面,现今移动装置的功能越来越多元,芯片与周边组件间的互连接口也更为繁复,所以如上所提到的接口连接(例如MIPI)相当重要。在开发移动装置、网通设备时,通常会因为智能手机、平板计算机内置芯片间接口不兼容,导致设计接口电路需经多重转换信号,不仅徒增成本,且芯片内传输效能低落也直接影响网通设备的射频(RF)无线通信传输表现。基于MIPI联盟推行的MIPI接口的规范要求,产品开发者不只可以强化装置内部芯片的链接整合设计,也能通过标准化接口进而减低芯片整合线路复杂度、节省接口转换组件数量,进而节省料件成本、加速推进产品研发时程。通过MIPI规范的标准接口,在智能装置的功能模块即可使用迎合市场主流的高速化传输接口,进而进行功能整合。
在一些实施例中,如图1所示,在基板SUB为硬性基板的情况下,显示区DR和周边区PR可配置于相同的水平高度处,但本发明不以此为限。在另一些实施例中,如图2所示,基板SUB可为柔性基板,显示区DR和周边区PR可配置于不同的水平高度处。举例来说,周边区PR可配置于显示区DR之下,如此可使得半导体封装200的显示面板具有窄边框的设计。除此之外,在驱动电路DC可通过MIPI或是基板SUB中的配线结构来电性连接至显示单元DU的情况下,可省略用于将驱动电路DC(位于显示面板的背面)电性连接至显示单元DU(位于显示面板的正面)的连接构件,例如柔性电路板(FPC)、连接垫或总线线等,因此相较于COF的封装方式,半导体封装200的显示面板具有更窄的边框设计。在本实施例中,显示单元DU可与驱动电路DC和内存M重叠。
在本实施例中,半导体封装100、200可包括主板(main board)MB,其可分别与内存M和驱动电路DC电性连接。也就是说,主板MB可将信号传递至外围区PR中的内存M和/或驱动电路DC。主板MB可例如是印刷电路板(printed circuit board,PCB)或柔性印刷电路板(flexible printed circuit board,FPCB)。
图3是依照本发明又一实施例的半导体封装的剖面示意图,其中半导体封装300与半导体封装100大致相似,其不同之处在于半导体封装300还包括了控制电路CC,因此相同或相似组件使用相同或相似标号,其余构件的连接关系、材料及其制造工艺已于前文中进行详尽地描述,因此于下文中不再重复赘述。图4是依照本发明再一实施例的半导体封装的剖面示意图,其中半导体封装400与半导体封装200大致相似,其不同之处在于半导体封装400还包括了控制电路CC,因此相同或相似组件使用相同或相似标号,其余构件的连接关系、材料及其制造工艺已于前文中进行详尽地描述,因此于下文中不再重复赘述。
请参照图3和图4,半导体封装300、400可选择性地包括控制电路CC,其设置于周边区PR中且分别与驱动电路DC和主板MB电性连接。在一些实施例中,控制电路CC可通过基板SUB中的配线结构来分别与驱动电路DC和主板MB电性连接,但本发明不以此为限。在另一些实施例中,控制电路CC也可通过移动行业处理器接口(MIPI)来分别与驱动电路DC和主板MB电性连接。在本实施例中,控制电路CC可与内存M和驱动电路DC间隔开来。控制电路CC可包括数字(逻辑)集成电路和模拟集成电路。应注意的是,图3和图4是以半导体封装300、400具有1个控制电路CC作为示范性实施例来进行说明,但本发明不以此为限。在其他实施例中,控制电路CC可为多个。
综上所述,在上述实施例的半导体封装中,内存和驱动电路均设置在基板的周边区中且两者彼此电性连接,如此可使得驱动电路能够负荷巨量的图像数据,致使半导体封装具有高操作速度和低功耗的特性,以符合高分辨率/高画质的显示单元对于画面更新率(frame rate)的要求。
另一方面,由于驱动电路和内存可分别经由不同的制造工艺制造后,再将两者安置在基板的周边区中。如此一来,在驱动电路和内存的制造工艺可以分开的情况下,此二者在制造上具有良好的制造工艺弹性(process flexibility)。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定者为准。
符号说明
100、200、300、400:半导体封装
SUB:基板
DU:显示单元
DC:驱动电路
CC:控制电路
M、M1、M2:内存
DR:显示区
PR:周边区
MB:主板
Claims (15)
1.一种半导体封装,包括:
基板,具有显示区和周边区;
显示单元,设置于所述显示区中;
驱动电路,设置于所述周边区中且与所述显示单元电性连接;以及
至少一内存,设置于所述周边区中且与所述驱动电路电性连接,
其中所述驱动电路与所述至少一内存彼此相互间隔开来。
2.如权利要求1所述的半导体封装,其中所述至少一内存通过所述基板的配线结构与所述驱动电路电性连接。
3.如权利要求1所述的半导体封装,其中所述至少一内存通过移动行业处理器接口MIPI与所述驱动电路电性连接。
4.如权利要求1所述的半导体封装,其中所述至少一内存包括彼此相互间隔开来的多个内存。
5.如权利要求1所述的半导体封装,其中所述显示区和所述周边区配置于相同的水平高度处。
6.如权利要求1所述的半导体封装,其中所述显示区和所述周边区配置于不同的水平高度处。
7.如权利要求6所述的半导体封装,其中所述周边区配置在所述显示区之下,所述显示单元与所述驱动电路和所述至少一内存重叠。
8.如权利要求1所述的半导体封装,还包括:
主板,分别与所述至少一内存和所述驱动电路电性连接。
9.如权利要求8所述的半导体封装,还包括:
控制电路,设置于所述周边区中且分别与所述驱动电路和所述主板电性连接。
10.如权利要求9所述的半导体封装,其中所述控制电路与所述至少一内存和所述驱动电路间隔开来。
11.如权利要求9所述的半导体封装,其中所述控制电路包括逻辑集成电路、模拟集成电路或其组合。
12.如权利要求1所述的半导体封装,其中所述基板包括柔性基板或硬性基板。
13.如权利要求1所述的半导体封装,其中所述驱动电路包括源极驱动电路。
14.如权利要求1所述的半导体封装,其中所述至少一内存包括静态随机存取内存SRAM、虚拟静态随机存取内存pseudo-SRAM、动态随机存取内存DRAM、闪存Flash、电可擦除可编程只读存储器EEPROM或其组合。
15.如权利要求1所述的半导体封装,其中所述显示单元包括液晶显示器LCD、有机发光二极管OLED、Mini-LED显示器或Micro-LED显示器。
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CN113077739B (zh) | 2023-12-19 |
KR102402572B1 (ko) | 2022-05-26 |
TWI749442B (zh) | 2021-12-11 |
KR20210089064A (ko) | 2021-07-15 |
US20210208632A1 (en) | 2021-07-08 |
US11086360B2 (en) | 2021-08-10 |
TW202127594A (zh) | 2021-07-16 |
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