TWI742680B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI742680B
TWI742680B TW109116847A TW109116847A TWI742680B TW I742680 B TWI742680 B TW I742680B TW 109116847 A TW109116847 A TW 109116847A TW 109116847 A TW109116847 A TW 109116847A TW I742680 B TWI742680 B TW I742680B
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work function
type work
layer
function layer
aluminum
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TW109116847A
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TW202044589A (zh
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程仲良
吳俊毅
子韋 方
趙皇麟
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台灣積體電路製造股份有限公司
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Abstract

相對於鋁基n型功函數層，本文描述的實施例為有關於有著無鋁n型功函數層的電晶體的製造方法。此方法包含在兩隔開的源極/汲極磊晶層之間形成通道部，以及在通道部上形成閘極堆疊物，其中形成閘極堆疊物的步驟包含在通道部上沉積高介電常數介電層以及在高介電常數介電層上沉積p型功函數層。在沉積p型功函數層之後，以不破真空的方式在p型功函數層上形成無鋁n型功函數層，及在無鋁n型功函數層上沉積金屬。此方法更包含沉積絕緣層，以圍繞兩隔開的源極/汲極磊晶層和閘極堆疊物。

Description

半導體結構及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體結構及其形成方法。
電晶體(例如n型或p型電晶體)的臨界電壓可透過調整電晶體的閘極結構中的功函數層的厚度來調整。然而，因為電晶體的尺寸縮小，功函數層的厚度調整受到限制，因此透過將電晶體的閘極結構微縮化來製造較小的裝置會為調整臨界電壓帶來挑戰。
在一些實施例中，提供半導體結構，半導體結構包含鰭結構，位於基底上；兩隔開的源極/汲極磊晶堆疊物，形成於鰭結構的頂表面上；複數個奈米片層，設置於兩隔開的源極/汲極磊晶堆疊物之間，其中複數個奈米片層間隔開；以及閘極結構，圍繞複數個奈米片層，其中閘極結構包含:介電堆疊物，圍繞複數個奈米片層形成；功函數層，圍繞介電堆疊物形成；無鋁功函數層，圍繞功函數層形成；以及金屬層，圍繞無鋁功函數層形成。
在一些其他實施例中，提供半導體結構，半導體結構包含奈米片通道部，設置於兩隔開的源極/汲極磊晶層之間，其中奈米片通道部包含垂直堆疊且間隔開的兩個或多個奈米片層；以及閘極堆疊物，設置於奈米片通道部上，並圍繞奈米片通道部的兩個或多個奈米片層，其中閘極堆疊物包含:介電層，設置於奈米片通道部的兩個或多個奈米片層上；一或多個p型功函數層，位於介電層上；無鋁n型功函數層，位於一或多個p型功函數層上；及金屬，位於奈米片通道部的兩個或多個奈米片層之間。
在另外一些實施例中，提供半導體結構的形成方法，此方法包含在兩隔開的源極/汲極磊晶層之間形成通道部；在通道部上形成閘極堆疊物，其中形成閘極堆疊物的步驟包含:在通道部上沉積高介電常數介電層；在高介電常數介電層上沉積p型功函數層；在沉積p型功函數層之後，以不破真空的方式在p型功函數層上形成無鋁n型功函數層；及在無鋁n型功函數層上沉積金屬；以及沉積絕緣層，以圍繞兩隔開的源極/汲極磊晶層和閘極堆疊物。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。舉例來說，如果圖中的裝置被翻轉，被描述為在其他元件或部件“下方”或“之下”的元件將被定位在其他元件或部件“上方”。 因此，示例性術語“下方”可以涵蓋上方和下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
本文使用的術語“標稱的(nominal)”是指在產品或製程的設計階段期間設定的組件或製程操作的特性或參數的期望值或目標值，以及在期望值以上及/或以下的範圍值。數值的範圍可為由於製造過程或誤差導致的變化。
在一些實施例中，術語“大約”和“大致”是指在目標值的5%內(例如目標值的±1%、±2%、±3%、±4%及、±5%內)變化之給定的數值。
本文使用的術語“垂直”是指標稱垂直於基底的表面。
本文使用的術語“絕緣層”是指作為電性絕緣的層(例如介電層)。
場效電晶體(field effect transistor，FET)的閘極結構或閘極堆疊物中的一些層部分控制了電晶體的臨界電壓。特別來說，電晶體的臨界電壓值取決於包含在閘極堆疊物中的層的集體厚度和類型。因此，透過控制在每個場效電晶體中的這些層的厚度(或這些層的數量)，可製造有著不同臨界電壓的場效電晶體。舉例來說，有著低臨界電壓(例如在約80mV與約160mV之間)的場效電晶體可用於晶片中的“低”或“超低”功率應用，而有著高臨界電壓(例如大於約200mV)的場效電晶體可用於晶片中的高功率應用。
由於持續的裝置微縮化以及對低功率攜帶式裝置(例如行動電話、智慧型手表及其他可穿戴電子裝置、平板電腦等)的推廣，因此需要具有較低臨界電壓的電晶體的積體電路(integrated circuits，ICs)。p型場效電晶體和n型場效電晶體可具有不同的“絕對值”臨界電壓(例如臨界電壓的大小，不考慮其符號)，因為p型場效電晶體和n型場效電晶體在其閘極堆疊中包含不同類型及/或不同數量的金屬層。舉例來說，p型場效電晶體具有比n型場效電晶體更高的臨界電壓，因此需要較高電壓來開啟(例如使電流在源極與汲極端子之間流動)。出於此原因，相較於p型場效電晶體，n型場效電晶體可被稱為“強”，而相較於n型場效電晶體，p型場效電晶體可被稱為“弱”。
在n型場效電晶體中，進一步縮減(例如降低)臨界電壓的方法為增加形成於場效電晶體的閘極堆疊物中的含鋁n型功函數層的厚度，含鋁n型功函數層例如鈦鋁(TiAl)或鈦鋁碳(TiAlC)。然而，TiAl或TiAlC層的厚度增加可受限於具有挑戰性閘極堆疊物幾何形狀的場效電晶體的微縮化約束，這些場效電晶體例如全環繞式閘極(gate-all-around，GAA)奈米片場效電晶體(nano-sheet FETs，NSFETs)。舉例來說，隨著奈米片至奈米片的間距縮小，TiAl或TiAlC層的可用空間縮小。因此，增加n型奈米片場效電晶體中的TiAl或TiAlC層的厚度可變得具挑戰性。舉例來說，由於奈米片至奈米片的間距小(例如在約8nm與約12nm之間)，因此現有或較厚(例如等於或大於約2.5nm)的TiAl或TiAlC層可導致閘極堆疊物間隙填充不佳，進而導致閘極堆疊物中出現空隙，以及橫跨電晶體的閘極堆疊物電阻發生變化。
本文描述的實施例為有關於有著無鋁n型功函數層的電晶體的製造方法，無鋁n型功函數層比鋁基n型功函數層(例如TiAl或TiAlC)更薄。因此，本文描述的無鋁n型功函數層可緩和上述不佳的閘極堆疊物間隙填充所帶來的挑戰。在一些實施例中，無鋁n型功函數層可成長至厚度約5Å與約15Å之間，此厚度比鋁基n型功函數層更薄至少約10Å。在一些實施例中，無鋁n型功函數層包含矽化鈦(TiSix )、矽化鉭(TaSix )、矽化鈷(CoSix )或矽化鎳(NiSix )，且無鋁n型功函數層與閘極堆疊物的p型功函數層原位形成(例如沒有破真空)。
第1和2圖為在移除犧牲閘極堆疊物之後，半成品的奈米片場效電晶體100的等角視圖。在一些實施例中，第2圖顯示將第1圖沿z軸逆時針旋轉45°之後，半成品的奈米片場效電晶體100。換句話說，第2圖為第1圖所示製造的奈米片場效電晶體100的另一視圖。如第1圖所示，半成品的奈米片場效電晶體100包含有著間隔開的奈米片層115的一個或多個多層奈米片堆疊物105。在一些實施例中，在較早的製造操作期間磊晶成長奈米片層115，以作為第2圖所示的鰭結構120的一部分。在一些實施例中，奈米片層115包含結晶矽(Si)，並形成半成品的奈米片場效電晶體100的通道區。或者，奈米片層115可包含矽鍺(SiGe)、第III-V族化合物半導體(例如砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)或氮化鎵(GaN))。作為範例，將在件隔開的Si奈米片層115的背景下描述在成品的奈米片場效電晶體100中的奈米片堆疊物105。基於本文的揭露內容，可使用上述的其他材料。這些材料在本發明實施例的精神和範圍中。作為範例而非限制，可用於成長Si奈米片層115的前驅物氣體包含矽烷(SiH4 )、二矽烷(Si2 H6 )、任何其他合適的氣體或前述之組合。
在一些實施例中，奈米片層115可具有相同或不同的厚度。依據一些實施例，每個Si奈米片層115的厚度可在約5nm至約8nm的範圍中。在一些實施例中，Si奈米片層115具有與奈米片堆疊物105的寬度匹配的相等寬度(例如沿第1圖的x軸)。作為範例而非限制，Si奈米片層115的寬度可在約15nm至約50nm的範圍中。
在一些實施例中，每個奈米片堆疊物105可包含多達約10至12個總奈米片層。然而，依據半成品的奈米片場效電晶體100的設計可能有更多或更少的奈米片堆疊物105。在一些實施例中，多層奈米片堆疊物105的高度105H 可在約100nm與約200nm之間的範圍中。奈米片層115和奈米片堆疊物105的上述厚度和高度並非限制性。
請參照第2圖，鰭結構120形成於基底125上。作為範例而非限制，鰭結構120和基底125包含半導體材料，例如結晶矽。在一些實施例中，鰭結構120和基底125可包含其他元素半導體，例如鍺(Ge)、化合物半導體(其包含碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)及/或銻化銦(InSb))、合金半導體(其包含矽鍺(SiGe)、鎵砷磷(GaAsP)、鋁銦砷(AlInAs)、鋁鎵砷(AlGaAs)、鎵銦砷(GaInAs)、鎵銦磷(GaInP)及/或鎵銦砷磷(GaInAsP))或前述之組合。作為範例，將在結晶矽(Si)的背景下描述鰭結構120形成於基底125上。基於本文的揭露內容，可使用上述的其他材料。這些材料在本發明實施例的精神和範圍中。
可透過任何合適的方法將鰭結構120圖案化。舉例來說，鰭結構120可透過使用一個或多個光微影製程(包含雙重圖案化或多重圖案化製程)來圖案化。一般來說，雙重圖案化或多重圖案化製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著，移除犧牲層，且可接著使用剩下的間隔物將鰭結構120圖案化。
如第1和2圖所示，半成品的奈米片場效電晶體100包含額外的結構元件，例如襯墊130、絕緣層135、成長於鰭結構120上的源極/汲極(source/drain，S/D)磊晶堆疊物140、蓋層145、隔離層150、形成於隔離層150中的閘極堆疊物開口155及形成於閘極堆疊物開口155中的隔離層150的側壁表面上的間隙壁160。在一些實施例中，源極/汲極磊晶堆疊物140在隔離層150的整個厚度內沿y軸延伸並鄰接間隙壁160。在一些實施例中，奈米片層115穿過間隙壁160並接觸源極/汲極磊晶堆疊物140，如第10圖所示。
在一些實施例中，絕緣層135可為與鰭結構120電性隔離的隔離結構(例如淺溝槽隔離(shallow trench isolation，STI))，並包含氧化矽(SiO2 )、氮化矽(Si3 N4 )、氮氧化矽(SiON)、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、磷摻雜矽酸鹽玻璃(phosphorous-doped silicate glass，PSG)、低介電常數材料(例如有著介電常數值小於約3.9)及/或有著合適填充性質的其他合適的介電材料。在一些實施例中，襯墊130為氮化層，例如Si3 N4 。
在一些實施例中，源極/汲極磊晶堆疊物140可為適用於p型奈米片場效電晶體的硼摻雜(B-doped)SiGe堆疊物或適用於n型奈米片場效電晶體的磷摻雜(P-doped)Si層。在一些實施例中，磷摻雜(n型)Si源極/汲極層可透過使用矽烷(SiH4 )前驅物磊晶成長。可在成長期間將磷摻雜物引入Si磊晶成長層。作為範例而非限制，磷濃度可在約1021 atoms/cm3 至約8x1021 atoms/cm3 的範圍中。相對地，硼摻雜(p型)SiGe源極/汲極可為可包含連續成長的兩個或更多個磊晶層(未顯示於第1圖)的磊晶堆疊物，且可具有不同的鍺(Ge)原子百分比和不同的硼摻雜物濃度。作為範例而非限制，第一磊晶層可具有鍺原子百分比在0至約40%的範圍中，且硼摻雜物濃度可在約5x1019 atoms/cm3 至約1x1021 atoms/cm3 的範圍中；第二磊晶層可具有鍺原子百分比在約20%至約80%的範圍中，且硼摻雜物濃度可在約3x1020 atoms/cm3 至約5x1021 atoms/cm3 的範圍中；以及第三磊晶層可為蓋層，蓋層可具有相似於第一磊晶層的鍺原子百分比和硼摻雜物濃度(例如鍺原子百分比在0至約40%的範圍中，且硼摻雜物濃度可在約5x1019 atoms/cm3 至約1x1021 atoms/cm3 的範圍中)。這些層的厚度可依據裝置效能需求而改變。舉例來說，第一磊晶層可具有厚度在約10nm至約20nm的範圍中，第二磊晶層可具有厚度在約30nm至約60nm的範圍中，且第三磊晶層(蓋層)可具有厚度在0至約10nm的範圍中。可注意的是，上述厚度和摻雜濃度並非限制性，且其他厚度和摻雜濃度在本發明實施例的精神和範圍中。
在一些實施例中，蓋層145可具有厚度在約3nm至約5nm的範圍中。作為範例而非限制，蓋層145可透過順應性沉積製程、原子層沉積(atomic layer deposition，ALD)、電漿輔助原子層沉積(plasma-enhanced ALD，PEALD)、化學氣相沉積(chemical vapor deposition，CVD)、電漿輔助化學氣相沉積(plasma-enhanced CVD，PECVD)或任何其他合適的沉積方法沉積。在一些實施例中，蓋層145在後續在源極/汲極磊晶堆疊物140上形成接觸開口(未顯示於第1圖)的蝕刻製程期間作為蝕刻停止層。
依據一些實施例，隔離層150為層間介電質(interlayer dielectric，ILD)，層間介電質包含具有或不具有碳及/或氮的氧化矽基介電材料。隔離層150圍繞源極/汲極磊晶堆疊物140，且在移除犧牲閘極堆疊物之前形成，犧牲閘極堆疊物未顯示於第1圖。在移除犧牲閘極堆疊物之後，閘極堆疊物開口155形成於隔離層150中，如第1圖所示。作為範例而非限制，隔離層150可透過化學氣相沉積、物理氣相沉積(physical vapor deposition，PVD)或任何其他合適的沉積方法沉積。
最後，間隙壁160可包含介電材料，例如SiON、氮化矽碳(SiCN)、氮氧化矽(SiOC)、Si3 N4 或前述之組合。在一些實施例中，間隙壁160的厚度可在約2nm至約5nm的範圍中。間隙壁160可為一層或多層的堆疊物，一層或多層的堆疊物包含相同或不同材料。依據一些實施例，間隙壁160沉積於犧牲閘極堆疊物的側壁表面上，之後的閘極取代製程期間移除犧牲閘極堆疊物以形成閘極堆疊物開口155。在第1圖中，間隙壁160作為將在後續操作中形成於閘極堆疊物開口155中的金屬閘極堆疊物的結構元件。
第3圖為依據一些實施例之描述製造有著無鋁功函數層的閘極堆疊物的n型和p型奈米片場效電晶體結構的方法300的流程圖。可注意的是，方法300可不限於奈米片電晶體，且可應用於可受益於較薄的功函數層的幾何形狀的電晶體，例如鰭式場效電晶體、平面場效電晶體、奈米線場效電晶體等。
其他製造操作可在方法300的各種操作之間進行，且僅為了清楚起見可省略這些其他製造操作。本發明實施例不限於此操作描述。應當理解的是，可進行額外操作。再者，可能不需要進行本文提供的所有操作。此外，可同時進行一些操作，或以與第3圖不同的順序進行一些操作。在一些實施例中，除了現在描述的操作之外或取代現在描述的操作，可進行一個或多個其他的操作。為了顯示目的，參考第1、2和4-8圖所示的實施例描述方法300。提供用於描述方法300的圖式僅為顯示目的，且未按比例繪示。此外，這些圖式可能無法反映實際結構、特徵或層的實際幾何形狀。為了顯示目的，可能刻意地添加了一些結構、層或幾何形狀。
請參照第3圖，方法300開始於操作310，在第1和2圖所示的閘極堆疊物開口155中奈米片層115的暴露表面上形成介電堆疊物的製程。依據一些實施例，第4圖為在方法300的操作310之後，沿第1圖的切割線200的半成品的奈米片場效電晶體100。在一些實施例中，第4圖顯示半成品的奈米片場效電晶體100，觀看者看到間隙壁160之間並沿第1圖的y軸的閘極堆疊物開口155中的奈米片層115。
依據第4圖，形成介電堆疊物400以圍繞在間隙壁160之間懸置的奈米片層115。在一些實施例中，介電堆疊物400為包含介面層400A和高介電常數層400B的閘極介電堆疊物。可以注意的是，介電堆疊物400的前述層的形成不限於奈米片層115。舉例來說，介面層400A也形成於鰭結構120不被絕緣層135覆蓋的表面上(例如在鰭結構120的頂表面上)，而高介電常數層400B也形成於絕緣層135上及鰭結構120上方的介面層400A上。
在一些實施例中，介面層400A透過將奈米片層115的矽表面暴露於氧化環境來形成。作為範例而非限制，氧化環境可包含臭氧(O3 )、氫氧化氨/過氧化氫/水的混合物(SC1)以及鹽酸/過氧化氫/水的混合物(SC2)的組合。作為前述氧化製程的結果，在約5Å與約15Å之間的SiO2 層形成於暴露的矽表面上，例如形成於鰭結構120不被絕緣層135和奈米片層115覆蓋的表面上。
在一些實施例中，高介電常數層400B為有著介電常數值(k值)大於約3.9的介電質。作為範例而非限制，高介電常數層400B可包含氧化鉿、氧化鑭、氧化鋁、氧化釔或前述之組合透過原子層沉積或電漿輔助原子層沉積來沉積厚度在約10Å與約20Å之間。
在一些實施例中，在沉積介電堆疊物400之後，可進行一系列的犧牲蓋層和尖端退火操作，以改善介電堆疊物400的電氣特性。作為範例而非限制，第一犧牲蓋層(未顯示於第4圖)可沉積於介電堆疊物400上，接著在氮氣環境中進行第一尖端退火，以改善高介電常數層400B的品質。作為範例而非限制，第一犧牲蓋層可包含氮化鈦矽(TiSiN)，且透過使用四氯化鈦(TiCl4 )、矽烷(SiH4 )和氨(NH3 )的原子層沉積製程沉積厚度在約10Å與約20Å之間。再者，第一尖端退火可在溫度約850°C與約950°C之間的範圍中持續約1秒或更少的時間。
在一些實施例中，第二犧牲蓋層(未顯示於第4圖)可沉積於第一犧牲蓋層上，接著在氮氣環境中在溫度約900°C與約950°C之間進行第二尖端退火。依據一些實施例，第二尖端退火促進介面層400A和高介電常數層400B的部分混合以及介電堆疊物400中的電偶極的形成，其可幫助主要對於p型奈米片場效電晶體設定功函數。作為範例而非限制，第二犧牲蓋層可為透過使用二矽烷(Si2 H6 )和氫在溫度約350°C與約450°C之間的化學氣相沉積製程沉積的矽層。在一些實施例中，第二犧牲蓋層可沉積厚度在約20Å與約30Å之間。
在一些實施例中，在溫度約850°C與約950°C之間進行第三尖端退火之前，移除第一犧牲蓋層和第二犧牲蓋層。依據一些實施例，第三尖端退火在NH3 中進行，以將氮引入高介電常數層400B中，並改善介電堆疊物400的整體可靠性。
請參照第3和5圖，方法300繼續至操作320，在介電堆疊物400正上方沉積一個或多個p型功函數層以形成p型功函數堆疊物500的製程顯示於第5圖中。本文使用的術語“p型功函數層”是指主要用於調整p型奈米片場效電晶體的臨界電壓，且以較小程度調整n型奈米片場效電晶體的臨界電壓的功函數層。為了方便製造，在n型奈米片場效電晶體和p型奈米片場效電晶體上都有p型功函數層。在一些實施例中，每個p型功函數層包含鈦及/或氮(例如氮化鈦(TiN)的形式)，且具有厚度在約5Å與約35Å之間。
p型電晶體的臨界電壓的調整可透過控制p型功函數層的數量或p型功函數堆疊物500的總厚度來完成。舉例來說，在p型功函數堆疊物500中的p型功函數層的數量越多，或p型功函數堆疊物500越厚，p型電晶體的臨界電壓值越低。因此，如上所述，可在同一晶片中形成不同功率應用之具有不同臨界電壓的電晶體。如上所述，p型功函數層的存在對p型奈米片場效電晶體具有很強的影響，而n型奈米片場效電晶體可能不受p型功函數層的存在影響。在一些實施例中，相較於p型奈米片場效電晶體，n型奈米片場效電晶體接收較少數量的p型功函數層，或具有較薄的p型功函數堆疊物500。
有著不同數量的p型功函數層或具有不同厚度的p型功函數堆疊物500的電晶體可透過光微影和蝕刻操作完成。作為範例而非限制，第一p型功函數層可同時沉積於晶片的n型和p型電晶體上。在一些實施例中，後續以光阻遮蔽接收最大數量的p型功函數層的電晶體，使得可以透過蝕刻從接收較少p型功函數層的電晶體移除第一p型功函數層。當從接收較少p型功函數層的電晶體移除第一p型功函數層之後，從接收最大數量的p型功函數層的電晶體移除光阻，且此製程在第二p型功函數層沉積時繼續。之後，使用光阻以遮蔽接收最大數量和第二最大數量的p型功函數層的電晶體。後續的蝕刻製程從接收較少p型功函數層的電晶體移除第二p型功函數層。重複前述順序直到所有電晶體(p型和n型)接收合適數量的p型功函數層(例如n型奈米片場效電晶體為1至3個，p型奈米片場效電晶體為4至6個)。
在上述製程之後，p型功函數堆疊物500中的最後的p型功函數層(例如最上層)同時沉積於所有的電晶體(p型和n型)上。前述的p型功函數形成順序並非限制性，且可使用相似或不同的操作進行其他順序。然而，對於方法300，重要的是，如上所述，p型功函數堆疊物500中的最後的p型功函數層(例如最上層)對於n型和p型電晶體為共用的。
作為範例而非限制，p型功函數堆疊物500的每個p型功函數層可在沉積溫度約400°C與約450°C之間使用TiCl4 和NH3 的原子層沉積製程沉積。再者，在移除光阻之後，p型功函數層的移除可以SC1或SC2的濕清潔來達成。如以上所討論，p型功函數堆疊物500的每個p型功函數層由於其獨立沉積而可具有不同的厚度。
請參照第3圖，方法300繼續至操作330，以不破真空的方式在一個或多個p型功函數層正上方形成無鋁n型功函數層(即不包含鋁的n型功函數層)的製程。換句話說，請參照第6圖，在p型功函數堆疊物500的最後p型功函數層的沉積之後，操作330以不破真空的方式(例如原位)形成無鋁n型功函數層600。此意味著無鋁n型功函數層600的形成可在用於p型功函數層的相同沉積反應器中進行，或在與用於p型功函數層的沉積反應器安裝在相同的主機上的不同反應器中進行。在一些實施例中，無鋁n型功函數層600包含金屬矽化物(例如TiSix 、TaSix 、CoSix 或NiSix )，且沉積於n型和p型奈米片場效電晶體上。作為範例，將在TiSix 或TaSix 的背景下描述無鋁n型功函數層600。基於本文的揭露內容，可使用上述的其他材料。這些材料在本發明實施例的精神和範圍中。
依據一些實施例，無鋁n型功函數層600可透過原子層沉積製程形成，原子層沉積製程包含將p型功函數堆疊物500的最後沉積p型功函數層依序地浸入TiCl4 (或氯化鉭(TaCl5 ))蒸氣和SiH4 氣體，以形成有著厚度在約5Å與約10Å之間的TiSix (或TaSix )層。在TiCl4 (或TaCl5 )蒸氣中的第一浸泡可持續約50秒至約150秒，而在SiH4 氣體中的第二浸泡可持續約180秒至約400秒。在一些實施例中，對於TiCl4 (或TaCl5 )蒸氣和SiH4 氣體，分別比50秒和180秒更短的浸泡時間可能無法產生完全形成的無鋁n型功函數層600，且可能需要兩次以上的連續浸泡，其可能增加整體加工時間。相反地，對於TiCl4 (或TaCl5 )蒸氣和SiH4 氣體，分別比150秒和400秒更長的浸泡時間可能不必要地延長加工時間並增加製造成本。
在一些實施例中，在第一浸泡之後，在引入SiH4 氣體之前，從反應器將多餘的TiCl4 (或TaCl5 )蒸氣排氣(抽空)，以防止蒸氣與氣體之間的氣相反應，其可不控制地增加形成的無鋁n型功函數層600的成長速率。依據一些實施例，蒸氣的TiCl4 (或TaCl5 )分子化學吸附於p型功函數堆疊物500的表面上，並與SiH4 氣體化學反應以形成TiSix (或TaSix )層(例如無鋁n型功函數層600)。在一些實施例中，基於上述的加工條件，可能需要兩次以上的連續浸泡。
如上所述，相對於p型功函數沉積製程，在TiCl4 (或TaCl5 )蒸氣中的第一浸泡和在SiH4 氣體中的第二浸泡為原位進行(例如不破真空)。這是為了防止由於潛在的破真空而在p型功函數堆疊物500與無鋁n型功函數層600之間引入氧分子，其可使電晶體的臨界電壓偏離期望值。在一些實施例中，TiSix (或TaSix )的n型功函數層比TiAl、TiAlC的n型功函數層具有更強的抗氧化性。因此，TiSix (或TaSix )的n型功函數層可比TiAl、TiAlC的n型功函數層形成地更薄，但是提供等效調製的臨界電壓。舉例來說，TiSix (或TaSix )的n型功函數層可比TiAl、TiAlC的n型功函數層薄約10Å或更薄。如上所述，更薄的n型功函數層可緩和奈米片間距在約8nm與約12nm之間的奈米片場效電晶體的閘極堆疊物中的間隙填充問題。
在一些實施例中，無鋁n型功函數層600在溫度約400°C與約450°C之間的範圍中形成，其有利地與p型功函數層的沉積匹配。
依據一些實施例，如第6圖所示，無鋁n型功函數層600也形成於絕緣層135和鰭結構120上方的p型功函數堆疊物500上的閘極堆疊物開口155的底部。
請參照第3圖，方法300繼續至操作340，在無鋁n型功函數層600上沉積金屬填充物，以圍繞第1和2圖所示的奈米片層115並填充閘極堆疊物開口155的製程。作為範例而非限制，第7圖顯示依據方法300的操作340，在形成金屬填充物700之後的半成品的奈米片場效電晶體100。在一些實施例中，金屬填充物700包含成核層(位顯示於第7圖)，成核層具有厚度在約15Å與約30Å之間。在一些實施例中，金屬填充物700包含在溫度約300°C與約400°C之間使用六氟化鎢(WF6 )和氫(H2 )的化學氣相沉積製程沉積的鎢(W)金屬。無氟的鎢成核層(即不包含氟的成核層)可在溫度約400°C與約480°C之間使用氯化鎢(V)(W2 Cl10 )的原子層沉積製程沉積。在一些實施例中，無氟成核層作為金屬填充物700的黏著層且作為氟的擴散阻障。
在一些實施例中，介電堆疊物400、p型功函數堆疊物500、無鋁n型功函數層600和金屬填充物700共同形成閘極堆疊物，閘極堆疊物圍繞奈米片層115並填充閘極填充物開口。作為範例而非限制，第8圖顯示在第3圖描述的方法300完成之後的最終奈米片場效電晶體100。
作為範例而非限制，第9A和9B圖為使用第3圖所示的方法300形成的n型奈米片場效電晶體100n和p型奈米片場效電晶體100p的等角視圖。如上所述，n型奈米片場效電晶體100n的p型功函數堆疊物500p比p型奈米片場效電晶體100p的p型功函數堆疊物500p包含更少的p型功函數層。出於此原因，n型奈米片場效電晶體100n的p型功函數堆疊物500p看起來比p型奈米片場效電晶體100p的p型功函數堆疊物500p更薄。
作為範例而非限制，第11圖顯示使用方法300形成的n型奈米片場效電晶體A、B和C以及p型奈米片場效電晶體D、E和F的剖面示意圖。如上所述，p型奈米片場效電晶體D、E和F比n型奈米片場效電晶體A、B和C具有更大數量的p型功函數層500x(其中x為a到e)。在第11圖的範例中，n型奈米片場效電晶體A、B和C可具有多達3個p型功函數層500a、500b和500c，而p型奈米片場效電晶體D、E和F可具有多達6個p型功函數層(例如500a到500e)。在一些實施例中，隨著p型功函數層的數量增加，n型奈米片場效電晶體的臨界電壓提高。舉例來說，n型奈米片場效電晶體A具有比n型奈米片場效電晶體B和C更低的臨界電壓，且n型奈米片場效電晶體B具有比n型奈米片場效電晶體C更低的臨界電壓。相反地，隨著p型功函數層的數量增加，p型奈米片場效電晶體的臨界電壓降低。舉例來說，p型奈米片場效電晶體D具有比p型奈米片場效電晶體E和F更高的臨界電壓，且p型奈米片場效電晶體E具有比p型奈米片場效電晶體F更高的臨界電壓。
依據一些實施例，方法300不限於閘極環繞奈米片場效電晶體，而可應用於其他電晶體，例如鰭式場效電晶體、平面電晶體或由於微縮化需求而需成長較薄的n型功函數層的電晶體。
相對於鋁基n型功函數層(例如TiAl和TiAlC)，本文描述的實施例為有關於有著無鋁n型功函數層的電晶體的製造方法。依據一些實施例，無鋁n型功函數層可具有厚度在約0.5nm與約1.5nm之間，此厚度比鋁基n型功函數層更薄至少約10Å。因此，本文描述的無鋁n型功函數層可緩和不佳的閘極堆疊物間隙填充所帶來的挑戰，例如在有著挑戰性的閘極堆疊物幾何形狀的電晶體中存在的高閘極堆疊物電阻和可靠性問題。在一些實施例中，無鋁n型功函數層包含TiSix 、TaSix 、CoSix 或NiSix 。依據一些實施例，本文描述的無鋁n型功函數層與p型功函數層原位形成(例如沒有破真空)。因此，可防止或減少不期望的氧混入功函數層中。
在一些實施例中，半導體結構包含位於基底上的鰭結構以及位於鰭結構上的垂直堆疊物。垂直堆疊物包含第一部分和第二部分，其中第一部分和第二部分的每一者具有交替的第一和第二奈米片層。垂直堆疊物更包含設置於第一和第二部分之間的第三部分，第三部分有著第二奈米片層且沒有第一奈米片層，其中第二奈米片層從垂直堆疊物的第一部分通過第三部分延伸至第二部分。半導體結構更包含設置於垂直堆疊物的第三部分上的閘極結構。再者，閘極結構圍繞第三部分中的第二奈米片層，且包含形成於第三部分的第二奈米片層上的介電堆疊物、介電堆疊物上的功函數堆疊物、功函數堆疊物上的無鋁功函數層以及圍繞第三部分中的第二奈米片層且在垂直堆疊物的第一和第二部分之間的金屬填充物。
在一些其他實施例中，上述半導體結構更包括:間隙壁，設置於閘極結構與兩隔開的源極/汲極磊晶堆疊物的每一者之間，其中間隙壁圍繞複數個奈米片層不被閘極結構圍繞的部分；以及絕緣層，圍繞閘極結構和兩隔開的源極/汲極磊晶堆疊物。
在一些其他實施例中，其中功函數層包括一個或複數個p型功函數層。
在一些其他實施例中，其中無鋁功函數層包括金屬矽化物。
在一些其他實施例中，其中無鋁功函數層包括矽化鈦、矽化鉭、矽化鈷或矽化鎳。
在一些其他實施例中，其中無鋁功函數層具有厚度在約5Å與約15Å之間。
在一些其他實施例中，其中複數個奈米片層包括矽。
在一些其他實施例中，其中複數個奈米片層之間的間距在約8nm與約12nm之間。
在一些實施例中，半導體結構包含設置於兩隔開的源極/汲極磊晶層之間的奈米片通道部，其中奈米片通道部包括垂直堆疊且間隔開的兩個或多個奈米片層。半導體結構也包含設置於奈米片通道部上並圍繞奈米片通道部的兩個或多個奈米片層的閘極堆疊物，其中閘極堆疊物包含設置於奈米片通道部的兩個或多個奈米片層上的介電層、位於介電層上的一或多個p型功函數層、位於一或多個p型功函數層上的無鋁n型功函數層及位於奈米片通道部的兩個或多個奈米片層之間的金屬。
在一些其他實施例中，其中無鋁n型功函數層包括金屬矽化物。
在一些其他實施例中，其中金屬矽化物包括鈦、鉭、鈷或鎳。
在一些其他實施例中，其中一或多個p型功函數層包括氮化鈦。
在一些其他實施例中，其中兩個或多個奈米片層的間距在約8nm與約12nm之間。
在一些其他實施例中，其中無鋁n型功函數層具有厚度在約5Å與約15Å之間。
在一些實施例中，一方法包含在兩隔開的源極/汲極磊晶層之間形成通道部，以及在通道部上形成閘極堆疊物，其中形成閘極堆疊物的步驟包含:在通道部上沉積高介電常數介電層以及在高介電常數介電層上沉積p型功函數層。在沉積p型功函數層之後，以不破真空的方式在p型功函數層上形成無鋁n型功函數層，及在無鋁n型功函數層上沉積金屬。此方法更包含沉積絕緣層，以圍繞兩隔開的源極/汲極磊晶層和閘極堆疊物。
在一些其他實施例中，其中形成無鋁n型功函數層的步驟包括:將p型功函數層暴露於四氯化鈦蒸氣約50秒至約150秒；以及在將p型功函數層暴露於四氯化鈦蒸氣之後，將p型功函數層暴露於矽烷氣體約180秒至約400秒，以形成矽化鈦。
在一些其他實施例中，其中形成無鋁n型功函數層的步驟包括:將p型功函數層暴露於四氯化鉭蒸氣約50秒至約150秒；以及在將p型功函數層暴露於四氯化鉭蒸氣之後，將p型功函數層暴露於矽烷氣體約180秒至約400秒，以形成矽化鉭。
在一些其他實施例中，其中形成無鋁n型功函數層的步驟包括沉積無鋁n型功函數層厚度在約5Å與約15Å之間。
在一些其他實施例中，其中形成無鋁n型功函數層的步驟包括以溫度約400°C與約450°C之間沉積無鋁n型功函數層。
在一些其他實施例中，其中形成無鋁n型功函數層的步驟包括沉積矽化鈦、矽化鉭、矽化鈷或矽化鎳。
應當理解的是，實施方式的部分而非發明摘要為用於解釋申請專利範圍。發明摘要的部分可闡述所考慮的一個或多個實施例，但不是所有的例示性實施例，因此不意圖限制所附上的申請專利範圍。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明進行各種改變、置換或修改。
100:奈米片場效電晶體 100n,A,B,C:n型奈米片場效電晶體 100p,D,E,F:p型奈米片場效電晶體 105:奈米片堆疊物 105H:高度 115:奈米片層 120:鰭結構 125:基底 130:襯墊 135:絕緣層 140:源極/汲極磊晶堆疊物 145:蓋層 150:隔離層 155:閘極堆疊物開口 160:間隙壁 200:切割線 300:方法 310,320,330,340:操作 400:介電堆疊物 400A:介面層 400B:高介電常數層 500,500a,500b,500c,500d,500e,500n,500p:p型功函數堆疊物 600:無鋁n型功函數層 700:金屬填充物
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1和2圖為依據一些實施例之半成品的全環繞式閘極奈米片場效電晶體結構的等角視圖。 第3圖為依據一些實施例之製造有著無鋁n型功函數層的閘極堆疊物的全環繞式閘極奈米片場效電晶體結構的方法的流程圖。 第4-7圖為依據一些實施例之製造有著無鋁n型功函數層的閘極堆疊物的全環繞式閘極奈米片場效電晶體結構期間的剖面示意圖。 第8圖為依據一些實施例之有著無鋁n型功函數層的全環繞式閘極奈米片場效電晶體結構的等角視圖。 第9A和9B圖分別為依據一些實施例之有著無鋁n型功函數層的n型全環繞式閘極奈米片場效電晶體結構和p型全環繞式閘極奈米片場效電晶體結構的等角視圖。 第10圖為依據一些實施例之半成品的全環繞式閘極奈米片場效電晶體結構的剖面示意圖。 第11圖為使用第3圖的方法形成的n型奈米片場效電晶體和p型奈米片場效電晶體的剖面示意圖。
100:奈米片場效電晶體
115:奈米片層
120:鰭結構
125:基底
130:襯墊
135:絕緣層
400:介電堆疊物
400A:介面層
400B:高介電常數層
500:p型功函數堆疊物
600:無鋁n型功函數層
700:金屬填充物

Claims (12)

  1. 一種半導體結構，包括：一鰭結構，位於一基底上；兩隔開的源極/汲極磊晶堆疊物，形成於該鰭結構的頂表面上；複數個奈米片層，設置於該兩隔開的源極/汲極磊晶堆疊物之間，其中該複數個奈米片層間隔開；以及一閘極結構，圍繞該複數個奈米片層，其中該閘極結構包括：一介電堆疊物，圍繞該複數個奈米片層形成；一功函數層，圍繞該介電堆疊物形成；一無鋁功函數層，圍繞該功函數層形成，其中該無鋁功函數層包括金屬矽化物；以及一金屬層，圍繞該無鋁功函數層形成。
  2. 如請求項1之半導體結構，更包括：一間隙壁，設置於該閘極結構與該兩隔開的源極/汲極磊晶堆疊物的每一者之間，其中該間隙壁圍繞該複數個奈米片層不被該閘極結構圍繞的一部分；以及一絕緣層，圍繞該閘極結構和該兩隔開的源極/汲極磊晶堆疊物。
  3. 如請求項1或2之半導體結構，其中該功函數層包括一個或複數個p型功函數層。
  4. 如請求項1或2之半導體結構，其中該無鋁功函數層包括矽化鈦、矽化鉭、矽化鈷或矽化鎳。
  5. 一種半導體結構，包括： 一奈米片通道部，設置於兩隔開的源極/汲極磊晶層之間，其中該奈米片通道部包括垂直堆疊且間隔開的兩個或多個奈米片層；以及一閘極堆疊物，設置於該奈米片通道部上，並圍繞該奈米片通道部的該兩個或多個奈米片層，其中該閘極堆疊物包括：一介電層，設置於該奈米片通道部的該兩個或多個奈米片層上；一或多個p型功函數層，位於該介電層上；一無鋁n型功函數層，位於該一或多個p型功函數層上，其中該無鋁n型功函數層包括一金屬矽化物；及一金屬，位於該奈米片通道部的該兩個或多個奈米片層之間。
  6. 如請求項5之半導體結構，其中該金屬矽化物包括鈦、鉭、鈷或鎳。
  7. 如請求項5或6之半導體結構，其中該一或多個p型功函數層包括氮化鈦。
  8. 一種半導體結構的形成方法，包括：在兩隔開的源極/汲極磊晶層之間形成一通道部；在該通道部上形成一閘極堆疊物，其中形成該閘極堆疊物的步驟包括：在該通道部上沉積一高介電常數介電層；在該高介電常數介電層上沉積一p型功函數層；在沉積該p型功函數層之後，以不破真空的方式在該p型功函數層上形成一無鋁n型功函數層；及在該無鋁n型功函數層上沉積一金屬；以及沉積一絕緣層，以圍繞該兩隔開的源極/汲極磊晶層和該閘極堆疊物。
  9. 如請求項8之半導體結構的形成方法，其中形成該無鋁n型功函數層的步驟包括：將該p型功函數層暴露於四氯化鈦蒸氣約50秒至約150秒；以及在將該p型功函數層暴露於四氯化鈦蒸氣之後，將該p型功函數層暴露於矽烷氣體約180秒至約400秒，以形成矽化鈦。
  10. 如請求項8之半導體結構的形成方法，其中形成該無鋁n型功函數層的步驟包括：將該p型功函數層暴露於四氯化鉭蒸氣約50秒至約150秒；以及在將該p型功函數層暴露於四氯化鉭蒸氣之後，將該p型功函數層暴露於矽烷氣體約180秒至約400秒，以形成矽化鉭。
  11. 如請求項8至10中任一項之半導體結構的形成方法，其中形成該無鋁n型功函數層的步驟包括以溫度約400℃與約450℃之間沉積該無鋁n型功函數層。
  12. 如請求項8至10中任一項之半導體結構的形成方法，其中形成該無鋁n型功函數層的步驟包括沉積矽化鈦、矽化鉭、矽化鈷或矽化鎳。
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