CN111987159A - 半导体结构和形成半导体结构的方法 - Google Patents

半导体结构和形成半导体结构的方法 Download PDF

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CN111987159A
CN111987159A CN202010268836.5A CN202010268836A CN111987159A CN 111987159 A CN111987159 A CN 111987159A CN 202010268836 A CN202010268836 A CN 202010268836A CN 111987159 A CN111987159 A CN 111987159A
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work function
layer
type work
aluminum
nanosheet
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CN111987159B (zh
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程仲良
方子韦
吴俊毅
赵皇麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本文所述的实施例针对用于制造具有与基于铝的n型功函层相反的无铝n型功函层的晶体管的方法。该方法包括：形成设置在间隔开的源极/漏极外延层之间的沟道部分，以及在沟道部分上形成栅极堆叠件，其中，形成栅极堆叠件包括在沟道部分上沉积高k介电层并在介电层上沉积p型功函层。在沉积p型功函层之后，在没有真空破坏的情况下，在p型功函层上形成无铝n型功函层，并且在无铝n型功函层上沉积金属。该方法还包括沉积围绕间隔开的源极/漏极外延层和栅极堆叠件的绝缘层。本发明的实施例还涉及半导体结构和形成半导体结构的方法。

Description

半导体结构和形成半导体结构的方法
技术领域
本发明的实施例涉及半导体结构和形成半导体结构的方法。
背景技术
晶体管(例如，n型或p型晶体管)的阈值电压可以通过调整晶体管的栅极结构内的功函层的厚度来调节。然而，按比例缩小晶体管栅极结构以制造更小的器件给阈值电压调节带来了挑战，因为功函层厚度的调整由于晶体管尺寸的减小而受到限制。
发明内容
本发明的一些实施例提供了一种半导体结构，包括：鳍结构，位于衬底上；两个间隔开的源极/漏极外延堆叠件，形成在所述鳍结构的顶面上；纳米片层，设置在所述两个间隔开的源极/漏极外延堆叠件之间，其中，所述纳米片层间隔开；以及栅极结构，围绕所述纳米片层，其中，所述栅极结构包括：介电堆叠件，形成为围绕所述纳米片层；功函堆叠件，形成为围绕所述介电堆叠件；无铝功函层，形成为围绕所述功函堆叠件；和金属层，形成为围绕所述无铝功函层。
本发明的另一些实施例提供了半导体结构，包括：纳米片沟道部分，设置在间隔开的源极/漏极外延层之间，其中，所述纳米片沟道部分包括垂直堆叠并间隔开的两个或更多个纳米片层；以及栅极堆叠件，设置在所述纳米片沟道部分上并围绕所述纳米片沟道部分的两个或更多个纳米片层，其中，所述栅极堆叠件包括：介电层，设置在所述纳米片沟道部分的两个或更多个纳米片层上；一个或多个p型功函层，位于所述介电层上；无铝n型功函层，位于所述一个或多个p型功函层上；以及金属，位于所述纳米片沟道部分的两个或更多个纳米片层之间。
本发明的又一些实施例提供了一种形成半导体结构的方法，包括：形成设置在间隔开的源极/漏极外延层之间的沟道部分；在所述沟道部分上形成栅极堆叠件，其中，形成所述栅极堆叠件包括：在所述沟道部分上沉积高k介电层；在所述高k介电层上沉积p型功函层；在沉积所述p型功函层之后，在不发生真空破坏的情况下，在所述p型功函层上形成无铝n型功函层；和在无铝n型功函层上沉积金属；以及沉积围绕所述间隔开的源极/漏极外延层和所述栅极堆叠件的绝缘层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1和图2是根据一些实施例的部分制造的全环栅纳米片FET结构的等轴视图。
图3是根据一些实施例的用于制造具有用于全环栅纳米片FET的无铝n型功函层的栅极堆叠件的方法的流程图。
图4至图7是根据一些实施例的在具有用于全环栅纳米片FET的无铝n型功函层的栅极堆叠件的制造期间的截面图。
图8是根据一些实施例的具有无铝n型功函层的全环栅纳米片FET结构的等轴视图。
图9A和图9B是根据一些实施例的具有无铝n型功函层的相应n型和p型全环栅纳米片FET结构的等轴视图。
图10是根据一些实施例的部分制造的全环栅纳米片FET结构的截面图。
图11示出了使用图3所示的方法形成的全环栅纳米片FET的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文使用的术语“标称”是指在产品或工艺的设计阶段期间设定的组件或工艺操作的特性或参数的期望值或目标值，以及高于期望值和/或低于期望值的值的范围。值的范围通常由于制造工艺或公差而轻微变化。
在一些实施例中，术语“约”和“基本”可以表示在目标值的5％内变化(例如，目标值的±1％、±2％、±3％、±4％和±5％)的给定量的值。
本文使用的术语“垂直”意味着标称垂直于衬底的表面。
本文使用的术语“绝缘层”是指用作电绝缘体的层(例如，介电层)。
场效应晶体管(FET)的栅极结构或栅极堆叠件内的层部分地控制晶体管的阈值电压。更具体地，晶体管的阈值电压值取决于其栅极堆叠件中所包括的层的总厚度和类型。因此，通过控制每个FET中这些层的厚度(或层的数量)，可以制造具有不同阈值电压的FET。例如，具有低阈值电压(例如，在约80mV和约160mV之间)的FET可用于芯片内的“低”或“超低”功率应用，而具有高阈值电压(例如，大于约200mV)的FET可用于芯片内的高功率应用。
由于器件的持续按比例缩小以及低功率便携式器件(例如，移动电话、智能手表和其他可穿戴电子器件、平板电脑等)的推动，需要具有较低阈值电压的晶体管的集成电路(IC)。P型FET和N型FET可以具有不同的“绝对”阈值电压值(例如，阈值电压的大小而不考虑其符号)，因为它们的栅极堆叠件中包含不同类型和/或数量的金属层。例如，p型FET具有比n型FET更高的阈值电压，因此需要更高的电压来导通(例如，以允许电流在晶体管的源极和漏极端子之间流动)。出于这个原因，与p型FET相比，n型FET可以称为“较强”，并且与n型FET相比，p型FET可以称为“较弱”。
在n型FET中，进一步减小(例如，降低)阈值电压的一种方式是增加形成在FET的栅极堆叠件中的诸如钛铝(TiAl)或钛铝碳(TiAlC)的含铝n型功函层的厚度。然而，TiAl或TiAlC层的厚度的增加可能受到具有挑战性的栅极堆叠件几何形状的FET的按比例缩小约束的限制，FET诸如全环栅(GAA)纳米片FET(以下称为“NSFET”)。例如，随着纳米片至纳米片间隔减小，用于TiAl或TiAlC层的可用空间缩小。因此，增加n型NSFET中的TiAl或TiAlC层的厚度可能变得具有挑战性。例如，由于纳米片至纳米片间隔较小(例如，在约8nm和约12nm之间)，现有的或更厚的TiAl或TiAlC层(例如，等于或大于约2.5nm)可能导致不良的栅极堆叠件间隙填充—进而可能导致栅极堆叠件中的空隙以及晶体管两端的栅极堆叠件电阻变化。
本文描述的实施例针对用于制造具有无铝n型功函层的晶体管的方法，该无铝n型功函层比诸如TiAl和TiAlC的基于铝的n型功函层薄。因此，本文描述的无铝n型功函层可以减轻由上述指出的不良栅极堆叠件间隙填充引起的挑战。在一些实施例中，无铝n型功函层可以生长到约
Figure BDA0002442152720000041
和约
Figure BDA0002442152720000042
之间的厚度，该厚度比基于铝的n型功函层薄至少约
Figure BDA0002442152720000043
在一些实施例中，无铝n型功函层包括硅化钛(TiSix)、硅化钽(TaSix)、硅化钴(CoSix)或硅化镍(NiSix)，并且与栅极堆叠件的p型功函层原位形成(例如，没有真空破坏)。
图1和图2是在去除牺牲栅极堆叠件之后的部分制造的NSFET 100的等轴视图。在一些实施例中，图2示出了在绕z轴逆时针旋转约45°之后的图1的部分制造的NSFET 100。换句话说，图2是图1所示的制造的NSFET 100的另一视图。如图1所示，部分制造的NSFET 100包括具有间隔开的纳米片层115的一个或多个的多层纳米片堆叠件105。在一些实施例中，纳米片层115在较早的制造操作期间作为图2所示的鳍结构120的一部分外延生长。在一些实施例中，纳米片层115包括晶体硅(Si)并形成用于部分制造的NSFET 100的沟道区域。可选地，纳米片层115可以包括硅锗(SiGe)；诸如砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)或氮化镓(GaN)的III-V族化合物半导体。出于示例性目的，将在间隔开的Si纳米片层115的上下文中描述部分制造的NSFET 100中的纳米片堆叠件105。基于本文的公开内容，可以使用如上所述的其他材料。这些材料在本公开的精神和范围内。作为示例而非限制，可用于Si纳米片层115的生长的前体气体包括硅烷(SiH4)、乙硅烷(Si2H6)、任何其他合适的气体或他们的组合。
在一些实施例中，纳米片层115可以具有相同或不同的厚度。根据一些实施例，每个Si纳米片层115的厚度可以在从约5nm至约8nm的范围内。在一些实施例中，Si纳米片层115具有与纳米片多层堆叠件105的宽度匹配的相等宽度(例如，沿着图1的x轴)。作为示例而非限制，Si纳米片层115的宽度可以在从约15nm至约50nm的范围内。
在一些实施例中，每个纳米片堆叠件105可包括多达约10至12个总的纳米片层。然而，取决于部分制造的NSFET 100的设计，额外的或更少的纳米片层105是可能的。在一些实施例中，多层纳米片堆叠件105的高度105H可以在约100nm至约200nm之间的范围内。用于纳米片层115和纳米片堆叠件105的前述厚度和高度范围不是限制性的。
参照图2，在衬底125上形成鳍结构120。作为示例而非限制，鳍结构120和衬底125包括诸如晶体硅的半导体材料。在一些实施例中，鳍结构120和衬底125可包括(i)另一元素半导体，诸如锗(Ge)；以及(ii)化合物半导体，包括碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)和/或锑化铟(InSb)；(iii)合金半导体，包括硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)和/或磷砷化镓铟(GaInAsP)；或(iv)他们的组合。出于示例目的，将在晶体硅(Si)的上下文中描述形成在衬底125上的鳍结构120。基于本文的公开内容，可以使用如上所述的其他材料。这些材料在本公开的精神和范围内。
鳍结构120可以通过任何合适的方法图案化形成。例如，可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺来图案化鳍结构120。双重图案化或多重图案化工艺可以结合光刻和自对准工艺，从而允许创建例如间距小于使用单个直接光刻工艺所获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后可以使用剩余的间隔件来图案化鳍结构120。
如图1和图2所示，部分制造的NSFET 100包括附加的结构元件，诸如衬垫130、绝缘层135、生长在鳍结构120上的源极/漏极(S/D)外延堆叠件140、覆盖层145、隔离层150、形成在隔离层150中的栅极堆叠件开口155，以及形成在栅极堆叠件开口155中的隔离层150的侧壁表面上的间隔件160。在一些实施例中，S/D外延堆叠件140在隔离层150的整个厚度内沿y轴延伸并且邻接间隔件160。在一些实施例中，片层115横穿间隔件160并与S/D外延堆叠件140接触，如图10所示。
在一些实施例中，绝缘层135可以是电隔离鳍结构120的隔离结构(诸如浅沟槽隔离(STI))，并且包括氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、氟掺杂的硅酸盐玻璃(FSG)、磷掺杂的硅酸盐玻璃(PSG)、低k介电材料(例如，k值小于约3.9)和/或具有适当填充属性的其他合适的介电材料。在一些实施例中，衬垫130是氮化物层，诸如Si3N4。
在一些实施例中，外延堆叠件140可以是适合于p型NSFET的硼掺杂(B掺杂)的SiGe堆叠件，或适合于n型NSFET的磷掺杂(P掺杂)的Si层。在一些实施例中，可以使用硅烷(SiH4)前体外延生长P掺杂的(n型)SiS/D层。可以在生长期间将磷掺杂剂引入Si外延生长的层中。作为示例而非限制，磷浓度可以在从约1021原子/cm3至约8×1021原子/cm3的范围内。相反地，B掺杂(p型)SiGeS/D可以是外延堆叠件，其可以包括连续生长的两个或多个外延层(图1中未示出)，并且可以具有不同的锗(Ge)原子％和不同的B掺杂剂浓度。作为示例而非限制，第一层可以具有范围在从0至约40％的Ge原子％，以及范围在从约5x1019原子/cm3至约1x1021原子/cm3的B掺杂剂浓度；第二外延层可以具有范围在从约20％至约80％的Ge原子％，以及范围在从约3x1020原子/cm3至约5x1021原子/cm3的B掺杂剂浓度；并且第三外延层可以是覆盖层，该覆盖层可以具有与第一层相似的Ge原子％和B掺杂剂浓度(例如，0至约40％的Ge，和约5x1019原子/cm3至约1x1021原子/cm3的B掺杂剂)。这些层的厚度可以根据器件性能要求而变化。例如，第一外延层可以具有范围在从约10nm至约20nm的厚度，第二外延层可以具有范围在从约30nm至约60nm的厚度，并且第三外延层(覆盖层)可以具有范围在从0至约10nm的厚度。应该注意，上述厚度和掺杂浓度不是限制性的，并且其他厚度和掺杂浓度在本公开的精神和范围内。
在一些实施例中，覆盖层145可以具有范围在从约3nm至约5nm的厚度。作为示例而非限制，可以通过共形沉积工艺来沉积覆盖层145，该共形沉积工艺诸如原子层沉积(ALD)、等离子体增强的ALD(PEALD)、化学气相沉积(CVD)、等离子体增强CVD(PECVD)，或任何其他适当的沉积方法。在一些实施例中，覆盖层145在S/D外延堆叠件140上形成接触开口(图1中未示出)期间的后续蚀刻工艺中用作蚀刻停止层。
根据一些实施例，隔离层150是层间电介质(ILD)，其包括具有或不具有碳和/或氮的基于氧化硅的介电材料。隔离层150围绕S/D外延堆叠件140，并且在牺牲栅极堆叠件(其在图1中未示出)的去除之前形成。在牺牲栅极堆叠件的去除之后，在隔离层150中形成栅极堆叠件开口155，如图1所示。作为示例而非限制，隔离层150可以通过CVD、物理气相沉积(PVD)或任何其他适当的沉积方法来沉积。
最后，间隔件160可以包括介电材料，诸如SiON、碳氮化硅(SiCN)、碳氧化硅(SiOC)、Si3N4或它们的组合。在一些实施例中，间隔件160的厚度可以在从约2nm至约5nm的范围内。间隔件160可以是包括相同或不同材料的一个或多个层的堆叠件。根据一些实施例，间隔件160沉积在牺牲栅极堆叠件的侧壁表面上，之后在栅极替换工艺期间被去除以形成栅极堆叠件开口155。在图1中，间隔件160用作金属栅极堆叠件的结构元件，该金属栅极堆叠件将在随后的操作中形成在栅极堆叠件开口155中。
图3是根据一些实施例的描述用于具有无铝功函层的n型和p型NSFET的栅极堆叠件的制造的方法300的流程图。应该注意，制造方法300可以不限于纳米片晶体管，并且可以适用于具有将从较薄功函层中受益的几何形状的晶体管，诸如finFET、平面FET、纳米线FET等。
其他制造操作可以在方法300的各个操作之间实施，并且仅为了清楚起见可以省略。本公开不限于该操作描述。应当理解，可以实施附加操作。此外，可能不是所有的操作都必需来实施本文提供的公开。另外，一些操作可以同时实施，或者以与图3所示的不同的顺序实施。在一些实施例中，除了当前描述的操作之外或代替当前描述的操作，可以实施一个或多个其他操作。为了说明的目的，参照图1、图2和图4至图8所示的实施例描述制造方法300。提供为描述方法300的附图仅用于说明目的，并且未按比例绘制。另外，这些图可能无法反映真实结构、部件或层的实际几何形状。为了说明的目的，可能已经刻意增强了一些结构、层或几何形状。
参照图3，方法300开始于操作310以及在图1和图2所示的栅极堆叠件开口155内的纳米片层115的暴露表面上形成介电堆叠件的工艺。根据一些实施例，图4是在方法300的操作310之后沿切割线200的图1所示的部分制造的NSFET100。在一些实施例中，图4示出了部分制造的NSFET 100，如同观察者沿着图1的y轴观看间隔件160之间的栅极堆叠件开口155内的纳米片层115。
根据图4，介电堆叠件400形成为围绕间隔件160之间的悬浮纳米片层115。在一些实施例中，介电堆叠件400是包括界面层400A和高k层400B的栅极介电堆叠件。应该注意，介电堆叠件400的前述层的形成不限于纳米片层115。例如，界面层400A也形成在鳍结构120的未由绝缘层135覆盖的表面上(例如，形成在鳍结构120的顶面上)，并且高k层400B也形成在绝缘层135上以及鳍结构120上方的界面层400A上。
在一些实施例中，通过将纳米片层115的硅表面暴露于氧化环境来形成界面层400A。作为示例而非限制，氧化环境可以包括臭氧(O3)、氢氧化氨/过氧化氢/水混合物(SC1)和盐酸/过氧化氢/水混合物(SC2)的组合。由于上述氧化工艺，在暴露的硅表面(例如，鳍结构120的未由绝缘层135覆盖的表面和纳米片层115的表面)上形成介于约
Figure BDA0002442152720000081
和约
Figure BDA0002442152720000082
之间的SiO2层。
在一些实施例中，高k层400B是介电常数(k值)高于约3.9的电介质。作为示例而非限制，高k层400B可包括通过ALD或PEALD沉积的厚度在约
Figure BDA0002442152720000091
和约
Figure BDA0002442152720000092
之间的氧化铪、氧化镧、氧化铝、氧化钇或它们的组合。
在一些实施例中，在介电堆叠件400的沉积之后，可以实施一系列牺牲覆盖层和尖峰退火操作以改善介电堆叠件400的电特性。作为示例而非限制，可以在介电堆叠件400上沉积第一牺牲覆盖层(图4中未示出)，随后在氮气环境中进行第一尖峰退火以改善高k层400B的质量。作为示例而非限制，第一牺牲覆盖层可包括氮化钛硅(TiSiN)，并通过ALD工艺使用四氯化钛(TiCl4)、硅烷(SiH4)和氨气(NH3)沉积介于约
Figure BDA0002442152720000093
和约
Figure BDA0002442152720000094
之间的厚度。此外，可以在约850℃和约950℃之间的范围内的温度下实施第一尖峰退火约1s或更短。
在一些实施例中，可以在第一牺牲覆盖层上沉积第二牺牲覆盖层(图4中未示出)，随后在约900℃和约950℃之间的退火温度下在氮气环境中进行第二尖峰退火。根据一些实施例，第二尖峰退火促进(i)界面层400A和高k层400B之间的部分混合，以及(ii)介电堆叠件400中的电偶极子的形成，其可以主要帮助设置用于p型NSFET的功函数。作为示例而非限制，第二牺牲覆盖层可以是通过使用乙硅烷(Si2H6)和氢的CVD工艺在约350℃至约450℃之间的温度下沉积的硅层。在一些实施例中，第二牺牲覆盖层可以沉积为介于约
Figure BDA0002442152720000095
和约
Figure BDA0002442152720000096
之间的厚度。
在一些实施例中，在实施约850℃和约950℃之间的第三尖峰退火之前，去除第一牺牲覆盖层和第二牺牲覆盖层。根据一些实施例，第三尖峰退火在NH3中实施以将氮结合至高k层400B中并改善介电堆叠件400的整体可靠性。
参照图3和图5，方法300继续操作320以及将一个或多个p型功函层直接沉积在介电堆叠件400上以形成图5所示的p型功函堆叠件500的工艺。本文使用的术语“功函层”是指主要负责调节p型NSFET的阈值电压，并且以较小的程度调节n型NSFET的阈值电压的功函层。为了便于制造，在n型和p型NSFET上都存在p型功函层。在一些实施例中，每个p型功函层都包括钛和/或氮(例如，以氮化钛(TiN)的形式)，并且具有介于约
Figure BDA0002442152720000101
和约
Figure BDA0002442152720000102
之间的厚度。
可通过控制p型功函层的数量或p型功函堆叠件500的总厚度来实现对p型晶体管的阈值电压调节。例如，p型功函堆叠件500中更大数量的p型功函层，或者p型功函堆叠件500越厚，p型晶体管的阈值电压值越低。因此，如上所述，可以在同一芯片内形成用于不同功率应用的具有不同阈值电压的晶体管。如上所述，p型功函层的存在对p型NSFET具有很强的影响，而n型NSFET可能不受p型功函层存在的影响。在一些实施例中，与p型NSFET相比，n型NSFET接收较少数量的p型功函层，或者具有较薄的p型功函层堆叠件500。
具有不同数量的p型功函层或具有不同厚度的p型功函堆叠件500的晶体管可以通过光刻和蚀刻操作来实现。作为示例而非限制，第一p型功函层可同时沉积在芯片的n型和p型晶体管上。在一些实施例中，随后用光刻胶掩蔽接收最大数量的p型功函层的晶体管，使得可以通过蚀刻从接收较少的p型功函层的晶体管中去除第一p型功函层。一旦已经从接收较少的p型功函层的晶体管中去除第一p型功层，则从接收最大数量的p型功函层的晶体管去除光刻胶，并使用第二p型功函层沉积继续该工艺。随后使用光刻胶来掩蔽接收最大数量和第二最大数量的p型功函层的晶体管。随后的蚀刻工艺从接收较少的p型功函层的晶体管(与具有最大数量和第二最大数量的p型功函层的晶体管不同)中去除第二p型功函层。重复上述顺序，直至所有晶体管(p型和n型)接收适当数量的p型功函层(例如，对于n型NSFET为1至3，以及对于p型NSFET为4至6)。
在上述工艺之后，p型功函堆叠件500中的最后p型功函层(例如，最顶层)同时沉积在所有晶体管(p型和n型)上。前述p型功函层形成顺序不是限制性的，并且可以实施使用相似或不同操作的其他顺序。然而，对于方法300而言，重要的是，如上所述，n型和p型晶体管都共用p型功函堆叠件500的最后p型功函层(例如，最顶层)。
作为示例而非限制，可以在约400℃和约450℃之间的沉积温度下使用TiCl4和NH3通过ALD工艺沉积p型功函堆叠件500的每个p型功函层。此外，在去除光刻胶之后，可以通过SC1或SC2湿清洁来实现p型功函层的去除。如上所述，p型功函堆叠件500中的每个p型功函层可以具有不同的厚度，因为它是独立沉积的。
参照图3，方法300继续进行操作330以及在不发生真空破坏的情况下，直接在一个或多个p型功函层上形成无铝n型功函层(即，不包括铝的n型功函层)的工艺。换句话说，并且参考图6，操作330的无铝n型功函层600的形成是在p型功函层堆叠件500的最后p型功函层的沉积之后进行的，而没有真空破坏(例如，原位)。这意味着无铝n型功函层600的形成既可以在用于p型功函层的相同沉积反应器中进行，也可以与用于该p型功函层的沉积反应器安装在同一主机上的不同反应器中进行。在一些实施例中，无铝n型功函层600包括诸如TiSix、TaSix、CoSix或NiSix的金属硅化物，并且沉积在n型和p型NSFET上。出于示例的目的，将在TiSix或TaSix的上下文中描述无铝n型功函层600。基于本文的公开内容，可以使用如上所述的其他材料。这些材料在本公开的精神和范围内。
根据一些实施例，可以通过ALD工艺来形成无铝n型功函层600，该ALD工艺包括将p型功函堆叠件500的最后沉积的p型功函层连续地浸入TiCl4(或氯化钽(TaCl5))蒸气和SiH4气体中以形成厚度介于约
Figure BDA0002442152720000111
和约
Figure BDA0002442152720000112
Figure BDA0002442152720000113
之间的TiSix(或TaSix)层。第一次浸入TiCl4(或TaCl5)蒸汽中可以持续约50s至约150s，第二次浸入SiH4气体中可以持续约180s至约400s。在一些实施例中，对于TiCl4(或TaCl5)蒸气和SiH4气体，分别短于50s和80s的浸渍时间可能不会产生完全形成的无铝n型功函层600，并且可能需要两次以上的连续浸渍，这可能会增加整个处理时间。相反地，对于TiCl4(或TaCl5)蒸气和SiH4气体，分别超过150s和400s的浸渍时间可能会不必要地延长处理时间并增加制造成本。
在一些实施例中，在第一次浸渍之后，在引入SiH4气体之前从反应器中排出(例如，抽出)过量的TiCl4(或TaCl5)蒸气，以防止蒸气与气体之间的气相反应，该气相反应可能会不可控制地增加形成的无铝n型功函层600的生长速率。根据一些实施例，来自蒸气的TiCl4(或TaCl5)分子被化学吸附在p型功函堆叠件500的表面上，并且与SiH4气体发生化学反应以形成TiSix(或TaSix)层(例如，无铝n型功函层600)。在一些实施例中，基于如上所述的处理条件，可能需要两个以上的连续浸渍。
如上所述，相对于p型功函层沉积工艺，在TiCl4(或TaCl5)蒸气中的第一次浸渍和在SiH4气体中的第二次浸渍均原位(例如，没有真空破坏)实施。这是为了防止由于潜在的真空破坏而在p型功函堆叠件500和无铝n型功函层600之间引入分子氧，该真空破坏可使晶体管的阈值电压偏离期望值。在一些实施例中，TiSix(或TaSix)n型功函层比TiAl、TiAlCn型功函层更耐氧化。因此，可以将TiSix(或TaSix)n型功函层形成为比TiAl、TiAlCn型功函层薄，但提供等效的阈值电压调制。例如，TiSix(或TaSix)n型功函层可以形成为约
Figure BDA0002442152720000121
或比TiAl、TiAlCn型功函层薄。如上所述，较薄的n型功函层可以减轻纳米片间隔在约8nm与约12nm之间的NSFET的栅极堆叠件中的间隙填充问题。
在一些实施例中，无铝n型功函层600在约400℃和约450℃之间的范围内的温度下形成，这有利地与p型功函层的沉积温度匹配。
根据一些实施例，并且如图6所示，无铝n型功函层600也形成在绝缘层135和鳍结构120上方的p型功函堆叠件500上的栅极堆叠件开口155的底部处。
参照图3，方法300继续操作340，以及在无铝n型功函层600上沉积金属填充物以围绕纳米片层115并且填充图1和图2所示的栅极堆叠件开口155的工艺。作为示例而非限制，图7示出了根据方法300的操作340在形成金属填充物700之后的部分制造的NSFET 100。在一些实施例中，金属填充物700包括厚度介于约
Figure BDA0002442152720000122
和约
Figure BDA0002442152720000123
之间的成核层(未在图7中示出)。在一些实施例中，金属填充物700包括使用六氟化钨(WF6)和氢(H2)在约300℃和约400℃之间的范围内的温度下通过CVD沉积的钨(W)金属。可以在约400℃和约480℃之间的范围内的温度下使用ALD工艺使用氯化钨(V)(W2Cl10)沉积无氟W成核层(即，不包含氟的成核层)。在一些实施例中，无氟成核层用作用于金属填充物700的胶层和用作用于氟的扩散阻挡层。
在一些实施例中，介电堆叠件400、p型功函堆叠件500、无铝n型功函层600和金属填充物700共同形成围绕纳米片层115的栅极堆叠件并填充栅极堆叠件开口。作为示例而非限制，图8示出了完成图3中描述的方法300之后的所得NSFET 100。
通过示例而非限制，图9A和图9B是使用图3所示的方法300形成的n型NSFET 100n和p型NSFET 100p的等轴视图。如上所述，与p型NSFET 100p的p型功函堆叠件500p相比，n型NSFET 100n的p型功函堆叠件500n包括较少的p型功函层。因此，n型NSFET 100n的p型功函堆叠件500n看起来比p型NSFET 100p的p型功函堆叠件500p薄。
作为示例而非限制，图11示出了使用方法300形成的n型NSFETA、B和C以及p型NSFETD、E和F的截面图。如上所述，p型NSFETD、E和F具有比n型NSFETA、B和C更大数量的p功函层500x(其中，x是‘a’至‘e’)。在图11的实例中，n型NSFETA、B和C最多可具有3个p型功函层500a、500b和500c，而p型NSFETD、E和F最多可具有6个功函层(例如，500a至500e)。在一些实施例中，n型NSFET的阈值电压随着p型功函层数量的增加而增加。例如，n型NSFETA的阈值电压低于n型NSFETB和C，并且n型NSFETB的阈值电压低于n型NSFETC。相反地，p型NSFET的阈值电压随着p型功函层数量的增加而减小。例如，p型NSFETD的阈值电压大于p型NSFETE和F，并且p型NSFETE的阈值电压大于p型NSFETF。
根据一些实施例，方法300不限于全环栅纳米片FET，并且可以适用于其他晶体管，诸如finFET、平面晶体管或由于缩放要求而需要将n型功函层变得更薄的晶体管。
本文所述的实施例针对用于制造具有与诸如TiAl和TiAlC的基于铝的n型功函层相反的无铝n型功函层的晶体管的方法。根据一些实施例，无铝n型功函层的厚度可以在约0.5nm和约1.5nm之间，其厚度比基于铝的n型功函层至少薄约
Figure BDA0002442152720000131
因此，本文描述的无铝n型功函层可以减轻由于不良的栅极堆叠件间隙填充而引起的挑战，诸如存在于具有挑战性的栅极堆叠件几何形状的晶体管中的高栅极堆叠件电阻和可靠性问题。在一些实施例中，无铝n型功函层包括TiSix、TaSix、CoSix或NiSix。根据一些实施例，本文描述的无铝功函层与p型功函层原位生长(例如，没有真空破坏)。因此，可以防止或减轻不期望的氧结合至功函层中。
在一些实施例中，半导体结构包括位于衬底上的鳍结构和位于鳍结构上的垂直堆叠件。垂直堆叠件包括第一部分和第二部分，其中，每个第一和第二部分均具有交替的第一和第二纳米片层。垂直堆叠件还包括具有第二纳米片层的第三部分，并且在第一部分和第二部分之间没有设置第一纳米片层，其中，第二纳米片层从第一部分穿过第三部分延伸至垂直堆叠件的第二部分。半导体结构还包括设置在垂直结构的第三部分上的栅极结构。此外，栅极结构围绕第三部分中的第二纳米片层，并且包括形成在第三部分中的第二纳米片层上的介电堆叠件、位于介电堆叠件上的功函堆叠件、位于功函堆叠件上的无铝功函层，以及金属填充物，该金属填充物围绕第三部分中的第二纳米片层，并且位于垂直堆叠件的第一部分和第二部分之间。
在一些实施例中，半导体结构包括设置在间隔开的源极/漏极外延层之间的纳米片沟道部分，其中，纳米片沟道部分包括垂直堆叠件并间隔开的两个或更多个纳米片层。半导体结构还包括设置在围绕纳米片沟道部分的两个或更多个纳米片层的纳米片沟道部分上的栅极堆叠件，其中，该栅极堆叠件包括设置在纳米片沟道部分的两个或更多个纳米片层上的介电层、位于介电层上的一个或多个p型功函层、位于一个或多个p型功函层上的无铝n型功函层，以及位于金属纳米片沟道部分的两个或更多个纳米片层之间的金属。
在一些实施例中，方法包括：形成设置在间隔开的源极/漏极外延层之间的沟道部分，以及在沟道部分上形成栅极堆叠件，其中，形成栅极堆叠件包括在沟道部分上沉积高k介电层并在介电层上沉积p型功函层。在沉积p型功函层之后，在没有真空破坏的情况下，在p型功函层上形成无铝n型功函层，并且在无铝n型功函层上沉积金属。该方法还包括沉积围绕间隔开的源极/漏极外延层和栅极堆叠件的绝缘层。
在一些实施例中，半导体结构，包括：鳍结构，位于衬底上；两个间隔开的源极/漏极外延堆叠件，形成在所述鳍结构的顶面上；纳米片层，设置在所述两个间隔开的源极/漏极外延堆叠件之间，其中，所述纳米片层间隔开；以及栅极结构，围绕所述纳米片层，其中，所述栅极结构包括：介电堆叠件，形成为围绕所述纳米片层；功函堆叠件，形成为围绕所述介电堆叠件；无铝功函层，形成为围绕所述功函堆叠件；和金属层，形成为围绕所述无铝功函层。在上述半导体结构中，还包括：间隔件，介于所述栅极结构与所述两个间隔开的源极/漏极外延堆叠件中的每个之间，其中，所述间隔件围绕所述纳米片层的未由所述栅极结构围绕的部分；以及绝缘层，围绕所述栅极结构和所述两个隔开的源极/漏极外延堆叠件。在上述半导体结构中，所述功函堆叠件包括一个或多个p型功函层。在上述半导体结构中，所述无铝功函层包括金属硅化物。在上述半导体结构中，所述无铝功函层包括硅化钛、硅化钽、硅化钴或硅化镍。在上述半导体结构中，所述无铝功函层的厚度在约
Figure BDA0002442152720000151
和约
Figure BDA0002442152720000152
之间。在上述半导体结构中，所述纳米片层包括硅。在上述半导体结构中，所述纳米片层之间的间隔在约8nm和约12nm之间。
在一些实施例中，半导体结构包括：纳米片沟道部分，设置在间隔开的源极/漏极外延层之间，其中，所述纳米片沟道部分包括垂直堆叠并间隔开的两个或更多个纳米片层；以及栅极堆叠件，设置在所述纳米片沟道部分上并围绕所述纳米片沟道部分的两个或更多个纳米片层，其中，所述栅极堆叠件包括：介电层，设置在所述纳米片沟道部分的两个或更多个纳米片层上；一个或多个p型功函层，位于所述介电层上；无铝n型功函层，位于所述一个或多个p型功函层上；以及金属，位于所述纳米片沟道部分的两个或更多个纳米片层之间。在上述半导体结构中，所述无铝n型功函层包括金属硅化物。在上述半导体结构中，所述金属包括钛、钽、钴或镍。在上述半导体结构中，所述一个或多个p型功函层包括氮化钛。在上述半导体结构中，所述两个或更多个纳米片层之间的间隔在约8nm和约12nm之间。在上述半导体结构中，所述无铝n型功函层的厚度在约
Figure BDA0002442152720000153
和约
Figure BDA0002442152720000154
之间。
在一些实施例中，形成半导体结构的方法包括：形成设置在间隔开的源极/漏极外延层之间的沟道部分；在所述沟道部分上形成栅极堆叠件，其中，形成所述栅极堆叠件包括：在所述沟道部分上沉积高k介电层；在所述高k介电层上沉积p型功函层；在沉积所述p型功函层之后，在不发生真空破坏的情况下，在所述p型功函层上形成无铝n型功函层；和在无铝n型功函层上沉积金属；以及沉积围绕所述间隔开的源极/漏极外延层和所述栅极堆叠件的绝缘层。在上述方法中，形成所述无铝n型功函层包括：将p型功函层暴露于四氯化钛蒸气中约50s至约150s；以及在将所述p型功函层暴露于四氯化钛蒸气之后，将所述p型功函层暴露于硅烷气体约180s至约400s以形成硅化钛。在上述方法中，形成所述无铝n型功函层包括：将所述p型功函层暴露于氯化钽蒸气中约50s至约150s；以及在将所述p型功函层暴露于氯化钽蒸气之后，将所述p型功函层暴露于硅烷气体约180s至约400s以形成硅化钽。在上述方法中，形成所述无铝n型功函层包括沉积厚度在约
Figure BDA0002442152720000161
和约
Figure BDA0002442152720000162
之间的所述无铝n型功函层。在上述方法中，形成所述无铝n型功函层包括在约400℃和约450℃之间的温度下沉积所述无铝n型功函层。在上述方法中，形成所述无铝n型功函层包括沉积硅化钛、硅化钽、硅化钴或硅化镍。
应当理解，“具体实施方式”部分而非公开的“摘要”部分旨在用于解释权利要求。如发明人所预期的，公开的摘要部分可以阐述本公开的一个或多个但不是所有可能的实施例，并且因此，不旨在以任何方式限制从属权利要求。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
鳍结构，位于衬底上；
两个间隔开的源极/漏极外延堆叠件，形成在所述鳍结构的顶面上；
纳米片层，设置在所述两个间隔开的源极/漏极外延堆叠件之间，其中，所述纳米片层间隔开；以及
栅极结构，围绕所述纳米片层，其中，所述栅极结构包括：
介电堆叠件，形成为围绕所述纳米片层；
功函堆叠件，形成为围绕所述介电堆叠件；
无铝功函层，形成为围绕所述功函堆叠件；和
金属层，形成为围绕所述无铝功函层。
2.根据权利要求1所述的半导体结构，还包括：
间隔件，介于所述栅极结构与所述两个间隔开的源极/漏极外延堆叠件中的每个之间，其中，所述间隔件围绕所述纳米片层的未由所述栅极结构围绕的部分；以及
绝缘层，围绕所述栅极结构和所述两个隔开的源极/漏极外延堆叠件。
3.根据权利要求1所述的半导体结构，其中，所述功函堆叠件包括一个或多个p型功函层。
4.根据权利要求1所述的半导体结构，其中，所述无铝功函层包括金属硅化物。
5.根据权利要求1所述的半导体结构，其中，所述无铝功函层包括硅化钛、硅化钽、硅化钴或硅化镍。
6.根据权利要求1所述的半导体结构，其中，所述无铝功函层的厚度在约
Figure FDA0002442152710000011
和约
Figure FDA0002442152710000012
之间。
7.根据权利要求1所述的半导体结构，其中，所述纳米片层包括硅。
8.根据权利要求1所述的半导体结构，其中，所述纳米片层之间的间隔在约8nm和约12nm之间。
9.一种半导体结构，包括：
纳米片沟道部分，设置在间隔开的源极/漏极外延层之间，其中，所述纳米片沟道部分包括垂直堆叠并间隔开的两个或更多个纳米片层；以及
栅极堆叠件，设置在所述纳米片沟道部分上并围绕所述纳米片沟道部分的两个或更多个纳米片层，其中，所述栅极堆叠件包括：
介电层，设置在所述纳米片沟道部分的两个或更多个纳米片层上；
一个或多个p型功函层，位于所述介电层上；
无铝n型功函层，位于所述一个或多个p型功函层上；以及
金属，位于所述纳米片沟道部分的两个或更多个纳米片层之间。
10.一种形成半导体结构的方法，包括：
形成设置在间隔开的源极/漏极外延层之间的沟道部分；
在所述沟道部分上形成栅极堆叠件，其中，形成所述栅极堆叠件包括：
在所述沟道部分上沉积高k介电层；
在所述高k介电层上沉积p型功函层；
在沉积所述p型功函层之后，在不发生真空破坏的情况下，在所述p型功函层上形成无铝n型功函层；和
在无铝n型功函层上沉积金属；以及
沉积围绕所述间隔开的源极/漏极外延层和所述栅极堆叠件的绝缘层。
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