TWI741176B - 基底條與具有其之電子部件封裝 - Google Patents

基底條與具有其之電子部件封裝 Download PDF

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Publication number
TWI741176B
TWI741176B TW107114071A TW107114071A TWI741176B TW I741176 B TWI741176 B TW I741176B TW 107114071 A TW107114071 A TW 107114071A TW 107114071 A TW107114071 A TW 107114071A TW I741176 B TWI741176 B TW I741176B
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TW
Taiwan
Prior art keywords
solder resist
resist layer
layer
electronic component
laminated body
Prior art date
Application number
TW107114071A
Other languages
English (en)
Chinese (zh)
Other versions
TW201919178A (zh
Inventor
吳隆
金相勳
高永國
Original Assignee
南韓商三星電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電機股份有限公司 filed Critical 南韓商三星電機股份有限公司
Publication of TW201919178A publication Critical patent/TW201919178A/zh
Application granted granted Critical
Publication of TWI741176B publication Critical patent/TWI741176B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
TW107114071A 2017-11-08 2018-04-25 基底條與具有其之電子部件封裝 TWI741176B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
??10-2017-0148305 2017-11-08
KR10-2017-0148305 2017-11-08
KR1020170148305A KR102456322B1 (ko) 2017-11-08 2017-11-08 기판 스트립 및 이를 포함하는 전자소자 패키지

Publications (2)

Publication Number Publication Date
TW201919178A TW201919178A (zh) 2019-05-16
TWI741176B true TWI741176B (zh) 2021-10-01

Family

ID=66672193

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107114071A TWI741176B (zh) 2017-11-08 2018-04-25 基底條與具有其之電子部件封裝

Country Status (3)

Country Link
JP (1) JP7087241B2 (ko)
KR (1) KR102456322B1 (ko)
TW (1) TWI741176B (ko)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052188A1 (en) * 2008-08-26 2010-03-04 Mohammad Khan Semiconductor Chip with Solder Joint Protection Ring
US20110215468A1 (en) * 2003-11-10 2011-09-08 Stats Chippac, Ltd. Bump-on-Lead Flip Chip Interconnection
US20150061125A1 (en) * 2007-12-26 2015-03-05 Skyworks Solutions, Inc. Integrated circuit package including in-situ formed cavity
US20160035591A1 (en) * 2012-04-18 2016-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for bump-on-trace Chip Packaging
US20170301626A1 (en) * 2014-08-26 2017-10-19 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4319944C2 (de) 1993-06-03 1998-07-23 Schulz Harder Juergen Mehrfach-Substrat sowie Verfahren zu seiner Herstellung
JP3407172B2 (ja) * 1995-12-26 2003-05-19 株式会社トッパンエヌイーシー・サーキットソリューションズ プリント配線板の製造方法
JP2003218542A (ja) 2002-01-25 2003-07-31 Dainippon Printing Co Ltd 多層配線基板多面付け体およびその製造方法
JP2004241425A (ja) 2003-02-03 2004-08-26 Kyocera Corp 多数個取り配線基板
JP2007173586A (ja) 2005-12-22 2007-07-05 Kyocera Corp 複数個取り配線基板の検査方法および複数個取り配線基板
JP5280032B2 (ja) * 2007-09-27 2013-09-04 新光電気工業株式会社 配線基板
JP4993739B2 (ja) 2007-12-06 2012-08-08 新光電気工業株式会社 配線基板、その製造方法及び電子部品装置
JP5079059B2 (ja) * 2010-08-02 2012-11-21 日本特殊陶業株式会社 多層配線基板
JP5547594B2 (ja) * 2010-09-28 2014-07-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP5190553B1 (ja) 2012-03-06 2013-04-24 フリージア・マクロス株式会社 キャリア付き金属箔
KR101548816B1 (ko) * 2013-11-11 2015-08-31 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20150062556A (ko) 2013-11-29 2015-06-08 삼성전기주식회사 휨방지 부재가 구비된 스트립 레벨 기판 및 이의 제조 방법
KR20150145451A (ko) 2014-06-19 2015-12-30 삼성전기주식회사 기판 스트립, 기판 판넬 및 기판 스트립의 제조방법
KR102222604B1 (ko) * 2014-08-04 2021-03-05 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20160068511A (ko) * 2014-12-05 2016-06-15 삼성전기주식회사 인쇄회로기판 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110215468A1 (en) * 2003-11-10 2011-09-08 Stats Chippac, Ltd. Bump-on-Lead Flip Chip Interconnection
US20150061125A1 (en) * 2007-12-26 2015-03-05 Skyworks Solutions, Inc. Integrated circuit package including in-situ formed cavity
US20100052188A1 (en) * 2008-08-26 2010-03-04 Mohammad Khan Semiconductor Chip with Solder Joint Protection Ring
US20160035591A1 (en) * 2012-04-18 2016-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for bump-on-trace Chip Packaging
US20170301626A1 (en) * 2014-08-26 2017-10-19 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same

Also Published As

Publication number Publication date
KR20190052540A (ko) 2019-05-16
JP7087241B2 (ja) 2022-06-21
KR102456322B1 (ko) 2022-10-19
TW201919178A (zh) 2019-05-16
JP2019087724A (ja) 2019-06-06

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