TWI741176B - Substrate strip and electronic component package having the same - Google Patents

Abstract

The present invention relates to a substrate strip comprising: a laminate composed of an insulating layer and a circuit layer; a first solder resist layer formed on the laminate; a reinforcement member formed on the first solder resist layer; and a second solder resist layer formed on the first solder resist layer to cover the reinforcement member, wherein the laminate is divided into a unit area and a dummy area, and wherein the reinforcement member and the second solder resist layer are formed on the dummy area.

Description

Base strip and electronic component packaging with the same

The following description is about a base strip and electronic component packaging with it.

Due to the development of semiconductor packaging technology, the packaging substrate has become very dense and miniaturized. Therefore, an ultra-fine printed circuit board is required. In order to make such an ultra-fine printed circuit board, it is very important to ensure the rigidity of the printed circuit board. When the rigidity is insufficient, the substrate will be severely warped and it is difficult to perform the normal process in the packaging process.

Japanese Patent Application No. 2009-141121 describes an example of a wiring substrate.

The object of the present invention is to provide a substrate strip that can reduce bending and an electronic component package with the substrate strip.

According to one aspect of the present invention, there is provided a base strip, the base strip comprising: a laminated body composed of an insulating layer and a circuit layer; a first solder resist layer formed on the On the laminated body; a reinforcing member formed on the first solder resist layer; and a second solder resist layer formed on the first solder resist layer to cover the reinforcing member, wherein the laminated body is divided into A unit area and a dummy area, and wherein the reinforcing member and the second solder resist layer are formed on the dummy area.

According to another aspect of the present invention, there is provided an electronic component package. The electronic component package includes: a base strip divided into a unit area and a dummy area; and an electronic component mounted on the unit area, wherein the base strip It includes: a laminated body composed of an insulating layer and a circuit layer; a first solder resist layer formed on the laminated body; a reinforcing member formed on the first solder resist layer; and a second solder resist layer formed on the The first solder resist layer covers the reinforcement member, wherein the reinforcement member and the second solder resist layer are formed on the dummy area.

100: layered body

110: Insulation layer

120, 121, 122: circuit layer

121': terminal pad

130: Through hole

200: The first solder mask

200a: Upper solder mask

200b: Lower solder mask

210: Cavity

220: open area

300, 310, 320: strengthening member

330: Pattern of fiducial mark

400: The second solder mask

410: open

420: Molded gate

430: Molded components

500: electronic components

510: Joining member

520: underfill glue

B: boundary

D: Dummy area

M: pattern mask

R: Anti-plating layer

S1: Metal foil

S2: Seed layer

U: unit area

U': unit

Fig. 1 is a cross-sectional view showing a base strip according to an embodiment of the present invention.

Fig. 2 is a plan view showing a base strip according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an electronic component package according to an embodiment of the present invention.

Fig. 4 shows a molding process of an electronic component package according to an embodiment of the present invention.

5 to 12 are cross-sectional views showing the manufacturing process used in the method of manufacturing the base strip according to the embodiment of the present invention.

In all figures and throughout the detailed description, the same reference numbers refer to the same elements. The drawings may not necessarily be drawn to scale, and for clarity, description, and convenience, the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated.

The following detailed description is provided to help readers gain a comprehensive understanding of the methods, equipment and/or systems described in this article. However, various changes, modifications and equivalent forms of the methods, devices and/or systems described herein will be obvious to those with ordinary knowledge in the art. The order of operations described herein is only an example, and is not limited to the order described herein, but except for operations that must occur in a certain order, it can be performed as will be obvious to those with ordinary knowledge in the art. Change. In addition, in order to increase clarity and conciseness, the description of the functions and structures known to those with ordinary knowledge in this technology may be omitted.

The features described herein can be implemented in many different forms and should not be regarded as limited to the examples described herein. To be more precise, the examples described herein are provided so that the content of this disclosure will be thorough and complete, and will convey the full scope of the disclosure to those skilled in the art.

Unless otherwise defined, all terms used herein including technical terms and scientific terms have the same meaning as those commonly understood by those with ordinary knowledge in the technology to which this disclosure belongs. Any term defined in a commonly used dictionary should be understood as having the same meaning in the context of related technologies, and unless clearly defined otherwise, it should not be interpreted as having an ideal or overly formal meaning.

Regardless of the figure number, the same or corresponding parts will be given the same reference numbers, and any redundant description of the same or corresponding parts will not be repeated. Throughout the description of this disclosure, when it is determined that a certain related traditional technology is described to avoid the main points of this disclosure, related detailed descriptions will be omitted. Examples can be used when explaining various components Terms such as "first" and "second", but the above components should not be limited to the above terms. The above terms are only used to distinguish each component. In the drawings, some components may be exaggerated, omitted or briefly described, and the size of the components does not necessarily reflect the actual size of the components.

Hereinafter, certain embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing a base strip according to an embodiment of the present invention, and FIG. 2 is a plan view showing a base strip according to an embodiment of the present invention.

1 and 2, the base strip according to the embodiment of the present invention includes a laminated body 100, a first solder resist layer 200, a reinforcing member 300 and a second solder resist layer 400.

The laminated body 100 is composed of an insulating layer 110 and a circuit layer 120, and has one surface and the other surface. Here, except for the side surface, the one surface and the other surface of the laminated body 100 are opposed to each other. In the present invention, one surface of the laminated body 100 is the surface on which the electronic component 500 is mounted, and the other surface is the surface bonded to the main board. In FIG. 1, the upper surface of the laminated body 100 is the one surface, and the lower surface is the other surface.

The insulating layer 110 of the laminated body 100 is formed of an insulating material (for example, resin) and has a thin plate shape. The resin of the insulating layer 110 may be various materials, such as thermosetting resin and thermoplastic resin, and more specifically epoxy resin, polyimide, and the like. Examples of epoxy resins include: naphthalene epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac epoxy resin, cresol novolac epoxy resin, rubber modified High-quality epoxy resin, cycloaliphatic epoxy resin, silicon epoxy resin, nitrogen epoxy resin, phosphorous epoxy resin, etc. However, it is not limited to this.

The insulating layer 110 may be a prepreg (PPG) including a fiber reinforcement member 300 (for example, glass cloth) in a resin. The insulating layer 110 may be a constituent film filled with an inorganic filler (for example, silicon dioxide) in a resin. As such a constitution film, an Ajinomoto build-up film (ABF) or the like can be used.

The inorganic filler included in the constituent film may be silicon dioxide (SiO ₂ ), barium sulfate (BaSO ₄ ), aluminum oxide (Al ₂ O ₃ ), or a combination of two or more of the foregoing. Inorganic fillers may further include: calcium carbonate, magnesium carbonate, fly ash, natural silica, synthetic silica, kaolin, clay, calcium oxide, magnesium oxide, titanium oxide, zinc oxide, calcium hydroxide, aluminum hydroxide, hydrogen Magnesium oxide, talc, mica, hydrotalcite, aluminum silicate, magnesium silicate, calcium silicate, braised talc, wollastonite, potassium titanate, magnesium sulfate, calcium sulfate or magnesium phosphate. However, it is not limited to this.

The laminated body 100 can be formed by using a plurality of insulating layers 110 laminated on top of each other. Although three insulating layers 110 are shown in FIG. 1, the number of insulating layers 110 is not limited.

The circuit layer 120 of the laminated body 100 is patterned to transmit electrical signals, and is formed as a conductor having a predetermined width and thickness and shaped according to the circuit design. Considering the nature of power conduction, the circuit layer 120 may be made of metal, such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), Platinum (Pt) or its alloys.

The circuit layer 120 is formed in the insulating layer 110. If a plurality of insulating layers 110 are formed, the circuit layer 120 is formed in each insulating layer 110. The circuit layer 120 can be formed on one or both surfaces of the insulating layer 110 and can be embedded in one of the insulating layers 110 Or in both surfaces. Figure 1 shows a three-layer insulating layer 110. In this case, the circuit layer 120 may be four layers.

The circuit layer 121 formed on one surface of the laminated body 100 may be formed to be embedded in the insulating layer 110. In addition, the circuit layer 121 formed on one surface of the laminated body 100 may include a terminal pad 121'. The terminal pad 121' is an area where the electronic component 500 is to be mounted. On the other hand, the circuit layer 122 formed on the other surface of the laminated body 100 may protrude beyond the other surface of the laminated body 100.

The circuit layer 120 may include a metal foil S1 and a seed layer S2. Except for the metal foil S1 and the seed layer S2, the remaining circuit layer 120 can be formed by an electroplating method using the seed layer as the lead-in wire. In this case, the circuit layer 120 may be formed in the order of the metal foil S1, the seed layer S2, and the electroplating layer. The metal foil S1 and the seed layer S2 may be the result of the circuit layer 120 formed by a modified semi-additive process (MSAP). Therefore, in the present invention, the metal foil S1 and the seed layer S2 of the circuit layer 120 do not necessarily need to be formed all the time. The existence of the metal foil S1 and the seed layer S2 can be determined according to the manufacturing method of the circuit layer 120. For example, if the circuit layer 120 is formed by subtractive (for example, tenting) or semi-additive process (SAP) technology, the circuit layer 120 may only have the seed layer S2 without metal. Foil S1.

The laminated body 100 may further include a through hole 130, and the through hole 130 is electrically connected to the vertically spaced circuit layer 120. That is, the through holes 130 are formed in different insulating layers 110 or connect the circuit layers 120 formed on the two surfaces of the insulating layer 110. The through hole 130 can also be made of metal, for example, the metal is the same as the circuit layer 120. The same metal. The through hole 130 may further include a seed layer S2.

The laminated body 100 is divided into a unit area U and a dummy area D. The unit area U includes a plurality of units U′ and is a part that serves as an actual substrate when the substrate strip is cut after packaging. A boundary B is provided between the plurality of units U′, and the base strip is cut along the boundary B. The dummy area D is the part other than the unit area that will be removed when the base strip is cut after packaging.

The circuit layer 120 is formed in each unit U'of the unit area U and the terminal pad 121' for mounting the electronic component 500 is also formed on each unit U'. Therefore, the electronic component 500 is mounted on each unit U′ of the unit area U.

As shown in FIG. 2, the dummy area D is located outside the unit area U. The unit area U occupies most of the base bar, and the dummy area D is formed along the edge of the unit area U to be located on the outermost edge of the base bar.

The first solder resist layer 200 is laminated on the laminated body 100 to cover the circuit layer 120, and has a photosensitive resin to prevent unnecessary short circuits. The first solder resist layer 200 may be formed on both surfaces of the laminated body 100. For convenience, the first solder resist layer 200 formed on one surface of the laminated body 100 is referred to as the upper solder resist layer 200a and the first solder resist layer 200 formed on the other surface of the laminated body 100 is referred to as The lower solder resist layer 200b will be further described.

The upper solder resist layer 200a is in contact with one surface of the laminated body 100 and the exposed surface of the embedded circuit layer 121 (when the circuit layer 121 formed on one surface of the laminated body 100 is embedded in the insulating layer 110). The upper solder resist layer 200a may cover the terminal pad 121'. Here, the upper solder resist layer 200a is provided with a cavity 210 to expose The one surface of the laminated body 100 and the terminal pad 121 ′ are exposed through the cavity 210. Since the terminal pad 121 ′ is formed in the unit area U, the cavity 210 is formed on the unit area U. A surface treatment layer, such as gold (Au) or nickel (Ni), may be formed on the surface of the terminal pad 121' exposed through the cavity 210.

When the circuit layer 122 formed on the other surface of the laminated body 100 protrudes beyond the other surface of the laminated body 100, the lower solder resist layer 200b is formed in contact with the other surface of the laminated body 100 to cover the protruding circuit layer 122 . The lower solder resist layer 200b may include an opening area 220 for exposing the lower surface of the protruding circuit layer 122. When the base strip is cut according to the unit U′ after packaging and mounted on the main board, a bonding member, such as solder, may be formed on the lower surface of the circuit layer 122 exposed through the opening area 220.

When the circuit layer 121 formed on one surface of the laminated body 100 is embedded in the insulating layer 110 and the circuit layer 122 formed on the other surface of the laminated body 100 protrudes beyond the other surface of the laminated body 100, the upper solder resist layer The thickness of 200a may be smaller than the thickness of the lower solder resist layer 200b.

The first solder resist layer 200 is formed on the unit area U and the dummy area D of the multilayer body 100. Since the circuit layer 120 is formed on the unit area U, the first solder resist layer 200 located on the unit area U protects the circuit layer 120 and the first solder resist layer 200 located on the dummy area D imparts rigidity to the base strip. On the other hand, the first solder resist layer 200 may not be formed on the boundary B between the plurality of cells U′ located in the cell region U.

The reinforcing member 300 is formed on the first solder resist layer 200 on the dummy area D and imparts rigidity to the base strip. The reinforcing member 300 is formed on the dummy area D but not in shape Completed on the unit area U. Therefore, the reinforcing member 300 is removed when cutting the base strip after packaging, and provides rigidity to the base strip before the packaging process is completed. Since the reinforcement member 300 is formed on the first solder resist layer 200 on the dummy region D, the reinforcement member 300 is formed as the circuit layer 120 higher than the unit region U of the laminated body 100.

The reinforcing member 300 may be formed only on the upper solder resist layer 200a of the first solder resist layer 200 and not on the lower solder resist layer 200b. However, it is not excluded that the reinforcing member 300 is formed on the upper solder resist layer 200a and the lower solder resist layer 200b.

The reinforcement member 300 may be formed of metal. For example, the reinforcing member 300 may be made of metal having greater rigidity or modulus than the circuit layer 120. Rigidity refers to the strain that occurs when an external force is applied. Rigidity can be simply regarded as the strain that occurs when an axial force (vertical stress) is applied. This stiffness depends on the modulus of elasticity or Young's modulus. It can be understood that the greater the modulus of elasticity or Young's modulus, the greater the rigidity.

In addition, the reinforcing member 300 may be formed of a metal such as the same metal as the circuit layer 120 or the like. The reinforcement member 300 may be formed by the same method as the method of forming the circuit layer 120. The reinforcing member 300 may include a metal foil S1 and a seed layer S2. According to the method of forming the reinforcing member 300 as described above, the reinforcing member 300 may also include only the seed layer S2. The reinforcing member 300 may be formed using the following method instead of a circuit forming method: after the reinforcing member 300 is patterned, the patterned reinforcing member 300 is adhered to the first solder resist layer 200. The method of forming the reinforcing member is not limited to this.

1 and 2, the reinforcement member 300 may be formed in various shapes. The reinforcement member 300 may be formed along the dummy area D and, more specifically, may extend along the dummy area D (see 310). A plurality of reinforcing members 300 may be arranged along the dummy area D Spaced apart or touching each other (see 320). The width of the reinforcement member 300 is equal to or less than the width of the dummy area D, and the thickness of the reinforcement member 300 may be greater than the thickness of the circuit layer 120. However, it is not limited to this.

In FIG. 2, the reinforcement member 300 is shown as being exposed above the surface. However, the reinforcing member 300 is covered by the second solder resist layer 400 and therefore is not exposed to the outside, so it is indicated by a dotted line.

The first solder resist layer 200 may be provided with a pattern 330 of fiducial marks. The pattern 330 of the fiducial mark is made of metal (for example, the same metal as the reinforcing member 300) and can be made together when the reinforcing member 300 is formed. In this case, the reinforcement member 300 is positioned on the upper surface of the first solder resist layer 200. The pattern 330 of the fiducial mark may be formed in a hole shape and not metal. The pattern 330 of the fiducial mark may be a working hole or a manufacturing hole. In this case, the pattern 330 of the fiducial mark penetrates the first solder resist layer 200. The pattern 330 of this fiducial mark can be used to identify the position of the base strip in the post-processing.

The second solder resist layer 400 may be laminated on the first solder resist layer 200 to cover the reinforcing member 300. The thickness of the second solder resist layer 400 is equal to or greater than the thickness of the reinforcement member 300, and the reinforcement member 300 is surrounded by the first solder resist layer 200 and the second solder resist layer 400. The reinforcement member 300 is not exposed to the outside. That is, the reinforcing member 300 is in contact with the upper surface of the first solder resist layer 200, and the surface of the reinforcing member 300 that is not in contact with the first solder resist layer 200 is in contact with the second solder resist layer 400.

The second solder resist layer 400 may be formed of the same material as the first solder resist layer 200. The second solder resist layer 400 may also have a higher rigidity than the first solder resist layer 200 or Modular material is formed.

The second solder resist layer 400 is not formed on the unit area U but only on the dummy area D, so that the area of the second solder resist layer 400 covering the first solder resist layer 200 can be the same as or smaller than the area of the dummy area D . In addition, the second solder resist layer 400 is removed when cutting the base strip after packaging, and provides rigidity to the base strip before the packaging process is completed.

The second solder resist layer 400 is provided with a mold gate 420 that opens laterally. The molded gate 420 is an entrance for introducing the molded component 430 in the substrate strip packaging process. The second solder resist layer 400 is formed in a region other than the region to be the mold gate 420.

The position and number of the molded gate 420 are not limited. In FIG. 2, a plurality of molded gates 420 are exemplarily shown on one side surface of the base strip. However, the present invention is not limited to this position and number.

The second solder resist layer 400 is provided with an opening 410 opening upward and thus the pattern 330 of the fiducial mark is exposed through the opening 410. When the pattern 330 of the fiducial mark is formed in a hole shape, the opening 410 may be formed to correspond to the hole. However, when the pattern 330 of the fiducial mark does not need to be exposed, for example, when the pattern 330 of the fiducial mark can be identified through the second solder resist layer 400 by X-rays or the like, the second solder resist layer 400 may cover the pattern of the fiducial mark 330, and the above-mentioned opening 410 may be unnecessary.

FIG. 3 is a cross-sectional view showing a package of an electronic component 500 according to an embodiment of the present invention. FIG. 4 shows a molding process of a package of an electronic component 500 according to an embodiment of the present invention.

3, the package of the electronic component 500 according to the embodiment of the present invention includes: a base strip divided into a unit area U and a dummy area D; and an electronic component 500 mounted on the unit area U. As described with reference to FIGS. 1 and 2, the base strip includes a laminated body 100, a first solder resist layer 200, a reinforcement member 300, and a second solder resist layer 400.

Regarding the base strip, the laminated body 100, the first solder resist layer 200, the reinforcement member 300, and the second solder resist layer 400 are the same as those explained above, and therefore the description thereof will be omitted.

The electronic component 500 is mounted on the base strip and specifically mounted in the cavity 210 of the first solder resist layer 200. More specifically, the electronic component 500 is mounted on the terminal pad 121 ′ on one surface of the laminated body 100 exposed through the cavity 210 by the bonding member 510. The joining member 510 may be solder. The electronic component 500 is spaced apart from one surface of the laminated body 100 by the bonding member 510, and an underfill 520 may be sandwiched between the electronic component 500 and the one surface of the laminated body 100. However, in addition to the flip chip method using the bonding member 510, the electronic component 500 can also be mounted on the base strip by wire bonding.

The electronic component 500 mounted on the substrate bar includes various components, such as active components, passive components, and integrated circuits (IC), and may be, for example, semiconductor chips. One electronic component 500 may be installed on each unit U′ of the unit area U, or a plurality of electronic components 500 may be installed on each unit U′.

The package of the electronic component 500 according to the embodiment of the present invention may further include a molding member 430 formed on the first solder resist layer 200 to cover the mounted electronic component 500. The molding member 430 may be introduced into the cavity 210 to cover the electronic part 500.

Referring to FIG. 4, the molding member 430 may flow onto the base strip through the molding gate 420. The molding member 430 may be formed on the first solder resist layer 200 and the electronic component 500 by using the second solder resist layer 400 as a dam. As a result, as shown in FIG. 3, the molding member 430 may be formed to a height lower than that of the second solder resist layer 400. However, it is not limited to this.

The package of the electronic component 500 according to the embodiment of the present invention may be cut according to the unit U′ after the molding member 430 is formed.

5 to 12 are cross-sectional views showing the manufacturing process used in the method of manufacturing the base strip according to the embodiment of the present invention.

Referring to FIG. 5, a laminated body 100 is formed. The laminated body 100 may be formed with a plurality of insulating layers 110 stacked in sequence. The laminated body 100 can be formed in a coreless form using a carrier. In this case, the circuit layer 121 formed on one surface of the laminated body 100 may be embedded in the insulating layer 110. When forming the laminate 100, the circuit layer 120 can be formed by various methods, such as a modified semi-additive method (MSAP), a semi-additive method (SAP), and tenting.

Referring to FIG. 6, a first solder resist layer 200 is formed on the laminated body 100. The metal foil S1 is attached to one surface of the first solder resist layer 200 and the other surface of the first solder resist layer 200 is in contact with the laminated body 100 so that the metal foil S1 is located on the outside.

Referring to FIG. 7, a pattern mask M is formed on the first solder resist layer 200 to pattern the first solder resist layer 200. Here, the pattern mask M may be a dry film. When the metal foil S1 is attached to one surface of the first solder resist layer 200, the pattern mask M is positioned on the metal foil S1.

Referring to FIG. 8, the first solder resist layer 200 is patterned to form a cavity 210 in the upper solder resist layer 200a and an opening area 220 in the lower solder resist layer 200b. After patterning the first solder resist layer 200, the pattern mask M is peeled off.

Through the exposure and development process, the first solder resist layer 200 can include a cavity 210 and an open area 220. For example, when the first solder resist layer 200 is of a negative type, the pattern mask M covers the cavity 210 and the opening area 220, and then the first solder resist layer 200 is exposed, and the unexposed part is removed through a development process. On the other hand, when the first solder resist layer 200 is a positive type, the pattern mask M opens the cavity 210 and the opening area 220, and then exposes the first solder resist layer 200, and the exposed part is removed through a development process . In the case where the metal foil S1 is attached to one surface of the first solder resist layer 200, the exposure and development process may be performed after the metal foil S1 corresponding to the cavity 210 and the opening area 220 is removed.

At the same time, the cavity 210 and the opening area 220 of the first solder resist layer 200 can be formed by laser processing, blast processing, or the like.

9 and 10, a seed layer S2 is formed on the first solder resist layer 200, and a plating resist R is laminated on the seed layer S2. The plating resist layer R is opened to the region where the reinforcing member 300 is to be formed, and the reinforcing member 300 is formed by electroplating. The seed layer S2 can be formed by electroless plating. The seed layer S2 may be formed on the bottom surface and the inner wall of the cavity 210 of the first solder resist layer 200. When the metal foil S1 is attached to the first solder resist layer 200, the seed layer S2 is formed on the metal foil S1.

11, the plating resist layer R is peeled off, and the seed layer S2 except for the region of the reinforcing member 300 is also removed. When the metal foil S1 is attached to the first solder resist layer 200, The metal foil S1 and the seed layer S2 except for the area of the reinforcing member 300 are removed.

Referring to FIG. 12, a second solder resist layer 400 is formed. The second solder resist layer 400 is formed on the first solder resist layer 200 to surround the reinforcing member 300. The second solder resist layer 400 is formed by applying a solder resist on the entire surface of the base strip (both the unit area U and the dummy area D), removing the solder resist located on the unit area U, and leaving Solder resist on dummy area D. The removal of solder resist can be achieved by mechanical processing (such as exposure/development or sandblasting). In this case, when the first solder resist layer 200 and the second solder resist layer 400 are both photosensitive, the first solder resist layer 200 and the second solder resist layer 400 may be formed of different materials, or may have different The characteristic of reacting with light (for example, different wavelengths) makes the first solder resist layer 200 unaffected when the second solder resist layer 400 is formed by exposure/development.

Although the present disclosure includes specific examples, it will be obvious to those with ordinary knowledge in the art that, without departing from the spirit and scope of the scope of the patent application and its equivalent scope, various examples can be made. Changes in form and details. The examples described herein should be considered as illustrative only and not restrictive. The description of the features or aspects in each example should be regarded as applicable to similar features or aspects in other examples. If the described technologies are executed in a different order and/or if the components in the system, architecture, device or circuit are combined in different ways and/or replaced or supplemented by other components or their equivalent forms, then A suitable result can be achieved. Therefore, the scope of this disclosure is not defined by the detailed description, but by the scope of the patent application and its equivalent scope, and all variants within the scope of the patent application and its equivalent scope shall be deemed to be included in this disclosure. Revealing.

100‧‧‧Layered body

110‧‧‧Insulation layer

120、121、122‧‧‧Circuit layer

121'‧‧‧Terminal pad

130‧‧‧Through hole

200‧‧‧First solder mask

200a‧‧‧Upper solder mask

200b‧‧‧Lower solder mask

210‧‧‧cavity

220‧‧‧Opening area

300‧‧‧Strengthening member

400‧‧‧Second solder mask

B‧‧‧Border

D‧‧‧Dummy area

S1‧‧‧Metal foil

S2‧‧‧Seed layer

U‧‧‧unit area

Unit U'‧‧‧

Claims (21)

A base strip comprising: a laminated body composed of an insulating layer and a circuit layer; a first solder resist layer formed on the laminated body; a reinforcing member formed on the first solder resist layer; and a second solder resist layer Layer formed on the first solder resist layer to cover the reinforcement member, wherein the laminate is divided into a unit area and a dummy area, and wherein the reinforcement member and the second solder resist layer are formed on the On the dummy area. The base strip according to claim 1, wherein the first solder resist layer is formed on the unit area and the dummy area, and the reinforcing member and the second solder resist layer are not formed on The unit area. The base strip as described in item 2 of the scope of patent application, wherein a cavity is formed in the unit region of the first solder resist layer to expose one surface of the laminate. The base strip as described in claim 1, wherein the first solder resist layer is formed on both surfaces of the laminated body, and the reinforcing member is formed on one surface of the laminated body On the first solder resist layer, but not on the first solder resist layer formed on the other surface of the laminate. The base strip according to the first item of the scope of patent application, wherein the reinforcing member is surrounded by the first solder resist layer and the second solder resist layer. The base strip according to item 1 of the scope of patent application, wherein the reinforcing member is made of metal, and the metal includes the same metal as the circuit layer. The base strip as described in claim 1, wherein a plurality of reinforcing members are formed, and the plurality of reinforcing members are arranged to be spaced apart from each other or in contact with each other along the dummy area. The base strip according to the first item of the scope of patent application, wherein the second solder resist layer is provided with a mold gate opening to the side surface of the second solder resist layer. The base strip as described in item 1 of the scope of patent application, wherein a pattern of a fiducial mark is formed on the first solder resist layer, and an opening is formed on the second solder resist layer to expose the fiducial mark The upper surface of the pattern. The base strip as described in item 1 of the scope of patent application, wherein the dummy area is formed along the edge of the unit area. An electronic component package, comprising: a base strip divided into a unit area and a dummy area; and electronic components mounted on the unit area, wherein the base strip includes: a laminated body composed of an insulating layer and a circuit layer; first A solder resist layer formed on the laminated body; a reinforcement member formed on the first solder resist layer; and a second solder resist layer formed on the first solder resist layer to cover the reinforcement member, The reinforcing member and the second solder resist layer are formed on the dummy area. The electronic component package according to claim 11, wherein the first solder resist layer is formed on the unit area and the dummy area, and the reinforcing member and the second solder resist layer are not formed On the unit area. The electronic component package according to the 12th patent application, wherein a cavity is formed in the unit area of the first solder resist layer to expose one surface of the laminated body. The electronic component package described in claim 11, wherein the first solder resist layer is formed on both surfaces of the laminated body, and the reinforcing member is formed on one surface of the laminated body On the first solder resist layer, but not on the first solder resist layer formed on the other surface of the laminate. The electronic component package according to claim 11, wherein the reinforcing member is surrounded by the first solder resist layer and the second solder resist layer. The electronic component package according to the 11th patent application, wherein the reinforcing member is made of metal, and the metal includes the same metal as the circuit layer. The electronic component package as described in claim 11, wherein a plurality of reinforcing members are formed, and the plurality of reinforcing members are arranged to be spaced apart from each other or in contact with each other along the dummy area. The electronic component package according to the 11th patent application, wherein the second solder resist layer is provided with a mold gate opening to the side surface of the second solder resist layer. The electronic component package as described in claim 11, wherein a pattern of a fiducial mark is formed on the first solder resist layer, and an opening is formed on the second solder resist layer to expose the fiducial mark The upper surface of the pattern. The electronic component package as described in claim 11, wherein the dummy area is formed along the edge of the unit area. The electronic component package described in item 11 of the scope of the patent application further includes: a molded member located on the first solder resist layer to cover the electronic component.

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