JP2023139109A - Printed circuit board and electronic element package containing them - Google Patents

Abstract

To provide a printed circuit board in which a package substrate and a binding force are improved, and provide an electronic element package containing them.SOLUTION: A printed circuit board contains: a lamination body 100 constructed by an insulation layer 110 and a circuit layer 121; a first solder resist layer 200 that is laminated onto one layer of the lamination body 100; a bump 140 that is formed on one surface of the lamination body via the first solder resist layer 200, and is electrically connected to the circuit layer 121; and a second solder resist layer 310 that is laminated onto the first solder resist layer 200, and provides an open part 320 exposing one surface of the bump 140. Also, the printed circuit board includes a third solder resist layer 400 covering a circuit layer 122 formed on the other surface of the lamination body 100. In the case where the circuit layer 122 formed on the other surface of the lamination body 100 is projected from the other surface of the lamination body 100, the third solder resist layer 400 is laminated so as to be higher than the projected circuit layer 122.SELECTED DRAWING: Figure 1

Description

The present invention relates to a printed circuit board and an electronic component package including the printed circuit board.

With the development of semiconductor packaging technology, package substrates have become ultra-high density and miniaturized, which has reduced the pitch and height of solder balls on POP (Package On Package) substrates. Interposer substrates may also be used to implement POP substrates using solder balls with small pitch and height.

Japanese Patent Application Publication No. 2010-029867

SUMMARY OF THE INVENTION An object of the present invention is to provide a printed circuit board with improved bonding strength with a package substrate, and an electronic device package including the same.

According to one aspect of the present invention, a laminate including an insulating layer and a circuit layer, a first solder resist layer laminated on one surface of the laminate, and a bump formed on one surface of the laminate and electrically connected to the circuit layer; a second solder resist layer laminated on the first solder resist layer and provided with an opening that exposes one surface of the bump; A printed circuit board is provided that includes a printed circuit board.

According to another aspect of the present invention, the invention includes a printed circuit board on which electronic elements are mounted, and a package board bonded to the printed circuit board, wherein the printed circuit board includes an insulating layer and a circuit layer. a first solder resist layer laminated on one side of the laminated body; and a first solder resist layer formed on one side of the laminated body through the first solder resist layer and electrically connected to the circuit layer. and a second solder resist layer that is laminated on the first solder resist layer and has an opening that exposes one surface of the bump.

FIG. 1 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention. 1 is a sectional view of an electronic device package according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a printed circuit board according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of an electronic device package according to another embodiment of the present invention. It is a figure showing the manufacturing process of the printed circuit board concerning one example of the present invention. It is a figure showing the manufacturing process of the printed circuit board concerning one example of the present invention. It is a figure which shows the manufacturing process of the printed circuit board based on another Example of this invention. It is a figure which shows the manufacturing process of the printed circuit board based on another Example of this invention.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the invention. A singular expression includes a plural expression unless expressly stated otherwise in a sentence.

In this application, when we say that a part "includes" a certain component, this does not mean excluding other components, unless there is a specific statement to the contrary, but it does mean that it can further include other components. means.

Further, throughout the specification, "above" means to be located above or below the target part, and does not necessarily mean to be located above with respect to the direction of gravity.

In addition, "coupling" does not mean only the case where each component directly physically contacts in the contact relationship between each component, but also the case where another configuration is interposed between each component, It is used as a concept that covers cases where each component is in contact with other components.

The terms first, second, etc. are used to describe various constituent elements, and the above constituent elements are not limited by the above terms. The above terms are only used to distinguish one component from another.

The size and thickness of each component shown in the drawings are shown arbitrarily for convenience of explanation, and the present invention is not necessarily limited thereto.

Embodiments of a printed circuit board and an electronic device package including the same according to the present invention will be described in detail with reference to the accompanying drawings. A reference numeral is attached to the reference numeral, and a redundant explanation thereof will be omitted.

Furthermore, each embodiment of the present invention described below does not necessarily represent a single embodiment, but must be understood as a concept encompassing embodiments that are dependent on each embodiment. .

FIG. 1 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an electronic device package according to an embodiment of the present invention.

Referring to FIG. 1, a printed circuit board according to an embodiment of the present invention includes a laminate, a first solder resist layer, a bump, a second solder resist layer, and further includes a third solder resist layer. can be included.

The laminate 100 is composed of an insulating layer 110 and a circuit layer 120, and has one side and the other side. Here, one surface and the other surface of the laminate 100 refer to both surfaces facing each other, excluding the side surfaces. Hereinafter, in the present invention, one surface of the laminate 100 is the surface on which the electronic element 600 is mounted and faces another package substrate (see 800 in FIG. 2), and the other surface is the surface that faces the main board. This is the surface to be joined. Based on FIG. 1, the top surface of the laminate 100 is one surface, and the bottom surface is the other surface.

The insulating layer 110 of the laminate 100 is made of an insulating material such as resin, and has a thin plate shape. As the resin for the insulating layer 110, various materials such as thermosetting resin and thermoplastic resin can be used, and specific examples include epoxy resin and polyimide. Here, the epoxy resin includes, for example, naphthalene epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin, cresol novolak epoxy resin, rubber modified epoxy resin, and cycloaliphatic epoxy resin. Examples include, but are not limited to, resins, silicone-based epoxy resins, nitrogen-based epoxy resins, and phosphorus-based epoxy resins.

The insulating layer 110 may be a prepreg (PPG) or a build up film. In the case of prepreg, a reinforcing material 300 such as glass fiber may be included in the epoxy resin described above. In the case of a build-up film, the epoxy resin described above may contain an inorganic filler such as silica (SiO ₂ ). Examples of this build-up film include ABF (Ajinomoto Build-up Film).

However, as the inorganic filler contained in the build-up film, one of silica (SiO ₂ ), barium sulfate (BaSO ₄ ), and alumina (Al ₂ O ₃ ) may be selected or used. The above can be used in combination. Other inorganic fillers include calcium carbonate, magnesium carbonate, fly ash, natural silica, synthetic silica, kaolin, clay, calcium oxide, magnesium oxide, titanium oxide, zinc oxide, potassium hydroxide, aluminum hydroxide, and hydroxide. Examples include, but are not limited to, magnesium, talc, mica, hydrotalcite, aluminum silicate, magnesium silicate, calcium silicate, calcined talc, wollastonite, potassium titanate, magnesium sulfate, calcium sulfate, and magnesium phosphate.

The stacked body 100 can be composed of a plurality of insulating layers 110 stacked one above the other. Although three insulating layers 110 are shown in FIG. 1, there is no limit to the number of insulating layers 110.

The circuit layer 120 of the laminate 100 is a patterned conductor for transmitting electrical signals, and is formed to have a predetermined width and thickness, and has a length or thickness depending on the circuit design. The shape can be determined. The circuit layer 120 can be formed of metal, such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), or platinum in consideration of electrical conductivity. (Pt) or an alloy thereof.

The circuit layer 120 is formed on the insulating layer 110, and when there is a plurality of insulating layers 110, it is formed for each insulating layer 110. The circuit layer 120 can be formed on one or both sides of the insulating layer 110, and can be embedded in one or both sides of the insulating layer 110.

In FIG. 1, three insulating layers 110 are shown, in which case the circuit layer 120 may be four layers.

The circuit layer 121 formed on one surface of the stacked body 100 among the circuit layers 120 may be embedded in the insulating layer 110 . Further, the circuit layer 121 formed on one surface of the stacked body 100 may include terminal pads 121'. This terminal pad 121' is a portion on which an electronic element 600, which will be described later, is mounted. Meanwhile, the circuit layer 122 formed on the other surface of the laminate 100 may be formed to protrude from the other surface of the laminate 100.

The circuit layer 120 may include a metal foil (not shown, see S1 in FIG. 3) and a seed layer (not shown, see S2 in FIG. 3), excluding the metal foil and the seed layer of the circuit layer 120. The remaining portion can be formed by electroplating using the seed layer as a lead-in wire. In this case, the circuit layer 120 may include a metal foil, a seed layer, and an electroplated layer in this order. The metal foil and seed layer may be the result of circuit layer 120 being formed by a modified semi-additive process (MSAP). Therefore, the metal foil and seed layer of the circuit layer 120 are not necessarily formed in the present invention, and their presence or absence is determined depending on the manufacturing method of the circuit layer 120. For example, when the circuit layer 120 is formed by a subtractive method (ex. Tenting) or a semi-additive method (SAP), the circuit layer 120 can include only a seed layer without metal foil.

The stacked body 100 may further include vias 130, and the vias 130 electrically connect the circuit layers 120 that are vertically spaced apart. That is, the vias 130 connect circuit layers 120 that are formed in different insulating layers 110 or on both sides of the same insulating layer 110. Via 130 can also be formed of metal, and can be formed of the same metal as circuit layer 120. Via 130 may also include a seed layer.

The first solder resist layer 200 is laminated on one surface of the laminate 100 to cover the circuit layer 120 with a photosensitive resin material and prevent unnecessary short circuits. In particular, the first solder resist layer 200 covers the circuit layer 121 formed on one surface of the laminate 100. When the circuit layer 121 formed on one surface of the laminate 100 is embedded in the insulating layer 110, the first solder resist layer 200 contacts one surface of the laminate 100 and one exposed surface of the embedded circuit layer 121. It is formed like this.

The first solder resist layer 200 includes a first cavity 210 through which the terminal pad 121' is exposed. A surface treatment layer of gold (Au), nickel (Ni), or the like may be formed on the exposed surface of the terminal pad 121'. Further, the electronic device 600 is inserted into the first cavity 210 and mounted on the terminal pad 121'.

The bumps 140 are formed on one surface of the laminate 100 through the first solder resist layer 200 and are electrically connected to the circuit layer 120 of the laminate 100 . In particular, the bumps 140 can be connected and in contact with the circuit layer 121 formed on one side of the stacked body 100. The bump 140 protrudes beyond the first solder resist layer 200, and as shown in FIG. , the protrusion may be located above the penetration, and the cross-sectional area of the penetration may be smaller than the cross-sectional area of the protrusion.

The bump 140 may be located outside the first cavity 210. For example, the first cavity 210 may be located at the center of the printed circuit board, and the bumps 140 may be located at the periphery of the first cavity 210. On the other hand, the bumps 140 can be formed of a metal including the same metal as the circuit layer 120, but are not limited to these, and are made of copper (Cu), palladium (Pd), aluminum (Al), etc. in consideration of electrical conductivity. It can be formed from metals such as nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or alloys thereof. The bump 140 may include a seed layer S2, and a surface treatment layer of gold (Au), nickel (Ni), etc. may be formed on the surface of the bump 140.

The second solder resist layer 300 is laminated on the first solder resist layer 200 and includes an opening 320 that exposes one surface of the bump 140. Here, one surface of the bump 140 is a surface facing another package substrate, and may be the top surface of the bump 140 in FIG. 1.

The cross-sectional area of the opening 320 is smaller than the area of one side of the bump 140, so that the second solder resist layer 300 can cover the end of one side of the bump 140. A bonding member 700, which will be described later, may be formed on the exposed upper surface of the bump 140.

The thickness of the second solder resist layer 300 may be greater than the thickness of the first solder resist layer 200. When the circuit layer 121 formed on one side of the laminate 100 is embedded in the insulating layer 110, the first solder resist layer 200 can perform its function even if it covers one side of the laminate 100 with a small thickness. On the other hand, since the second solder resist layer 300 is formed higher than the bump (especially the protrusion) 140, the thickness of the second solder resist layer 300 is the same as that of the first solder resist layer 200. It may be larger than that, but is not limited to this.

The second solder resist layer 300 includes a second cavity 310 , and the second cavity 310 corresponds to the first cavity 210 . Here, "corresponding" means that when the first cavity 210 and the second cavity 310 are projected onto a virtual plane parallel to the printed circuit board, the two cavities 210 and 310 overlap each other, and preferably The center lines of the first cavity 210 and the second cavity 310 may substantially coincide. The electronic device 600 can be inserted into the first cavity 210 and the second cavity 310.

The cross-sectional area of the second cavity 310 may be larger than the cross-sectional area of the first cavity 210. Thereby, the first solder resist layer 200 can be exposed through the second cavity 310 in a plan view.

The second solder resist layer 300 makes it possible to secure the height of the printed circuit board in areas other than the cavities 210 and 310, and when the second solder resist has a sufficient height, the interposer board is omitted in the POP board. can.

The third solder resist layer 400 is laminated on the other surface of the laminate 100 in order to cover the circuit layer 120 with a photosensitive resin material and prevent unnecessary short circuits. It is located on the opposite surface to the solder resist layer 200.

The third solder resist layer 400 covers the circuit layer 122 formed on the other surface of the laminate 100, and when the circuit layer 122 formed on the other surface of the laminate 100 protrudes from the other surface of the laminate 100, , the third solder resist layer 400 is stacked higher than the protruding circuit layer 122. Further, if the circuit layer 122 formed on the other surface of the laminate 100 protrudes from the other surface of the laminate 100 and the circuit layer 121 formed on one surface of the laminate 100 is embedded in the insulating layer 110, the third solder The thickness of the resist layer 400 may be greater than the thickness of the first solder resist layer 200.

The third solder resist layer 400 is provided with a first opening 410 to expose one surface of the circuit layer 122 formed on the other surface of the stacked body 100. Here, one surface of the circuit layer 122 is a surface facing the main board, and may be the lower surface of the circuit layer 122 in FIG. 1. The width of the first opening 410 is smaller than the width of the circuit layer 120, so that the third solder resist layer 400 can cover an edge of the circuit layer 120. A bonding agent such as solder may be formed on the exposed bottom surface of the circuit layer 120 to bond it to the main board.

Referring to FIG. 2, an electronic device package according to an embodiment of the present invention includes a printed circuit board on which an electronic device 600 is mounted, and may further include a package substrate 800 bonded to the printed circuit board. Further, the printed circuit board and the package board 800 can be bonded by a bonding member 700. This electronic device package may be a POP.

The printed circuit board includes a laminate 100 composed of an insulating layer 110 and a circuit layer 120, a first solder resist layer 200 laminated on one surface of the laminate 100, and a layer that penetrates the first solder resist layer 200. a bump 140 formed on one surface of the laminate 100 and electrically connected to the circuit layer 120; and an opening 320 laminated on the first solder resist layer 200 and exposing one surface of the bump 140. and a second solder resist layer 300, and may further include a third solder resist layer 400. The explanation regarding this printed circuit board is the same as that explained with reference to FIG.

The electronic device 600 is mounted on a printed circuit board, and for convenience, the electronic device mounted on the printed circuit board is referred to as a first electronic device 600 and is distinguished from a second electronic device 810 that is mounted on a package board 800. . The first electronic device 600 is inserted into the first cavity 210 of the first solder resist layer 200 and the second cavity 310 of the second solder resist layer 300, and the first electronic element 600 is inserted into the first cavity 210 of the first solder resist layer 200 and the second cavity 310 of the second solder resist layer 300. It can be mounted on the terminal pad 121' using a conductive member 610 such as solder. However, the first electronic device 600 can be mounted on the printed circuit board using a wire bonding method instead of a flip chip method using the conductive member 610.

The first electronic device 600 includes various devices such as active devices, passive devices, and integrated circuits (ICs), and may be, for example, a semiconductor chip.

The package substrate 800 is a substrate on which a second electronic device 810 is mounted, and is bonded onto a printed circuit board. In particular, the package substrate 800 may be mounted to face the surface of the printed circuit board on which the first electronic device 600 is mounted, and the second electronic device 810 may be mounted on the opposite surface. The second electronic device 810 can be mounted on the package substrate 800 using a flip-chip method or a wire bonding method. In FIG. 2, the second electronic device 810 is bonded to the substrate and electrically connected to the substrate using wires. Implemented by

The bonding member 700 for bonding the printed circuit board and the package board 800 connects the bumps 140 of the printed circuit board and the connection pads of the package board 800 to each other. The joining member 700 may be a solder ball.

The bonding member 700 does not contact the first solder resist layer 200 but can contact the second solder resist layer 300 . This is because the bonding member 700 is formed on the bump 140 and the height of the bonding member 700 is higher than the first solder resist layer 200. Even if the solder balls have a narrow pitch and a low height, the bumps 140 and the second solder resist layer 300 raise the position of the solder balls, so the printed circuit board and the package board 800 can be stably bonded. can.

FIG. 3 is a cross-sectional view of a printed circuit board according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of an electronic device package according to another embodiment of the present invention.

Referring to FIG. 3, a printed circuit board according to another embodiment of the present invention includes a laminate 100, a first solder resist layer 200, a bump 140, a second solder resist layer 300, and a third solder resist layer 300. The solder resist layer 400, a reinforcing material 420, and a fourth solder resist layer 500 may further be included.

Descriptions regarding the laminate 100, first solder resist layer 200, bumps 140, second solder resist layer 300, and third solder resist layer 400 are the same as those described with reference to FIGS. 1 and 2, and will be omitted. .

The reinforcing material 420 is formed on the third solder resist layer 400 to provide rigidity to the printed circuit board.

The reinforcing material 420 can be formed of metal, including the metal forming the circuit layer 120. The reinforcing material 420 can be formed by the same method as that used to form the circuit layer 120. Thereby, the reinforcing material 420 can include the metal foil S1 and the seed layer S2, and as described above, the reinforcing material 420 can also include only the seed layer S2 depending on the method of forming the reinforcing material 420. Further, the reinforcing material 420 can also be formed by patterning the reinforcing material 420 and then attaching the patterned reinforcing material 420 onto the first solder resist layer 200 instead of using the circuit forming method. There are no restrictions.

The stiffener 420 may have greater rigidity or modulus than the circuit layer 120. Rigidity means the rate of deformation in response to external force, and can simply be said to be the rate of deformation when axial force (vertical stress) is applied. This stiffness varies depending on the modulus of elasticity or Young's modulus, and it should be understood that the larger the elastic modulus or Young's modulus, the greater the stiffness.

Although the reinforcing material 420 is formed on the third solder resist layer 400, the reinforcing material 420 can be formed not to have an area larger than the third solder resist layer 400. That is, the reinforcing material 420 does not cover the first opening 410 of the third solder resist layer 400.

The fourth solder resist layer 500 is formed on the third solder resist layer 400 and covers the reinforcing material 420. Thereby, the reinforcing material 420 is covered with the third solder resist layer 400 and the fourth solder resist layer 500. That is, the reinforcing material 420 is in contact with the surface of the third solder resist layer 400, and the surface of the reinforcing material 420 that is not in contact with the third solder resist layer 400 is in contact with the fourth solder resist layer 500. Accordingly, the reinforcing material 420 is not exposed to the outside.

The fourth solder resist layer 500 includes a second opening 510, and the second opening 510 corresponds to the first opening 410. That is, the first opening 410 and the second opening 510 are formed to overlap each other, and the circuit layer 122 formed on the other surface of the stacked body 100 may be exposed through the first opening 410 and the second opening 510.

The cross-sectional area of the first opening 410 may be smaller than the cross-sectional area of the second opening 510. Accordingly, the third solder resist layer 400 may be exposed through the second opening 510.

Referring to FIG. 4, an electronic device package according to another embodiment of the present invention includes a printed circuit board on which an electronic device 600 is mounted, and may further include a package substrate 800 bonded to the printed circuit board. Furthermore, the printed circuit board and the package board 800 can be bonded together using a bonding member 700. This electronic device package may be a POP.

The printed circuit board includes a laminate 100 composed of an insulating layer 110 and a circuit layer 120, a first solder resist layer 200 laminated on one surface of the laminate 100, and a layer that penetrates the first solder resist layer 200. a bump 140 formed on one surface of the laminate 100 and electrically connected to the circuit layer 120; and an opening 320 laminated on the first solder resist layer 200 and exposing one surface of the bump 140. The second solder resist layer 300 may further include a third solder resist layer 400, a reinforcing material 420, and a fourth solder resist layer 500. The explanation regarding this printed circuit board is the same as that explained with reference to FIGS. 1 and 3.

The electronic device 600 is mounted on a printed circuit board, and for convenience, the electronic device mounted on the printed circuit board is referred to as a first electronic device 600 and is distinguished from a second electronic device 810 that is mounted on a package board 800. . The first electronic device 600 is inserted into the first cavity 210 of the first solder resist layer 200 and the second cavity 310 of the second solder resist layer 300, and the first electronic element 600 is inserted into the first cavity 210 of the first solder resist layer 200 and the second cavity 310 of the second solder resist layer 300. It can be mounted on the terminal pad 121' using a conductive member 610 such as solder. However, the first electronic device 600 can be mounted on the printed circuit board using a wire bonding method instead of the flip-chip method using the conductive member 610.

The first electronic device 600 includes various devices such as active devices, passive devices, and integrated circuits (ICs), and may be, for example, a semiconductor chip.

The package substrate 800 is a substrate on which a second electronic device 810 is mounted, and is bonded onto a printed circuit board. In particular, the package substrate 800 may be mounted to face the surface of the printed circuit board on which the first electronic device 600 is mounted, and the second electronic device 810 may be mounted on the opposite surface. The second electronic element 810 can be mounted on the package substrate 800 by a flip-chip method or a wire bonding method. In FIG. It is implemented using a bonding method.

The bonding member 700 for bonding the printed circuit board and the package board 800 connects the bumps 140 of the printed circuit board and the connection pads of the package board 800 to each other. This joining member 700 may be a solder ball.

The bonding member 700 does not contact the first solder resist layer 200 but can contact the second solder resist layer 300 . This is because the bonding member 700 is formed on the bump 140 and the height of the bonding member 700 is higher than the first solder resist layer 200. Even if the solder balls have a narrow pitch and a low height, the bumps 140 and the second solder resist layer 300 raise the position of the solder balls, so that the printed circuit board and the package board 800 can be stably bonded.

5 and 6 are diagrams showing the manufacturing process of a printed circuit board according to an embodiment of the present invention. 5 and 6, the printed circuit board according to FIG. 1 can be manufactured.

Referring to FIG. 5(a), a laminate 100 is formed on a carrier C. The laminate 100 can be formed by sequentially stacking a plurality of insulating layers 110 on a carrier C, and the carrier C includes an insulating material C0, a carrier metal C1, and a seed metal C2, and the carrier metal C1 and the seed metal C2 is bonded to C2 by a release layer C3 interposed therebetween.

By using the carrier C in this manner, the stacked body 100 can be realized in a coreless form. In this case, the circuit layer 121 formed on one side of the stacked body 100 can be embedded in the insulating layer 110. Meanwhile, in order to form the laminate 100, the circuit layer 120 can be formed by various methods such as MSAP, SAP, and Tenting. The circuit layer 120 may include a seed metal C2 and an electroplated layer formed thereon.

Referring to FIG. 5(b), the stacked body 100 is separated from the carrier C. Specifically, the carrier metal C1 and the seed metal C2 are separated from each other with the mold release layer C3 as a boundary, and the seed metal C2 is removed by etching.

Referring to FIG. 5(c), solder resist layers are applied to both sides of the laminate 100. The applied solder resist layer may be pre-cured. The solder resist layer applied to one side of the laminate 100 becomes the first solder resist layer 200, and the solder resist layer applied to the other side of the laminate 100 becomes the third solder resist layer 400.

Referring to FIG. 5(d), a photosensitive dry film D is attached on the solder resist layer, and the dry film D is patterned. The dry film D can be patterned through an exposure and development process.

Referring to FIG. 5(e), the solder resist layer corresponding to the portions opened by patterning the dry film D is removed. As a result, the first solder resist layer 200 including the first cavity 210 and the third solder resist layer 400 including the first opening 410 are formed. On the other hand, the solder resist layer can be removed by a photo process including exposure and development, or by blast processing. If carried out by blasting, a chemical post-treatment can be carried out as a subsequent step to remove residual solder resist.

Referring to FIG. 6(f), the dry film is peeled off, and the first solder resist layer 200 and the third solder resist layer 400 are post-cured. If necessary, curing using UV may be further performed.

Referring to FIG. 6(g), the seed layer S2 is formed by vapor deposition, electroless plating, or the like. Seed layer S2 can be formed of metal such as copper, titanium/copper, etc. The seed layer S2 is formed on the first solder resist layer 200 and also inside the first cavity 210.

Referring to FIG. 6H, bumps 140 penetrating the first solder resist layer 200 are formed. The bump 140 penetrates the first solder resist layer 200 , protrudes beyond the first solder resist layer 200 , and contacts the upper surface of the first solder resist layer 200 . On the other hand, when forming the bump 140, unnecessary seed layer S2 in the area other than the bump 140 is removed by etching or the like.

Referring to FIG. 6(i), a second solder resist layer 300 is formed on the first solder resist layer 200. The second resist layer includes a second cavity 310 corresponding to the first cavity 210 and an opening 320 that exposes the top surface of the bump 140.

The second solder resist layer 300 can be formed by applying a solder resist to the entire surface of the printed circuit board and then selectively removing the solder resist corresponding to the second cavity 310 and the opening 320 area. Selective removal of the solder resist can be performed by mechanical processing such as exposure/development or blasting. At this time, if both the first solder resist layer 200 and the second solder resist layer 300 are photosensitive, each of the first solder resist layer 200 and the second solder resist layer 300 is made of different materials or different light-sensitive materials. By having the characteristic of reacting to different wavelengths (for example, mutually different wavelengths), the second solder resist layer 300 can be formed by an exposure/development process without affecting the first solder resist layer 200.

7 and 8 are diagrams showing the manufacturing process of a printed circuit board according to another embodiment of the present invention. 7 and 8, the printed circuit board according to FIG. 3 can be manufactured.

Referring to FIG. 7(a), a laminate 100 is formed on the carrier C. The laminate 100 can be formed by sequentially stacking a plurality of insulating layers 110 on a carrier C, the carrier C includes an insulating material C0, a carrier metal C1, and a seed metal C2, and the carrier metal C1 and the seed metal C2 and are bonded to each other by a release layer C3 interposed therebetween.

In this way, by using the carrier C, the laminate 100 can be manufactured in a coreless form. In this case, the circuit layer 121 formed on one side of the stacked body 100 can be embedded in the insulating layer 110.

On the other hand, in order to form the laminate 100, the circuit layer 120 can be formed by various methods such as MSAP, SAP, and Tenting, and the circuit layer 120 includes a seed metal C2 and an electroplated layer formed thereon. can include.

Referring to FIG. 7B, a third solder resist layer 400 is formed on the laminate 100, a first opening 410 is formed in the third solder resist layer 400, and the circuit layer 122 is exposed.

Referring to FIG. 7C, a seed layer S2 is formed on the third solder resist layer 400 by vapor deposition, electroless plating, or the like. The seed layer S2 is also formed on the surface of the circuit layer 122 exposed through the first opening 410.

Referring to FIG. 7D, an electroplating layer is formed on the seed layer S2, and a patterned plating resist can be used at this time. The seed layer S2 and the electroplated layer formed thereon become the reinforcing material 420, and unnecessary seed layer S2 other than the reinforcing material 420 area is removed by etching or the like.

Referring to FIG. 7E, a fourth solder resist layer 500 covering the reinforcing material 420 is formed on the third solder resist layer 400. Thereby, the reinforcing material 420 is covered with the third solder resist layer 400 and the fourth solder resist layer 500.

Referring to FIG. 8(f), an additional carrier C is deposited on the fourth solder resist layer 500, and referring to FIG. 8(g), the stack 100 is separated from the existing carrier C. Specifically, the carrier metal C1 and the seed metal C2 are separated from each other with the mold release layer C3 as a boundary, and the seed metal C2 is removed by etching. The additional carrier C facilitates handling of the stack 100.

Referring to FIG. 8(h), a first solder resist layer 200 is formed. The first solder resist layer 200 can be formed by opening the regions where the first cavities 210 and the bumps 140 are to be formed after the solder resist is applied. Meanwhile, a seed layer S2 is formed on the first solder resist layer 200 by a method such as vapor deposition or electroless plating.

Referring to FIG. 8(i), bumps 140 are formed. The bump 140 penetrates the first solder resist layer 200 , protrudes beyond the first solder resist layer 200 , and contacts the upper surface of the first solder resist layer 200 . On the other hand, when forming the bump 140, unnecessary seed layer S2 in the area other than the bump 140 is removed by a method such as etching.

Referring to FIG. 8(j), a second solder resist layer 300 is formed on the first solder resist layer 200. The second resist layer includes a second cavity 310 corresponding to the first cavity 210 and an opening 320 that exposes the top surface of the bump 140.

The second solder resist layer 300 can be formed by applying a solder resist to the entire surface of the printed circuit board and then selectively removing the solder resist corresponding to the second cavity 310 and the opening 320 area. Selective removal of the solder resist can be performed by mechanical processing such as exposure/development or blasting. At this time, when both the first solder resist layer 200 and the second solder resist layer 300 are photosensitive, each of the first solder resist layer 200 and the second solder resist layer 300 is made of different materials or different light ( For example, since the second solder resist layer 300 can be formed by an exposure/development process without affecting the first solder resist layer 200, the second solder resist layer 300 can be formed by an exposure/development process.

Referring to FIG. 8(k), the additional carrier C is removed, and specifically, the carrier metal C1 and the seed metal C2 are separated from each other with the release layer C3 as a boundary, and the seed metal C2 is etched. removed. Thereafter, a surface treatment layer may be formed on the surface of the terminal pad 121' exposed through the first cavity 210 and the second cavity 310, if necessary.

Although the embodiments of the present invention have been described above, a person having ordinary knowledge in the relevant technical field will understand that additions and changes of constituent elements can be made without departing from the idea of the present invention described in the claims. The present invention can be modified and changed in various ways by adding, deleting, adding, etc., and these are also within the scope of the rights of the present invention.

100 Laminated body 110 Insulating layers 120, 121, 122 Circuit layer 121' Terminal pad 130 Via 140 Bump S1 Metal foil S2 Seed layer 200 First solder resist layer 210 First cavity 300 Second solder resist layer 310 Second cavity 320 Opening 400 Third solder resist layer 410 First opening 420 Reinforcing material 500 Fourth solder resist layer 510 Second opening 600 First electronic element 610 Conductive member 700 Bonding member 800 Package substrate 810 Second electronic element 820 Connection pad 830 Wire C Carrier C0 Insulating material C1 Carrier metal C2 Seed metal C3 Release layer D Dry film

Claims (32)

A laminate composed of an insulating layer and a circuit layer,
a first solder resist layer laminated on one surface of the laminate;
a bump that is formed on one surface of the laminate through the first solder resist layer and electrically connects to the circuit layer;
a second solder resist layer laminated on the first solder resist layer and provided with an opening that exposes one surface of the bump;
The thickness of the second solder resist layer is greater than the thickness of the first solder resist layer. a first cavity penetrating the first solder resist layer;
The printed circuit board of claim 1 , further comprising a second cavity extending through the second solder resist layer and corresponding to the first cavity. 3. The printed circuit board according to claim 2, wherein a portion of the circuit layer formed on one surface of the laminate is exposed through the first cavity and the second cavity. The printed circuit board according to claim 2 or 3, wherein the cross-sectional area of the first cavity is smaller than the cross-sectional area of the second cavity. The printed circuit board according to any one of claims 2 to 4, wherein the bump is located outside the first cavity. A plurality of the insulating layers are formed,
The circuit layer is formed on each of the plurality of insulating layers,
The printed circuit board according to any one of claims 1 to 5, wherein the laminate further includes a via connecting to the circuit layer. 7. The printed circuit board according to claim 1, wherein the circuit layer formed on one surface of the insulating layer among the circuit layers is embedded within the insulating layer. The printed circuit board according to any one of claims 1 to 7, further comprising a third solder resist layer laminated on the other surface of the laminate. The printed circuit board of claim 8, further comprising a fourth solder resist layer laminated on the third solder resist layer. The printed circuit board according to claim 9, further comprising a reinforcing material formed on the third solder resist layer. The printed circuit board according to claim 10, wherein the reinforcing material is covered by the third solder resist layer and the fourth solder resist layer. 12. The printed circuit board according to claim 10, wherein the reinforcing material is formed of a metal containing the same metal as the circuit layer. A first opening is formed in the third solder resist layer to expose a circuit layer formed on the other surface of the laminate among the circuit layers,
The printed circuit board according to any one of claims 9 to 12, wherein a second opening corresponding to the first opening is formed in the fourth solder resist layer. 14. The printed circuit board of claim 13, wherein the first opening has a smaller cross-sectional area than the second opening. The printed circuit board according to any one of claims 8 to 14, wherein the thickness of the third solder resist layer is greater than the thickness of the first solder resist layer. a printed circuit board on which electronic elements are mounted;
a package substrate bonded to the printed circuit board;
The printed circuit board includes:
A laminate composed of an insulating layer and a circuit layer,
a first solder resist layer laminated on one surface of the laminate;
a bump that is formed on one surface of the laminate through the first solder resist layer and electrically connects to the circuit layer;
a second solder resist layer laminated on the first solder resist layer and provided with an opening that exposes one surface of the bump;
The thickness of the second solder resist layer is greater than the thickness of the first solder resist layer. a first cavity penetrating the first solder resist layer;
further comprising a second cavity penetrating the second solder resist layer and corresponding to the first cavity,
The electronic device package of claim 16, wherein the electronic device is inserted into the first cavity and the second cavity. 18. The electronic device package according to claim 17, wherein the electronic device is mounted on a part of the circuit layer formed on one surface of the laminate, using a conductive member as an intermediary. The electronic device package according to claim 17 or 18, wherein a cross-sectional area of the first cavity is smaller than a cross-sectional area of the second cavity. The electronic device package according to any one of claims 17 to 19, wherein the bump is located outside the electronic device. A plurality of the insulating layers are formed,
The circuit layer is formed on each of the plurality of insulating layers,
The electronic device package according to any one of claims 16 to 20, wherein the laminate further includes a via connecting to the circuit layer. 22. The electronic device package according to claim 16, wherein the circuit layer formed on one surface of the insulating layer among the circuit layers is embedded within the insulating layer. The electronic device package according to any one of claims 16 to 22, further comprising a third solder resist layer laminated on the other surface of the laminate. The electronic device package of claim 23, further comprising a fourth solder resist layer laminated on the third solder resist layer. The electronic device package according to claim 24, wherein a reinforcing material is formed on the third solder resist layer. The electronic device package according to claim 25, wherein the reinforcing material is covered by the third solder resist layer and the fourth solder resist layer. 27. The electronic device package according to claim 25, wherein the reinforcing material is made of the same metal as the metal forming the circuit layer. A first opening is formed in the third solder resist layer to expose a circuit layer formed on the other surface of the laminate among the circuit layers,
28. The electronic device package according to claim 24, wherein a second opening corresponding to the first opening is formed in the fourth solder resist layer. 29. The electronic device package of claim 28, wherein a cross-sectional area of the first opening is smaller than a cross-sectional area of the second opening. The electronic device package according to any one of claims 23 to 29, wherein the third solder resist layer has a thickness greater than the first solder resist layer. The electronic device package according to any one of claims 16 to 30, further comprising a bonding member formed on the bump and bonding the printed circuit board and the package substrate. The electronic device package according to claim 31, wherein the bonding member is located higher than the first solder resist layer and does not contact the first solder resist layer.

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