KR20170086921A - Package substrate and method for manufacturing the same - Google Patents

Abstract

A package substrate according to an aspect of the present invention includes: a first insulating layer having a first cavity; A metal pillar formed through the first insulating layer in a thickness direction; A second insulating layer stacked under the first insulating layer; A pad embedded in the second insulating layer such that an upper surface thereof is exposed by the first cavity; And a first solder resist layer formed on the first insulating layer and having an opening exposing the upper surface of the metal pillar, wherein the first solder resist layer is formed on the first cavity, May be larger than the thickness of the first insulating layer and the upper surface of the metal pillar may be positioned between the upper surface of the first insulating layer and the upper surface of the first solder resist layer.

Description

[0001] DESCRIPTION [0002] PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME [0003]

The present invention relates to a package substrate and a manufacturing method thereof.

Package z-height Many embedded or cavity structures are being developed for shrinking. However, the embedded substrate still has many problems to mount the high I / O chip, and the cavity substrate has not developed an inexpensive and efficient process for realizing cavity depth or cavity shape.

Currently, it is used as a method of forming a cavity on a substrate. However, it needs to develop more bump formation and surface treatment capable of supporting deep cavity depth of 150um or more, high I / O like AP PKG Do.

U.S. Published Patent Application No. US20120159118

According to an aspect of the present invention, there is provided a semiconductor device comprising: a first insulating layer having a first cavity; A metal pillar formed through the first insulating layer in a thickness direction; A second insulating layer stacked under the first insulating layer; A pad embedded in the second insulating layer such that an upper surface thereof is exposed by the first cavity; And a first solder resist layer formed on the first insulating layer and having an opening exposing the upper surface of the metal pillar, wherein the first solder resist layer is formed on the first cavity, Is higher than the thickness of the first insulating layer and the upper surface of the metal pillar is positioned between the upper surface of the first insulating layer and the upper surface of the first solder resist layer.

The first cavities may be formed in a plurality of pads, and the pads may be formed in a plurality of pads, and at least one of the plurality of pads may be exposed by the plurality of first cavities.

And a circuit embedded in the second insulating layer.

And a metal paste formed on the upper surface of the metal pillar.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: stacking a first solder resist layer on a carrier; Patterning the first solder resist layer to form an opening and a cavity; Inserting a metal pillar into the opening and inserting a metal block into the cavity; Stacking a first insulating layer on the solder resist layer to cover the sides of the metal pillar and the metal block; Forming a pad protruding from the first insulating layer on the surface of the metal block; Stacking a second insulating layer on the first insulating layer to cover the pad; And removing the metal block such that the pad is exposed to the second insulating layer.

1 shows a package substrate according to a first embodiment of the present invention.
2 is a view showing an electronic component package using a package substrate according to the first embodiment of the present invention.
3 shows a package substrate according to a second embodiment of the present invention.
4 shows a package substrate according to a third embodiment of the present invention.
5 shows a package substrate according to a fourth embodiment of the present invention.
6 shows a package substrate according to a fifth embodiment of the present invention.
7 to 16 are views showing a method of manufacturing a package substrate according to the first embodiment of the present invention.
17 shows a part of a method for manufacturing a package substrate according to a second embodiment of the present invention.
18 shows a part of a method of manufacturing a package substrate according to a third embodiment of the present invention.
19 shows a part of a method of manufacturing a package substrate according to a fourth embodiment of the present invention.
20 shows a part of a method of manufacturing a package substrate according to a fifth embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a package substrate according to an embodiment of the present invention; Fig. 2 is a cross- The description will be omitted.

It is also to be understood that the terms first, second, etc. used hereinafter are merely reference numerals for distinguishing between identical or corresponding components, and the same or corresponding components are defined by terms such as first, second, no.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

Package substrate

1 is a view showing a package substrate according to a first embodiment of the present invention.

Referring to FIG. 1, a package substrate according to a first embodiment of the present invention includes a first insulating layer 110, a metal pillar 120, a second insulating layer 130, a pad 140, Layer 150, and may further include a third insulating layer 160, a second solder resist layer 170, and the like.

The first insulating layer 110 may include a first cavity 111. The first cavity 111 is a through hole penetrating the first insulating layer 110 in the thickness direction, and is a space for accommodating the first electronic component 180. The first cavity 111 may penetrate the entire thickness of the first insulating layer 110.

The metal pillar 120 is a columnar metal body formed by penetrating the first insulating layer 110 in the thickness direction, and is formed at a place where the first cavity 111 is not formed. The metal pillar 120 may serve as an electrical connection medium in bonding between the package substrates.

The thickness of the metal pillar 120 may be greater than the thickness of the first insulating layer 110. In this case, the upper portion of the metal pillar 120 may protrude from the first insulating layer 110 and be exposed. That is, the upper surface of the metal pillar 120 may protrude from the upper surface of the first insulating layer 110.

The metal pillar 120 may be formed in plurality and may be arranged in the periphery of the first cavity 111. In particular, the metal pillar 120 may be formed corresponding to the chip mounting area.

The metal pillar 120 is not limited to a metal and may be made of copper, palladium, aluminum, nickel, titanium, gold, Platinum (Pt) or the like may be used.

The second insulating layer 130 is stacked under the first insulating layer 110. Here, the concept of 'upper and lower' is not an absolute concept, but one direction is set upward in the thickness direction of the package substrate, and the opposite direction is set in the down direction.

As a result, the second insulation layer 130 is stacked on the opposite side of the first insulation layer 110 from the direction in which the metal pillar 120 protrudes.

The first insulating layer 110 and the second insulating layer 130 may be an insulating resin material. The resin of the first insulating layer 110 and the second insulating layer 130 may be thermosetting, thermoplastic or photocurable resin. For example, the resin of the first insulating layer 110 and the second insulating layer 130 may be an epoxy resin, a polyimide, a BT resin (Bismaleimide Triazine Resin), or the like.

Examples of the epoxy resin include epoxy resins such as naphthalene type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac type epoxy resin, cresol novolak type epoxy resin, rubber modified epoxy resin, A silicone-based epoxy resin, a nitrogen-based epoxy resin, a phosphorus-based epoxy resin, and the like, but is not limited thereto.

The first insulating layer 110 and the second insulating layer 130 may be resin impregnated with a reinforcing material. The stiffener may be a fiber reinforcement. The fiber reinforcing material may be a glass fiber, and the glass fiber may be divided into a glass filament, a glass fiber, and a glass fabric depending on the thickness, all of which may be used in the present invention.

On the other hand, prepreg (PPG) is an example of the insulating layer in which the reinforcing material is impregnated into the resin.

The reinforcing material contained in the first insulating layer 110 and the second insulating layer 130 may be an inorganic filler.

The inorganic filler may be selected from the group consisting of silica (SiO2), alumina (Al2O3), silicon carbide (SiC), barium sulphate (BaSO4), talc, mud, mica powder, aluminum hydroxide (AlOH3), magnesium hydroxide At least one selected from the group consisting of calcium (CaCO3), magnesium carbonate (MgCO3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO3), barium titanate (BaTiO3) and calcium zirconate Can be used.

An example of an insulating layer containing an inorganic filler is Ajinomoto Build up Film.

The first insulating layer 110 and the second insulating layer 130 may be made of the same material or different materials. Here, 'different material' may mean that at least one of resin or reinforcement is different.

The pad 140 may be buried in the second insulating layer 130 and the upper surface of the pad 140 may be exposed by the first cavity 111. That is, the pad 140 may be embedded on the upper surface of the second insulating layer 130 in correspondence with the first cavity 111. The pad 140 may partially protrude from the upper surface of the second insulating layer 130, but the side surface of the pad 140 may be completely embedded in the second insulating layer 130.

The pad 140 is connected to the first electronic component 180 accommodated in the first cavity 111 and is formed to correspond to the terminal of the first electronic component 180. [ The pad 140 may be formed in plural.

The pad 140 may be made of a metal material and may be made of copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti) Pt) may be used.

The pad 140 may include a seed layer S and a plating layer P. The seed layer S may include a first cavity 111 and a second cavity 111. The pad 140 may include a seed layer S. In this case, ). ≪ / RTI > The seed layer (S) and the plating layer (P) may be made of the same or different metals.

A first via 131 and a second via 132 may be formed in the second insulating layer 130.

The first via 131 is a via penetrating the second insulating layer 130 to connect to the lower portion of the pad 140. As described above, the plurality of pads 140 may be formed, and at least some of the plurality of pads 140 may be connected to the first vias 131. The first vias 131 may penetrate a part of the thickness of the second insulating layer 130.

The second vias 132 are vias that pass through the second insulation layer 130 to be connected to the lower portion of the metal pillar 120. The second vias 132 may penetrate the entire thickness of the second insulating layer 130.

The first circuit 133 may be formed on a lower surface of the second insulating layer 130 and the first circuit 133 may be electrically connected to the first via 131 and the second via 132.

The first solder resist layer 150 is laminated on the first insulating layer 110 as a photosensitive insulating layer. That is, the first insulating layer 110 is located between the second insulating layer 130 and the first solder resist layer 150.

The first solder resist layer 150 is provided with a second cavity 151. The second cavity 151 corresponds to the first cavity 111. That is, the second cavity 151 is located on the first cavity 111, and the first cavity 111 and the second cavity 151 One entire cavity can be constructed. Here, the size of the first cavity 111 and the size of the second cavity 151 may be the same.

In addition, an opening 152 is formed in the first solder resist layer 150. The opening 152 exposes the upper surface of the metal pillar 120. That is, the opening 152 is formed corresponding to the metal pillar 120. The size of the opening 152 may be the same as the size of the top surface of the metal pillar 120 but the size of the opening 152 is not limited as long as the opening 152 can expose at least a portion of the top surface of the metal pillar 120 Do not.

Meanwhile, the second cavity 151 and the opening 152 may be formed through the entire thickness of the first solder resist layer 150.

In addition, as described above, the upper surface of the metal pillar 120 may protrude from the upper surface of the first insulating layer 110. In this case, the upper surface of the metal pillar 120 may be formed below the upper surface of the first solder resist layer 150. That is, the upper surface of the metal pillar 120 may be positioned between the upper surface of the first insulating layer 110 and the upper surface of the first solder resist layer 150. Therefore, a space may be provided from the upper surface of the metal pillar 120 to the upper surface of the first solder resist layer 150.

The third insulating layer 160 is stacked under the second insulating layer 130. The third insulating layer 160 may be an insulating resin, and the resin may be a thermosetting, thermoplastic or photocurable resin. For example, the resin of the first insulating layer 110 and the second insulating layer 130 may be an epoxy resin, a polyimide, a BT resin (Bismaleimide Triazine Resin), or the like.

In addition, the above-described reinforcing material may be contained in the third insulating layer 160. [ The third insulating layer 160 may be the same insulating layer as the first insulating layer 110 and / or the second insulating layer 130.

A third via 161 may be formed in the third insulating layer 160. The third vias 161 may be connected to at least one of the first vias 131 and the second vias 132. Each of the first vias 131 and the second vias 132 may be formed in plurality and the third vias 161 may be connected to at least one of the plurality of first vias 131, 2 vias 132. In some embodiments,

The first via 131, the second via 132 and the third via 161 may all be made of metal and may be formed of copper (Cu), palladium (Pd), aluminum (Al), nickel Ni), titanium (Ti), gold (Au), platinum (Pt)

The second circuit 162 may be formed on the lower surface of the third insulating layer 160 and the second circuit 162 may be electrically connected to the third via 161.

The second solder resist layer 170 may be laminated under the third insulating layer 160 and the second solder resist layer 170 may expose at least a portion of the second circuit 162. The exposed second circuit 162 may be formed with a connection member connected to an external device such as a main board.

The thickness of the second solder resist layer 170 may be greater than the thickness of the first solder resist layer 150, but is not limited thereto.

2 is a view showing an electronic component package using the package substrate according to the first embodiment of the present invention.

Referring to FIG. 2, two package substrates are connected to each other, and this structure may be a package on package structure.

In the package-on-package structure of FIG. 2, the package substrate located below and the package substrate located above the first package substrate 100 may be referred to as the second package substrate 200, respectively.

The first package substrate 100 may be the package substrate shown in FIG.

That is, the first electronic component 180 is inserted into the first cavity 111 and connected to the pad 140 through a connecting member such as a solder ball SB. A connection member such as a solder ball SB is formed on the metal pillar 120 and the metal pillar 120 is connected to the second package substrate 200 via a connection member. The second electronic component 210 may be mounted on the second package substrate 200.

Hereinafter, the package substrate according to the second to fifth embodiments of the present invention will be described, and the first package substrate 100 shown in FIG. 2 will be described with reference to FIGS. Can be replaced with a package substrate.

3 is a view showing a package substrate according to a second embodiment of the present invention.

Referring to FIG. 3, in the package substrate according to the second embodiment of the present invention, a plurality of first cavities 111 are formed. Also, the pad 140 may be exposed by all of the plurality of first cavities 111. When there are a plurality of pads 140, at least one of the plurality of pads 140 may be exposed by the plurality of first cavities 111.

In other words, the plurality of first cavities 111 may be partitioned into barrier ribs, and at least one pad 140 may extend over the plurality of first cavities 111. This may be effective when electrical connection between the electronic components accommodated in each of the plurality of first cavities 111 is required.

4 is a view showing a package substrate according to a third embodiment of the present invention.

Referring to FIG. 4, the package substrate according to the third embodiment of the present invention may further include a third circuit 112 in the package according to the first embodiment.

The third circuit 112 is formed on the lower surface of the first insulating layer 110 to be buried on the upper surface of the second insulating layer 130 and may be formed at a level equivalent to that of the pad 140. The third circuit 112 may be connected to the metal pillar 120 and at least a portion of the third circuit 112 may be formed on the bottom surface of the metal pillar 120.

The third circuit 112 may be electrically connected to the second via 132.

The third circuit 112 may also include a seed layer S. [ In this case, the seed layer S is exposed to the upper surface of the second insulating layer 130. At least a portion of the seed layer (S) may be in contact with the metal pillar (120).

In this embodiment, the circuit can be increased by one layer as compared with the package substrate according to the first embodiment.

5 is a view showing a package substrate according to a fourth embodiment of the present invention.

Referring to FIG. 5, in the package substrate according to the fourth embodiment of the present invention, the cross-sectional area of the first cavity 111 may change from the upper portion to the lower portion of the first insulating layer 110. In particular, the cross-sectional area of the first cavity 111 may be reduced from the upper portion of the first insulating layer 110 to the lower portion thereof. That is, the longitudinal shape of the first cavity 111 may be inverted trapezoidal. In this case, the first electronic component 180 can be stably inserted into the first cavity 111.

However, the shape of the first cavity 111 is not limited to that illustrated in the drawings, and the first cavity 111 may have various shapes. For example, the cross-sectional area of the first cavity 111 increases from the top to the bottom of the first insulating layer 110, and the longitudinal profile of the first cavity 111 may be an orthogonal trapezoid.

6 is a view showing a package substrate according to a fifth embodiment of the present invention.

Referring to FIG. 6, the package substrate according to the fifth embodiment may further include the metal paste A in the package substrate according to the first embodiment.

The metal paste A may be formed on the upper surface of the metal pillar 120. The upper surface of the metal paste A may be less than or equal to the upper surface of the first solder resist layer 150.

The metal paste A may be made of a metal having a lower melting point than the metal of the metal pillar 120. For example, the metal paste A may be an alloy containing lead and / or tin. The metal paste A may serve to protect the metal pillar 120.

Package substrate manufacturing method

Hereinafter, a method of manufacturing the package substrate according to the first to fifth embodiments will be described.

7 to 16 are views showing a method of manufacturing a package substrate according to the first embodiment of the present invention.

Referring to FIG. 7, a first solder resist layer 150 is formed on the carrier C, and an opening 152 and a cavity 151 are formed in the first solder resist layer 150. The opening 152 and the cavity 151 may be formed by patterning the first solder resist and the opening 152 and the cavity 151 may be formed in the photolithography process when the first solder resist is photosensitive.

Both the opening 152 and the cavity 151 penetrate the entire thickness of the first solder resist layer 150 and the size of the cavity 151 may be larger than the size of the opening 152.

On the other hand, the carrier C may be composed of the resin layer R and the metal foil M. In this case, the first solder resist layer 150 is formed on the metal foil M. The metal foil M may be a copper foil.

Referring to Fig. 8, a metal paste A is formed in the opening 152 and the cavity 151. Fig. The thickness of the metal paste (A) may be smaller than the thickness of the first solder resist layer (150). The metal paste (A) can serve as an adhesive.

9, the metal pillar 120 is inserted into the opening 152, and the metal block B is inserted into the cavity 151. As shown in Fig.

Finally, the metal pillar 120 remains, but the metal block B is removed and the place where the metal block B is located becomes the cavity 111 again. This will be described later.

The heights of the metal pillar 120 and the metal block B may be greater than the thickness of the first solder resist layer 150 and the heights of the metal pillar 120 and the metal block B may be equal to each other.

Since the thickness of the metal paste A is smaller than the thickness of the first solder resist layer 150, a part of the metal pillar 120 and the metal block B can be inserted into the opening 152 and the cavity 151 have.

The metal pillar 120 and the metal block B may be made of the same metal material, but may be made of different metal materials. When the metal pillar 120 and the metal block B are made of the same metal material, the metal pillar 120 and the metal block B may all be made of copper.

Referring to FIG. 10, a first insulating layer 110 is deposited on the first solder resist layer 150.

The first insulating layer 110 is first laminated so as to cover the entire metal pillar 120 and the metal block B and then the first insulating layer 110 is formed to expose one surface of the metal pillar 120 and the metal block B, A portion of the substrate 110 may be polished. In this case, one side of each of the first insulating layer 110, the metal pillar 120, and the metal block B is located in the same layer. The first insulating layer 110 covers the metal pillar 120 and the metal block B side.

Referring to FIG. 11, a pad 140 is formed.

The pad 140 is formed on one surface of the metal block B. One surface of the metal block B where the pad 140 is formed is a surface of the surface of the metal block B opposite to the first solder resist.

A seed layer S is first formed on the first insulating layer 110, and a dry film D is formed thereon. Thereafter, the dry film D is removed from the place where the pad 140 is formed, and the plating layer P is formed in the place of the removed dry film D. The unnecessary dry film D and the seed layer S are removed, and the pad 140 is completed.

Referring to FIG. 12, a second insulating layer 130, a first via 131, and a second via 132 are formed.

First, a second insulating layer 130 is deposited on the first insulating layer 110 to cover the pad 140. A part of the second insulating layer 130 is removed corresponding to the positions where the first vias 131 and the second vias 132 are formed and the via plating proceeds in the removed second insulating layer 130, The first via 131 and the second via 132 may be formed.

Here, the first circuit 133 can be formed using the patterning and plating method of the dry film (D).

Referring to FIG. 13, a third insulating layer 160 and a second solder resist layer 170 are formed.

After the third insulating layer 160 is formed, the third vias 161 and the second circuit 162 are formed, and then the second solder resist layer 170 is formed. The second solder resist layer may be patterned to expose at least a portion of the second circuit 162 after being applied to cover the entire second circuit 162. [

Referring to Fig. 14, the carrier C is removed.

When the carrier C is composed of the resin layer R and the metal foil M, the resin layer R is first removed by peeling or the like, and the metal foil M can be removed by a method such as etching.

Referring to Fig. 15, the metal paste A is removed.

The metal paste (A) can be removed by a method such as etching. Particularly, since the metal paste A is made of a metal different from the metal pillar 120 and the metal block B, the metal paste A can be formed by using an etching solution which reacts only with the metal forming the metal paste A, (A) can be selectively removed.

16, the metal block B is removed.

The metal block B may be removed by a method such as etching, and an etching resist E may be used to prevent damage to the metal pillar 120 or other circuits. The etching resist (E) may be formed for the remaining metal regions except for the metal block (B). When the unnecessary etching resist (E) is removed, the package substrate is completed. The place where the metal block B is removed becomes a cavity 111 for accommodating the first electronic component 180.

However, the surface of the metal pillar 120, the circuit, and the like may further be subjected to the surface treatment.

17 is a view showing a part of a method of manufacturing a package substrate according to a second embodiment of the present invention.

Referring to FIG. 17, at least one of the pads 140 in the package substrate according to the second embodiment may be formed to have a larger area than the other pads 140.

That is, when the dry film (D) is patterned in the step of forming the pad (140), the sizes of the openings of the dry film (D) may be different from each other.

18 is a view showing a part of a method of manufacturing a package substrate according to a third embodiment of the present invention.

Referring to FIG. 18, a method of manufacturing a package substrate according to a third embodiment of the present invention may include forming a third circuit 112.

The third circuit 112 may be made together in the step of forming the pad 140. That is, when patterning the dry film (D) for forming the pad 140, an opening is formed corresponding to the pad 140 and the third circuit 112, and when the plating layer P is formed in the opening, 112 and the pad 140 may be simultaneously formed.

Alternatively, as shown in FIG. 18, the third circuit 112 may first be formed using the dry film D, and then the pad 140 may be formed using the dry film D again.

Here, when the pad 140 and the third circuit 112 are formed, the seed layer S may be formed first. In this case, the pad 140 and the third circuit 112 may be provided by forming a plating layer P on the seed layer S.

19 is a view showing a part of a method of manufacturing a package substrate according to a fourth embodiment of the present invention.

Referring to FIG. 19, in the method of manufacturing a package substrate according to the fourth embodiment of the present invention, the shape of the metal block B may not be a rectangular parallelepiped. However, the metal pillar 120 may have a rectangular parallelepiped shape.

20 is a view showing a part of a method of manufacturing a package substrate according to a fifth embodiment of the present invention.

20, in the package substrate according to the fifth embodiment of the present invention, in the step of removing the metal paste A, only the metal paste A formed corresponding to the metal block B is removed, The metal paste A formed corresponding to the metal layer 120 is not removed. The etching resist (E) is used, and the metal block (B) can be removed after a part of the metal paste (A) is first removed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention as set forth in the appended claims. The present invention can be variously modified and changed by those skilled in the art, and it is also within the scope of the present invention.

100: first package substrate
110: first insulating layer
111: first cavity
112: Third Circuit
120: metal pillar
130: second insulating layer
131: 1st Via
132: Second Via
133: First circuit
140: Pad
150: first solder resist layer
151: second cavity
152: aperture
160: Third insulating layer
161: Third Via
162: Second circuit
170: second solder resist layer
180: first electronic component
200: second package substrate
210: substrate
220: second electronic component
SB: Solder ball
S: Seed layer
P: Plating layer
B: Metal block
D: Dry film
A: Metal paste

Claims (16)

A first insulating layer having a first cavity;
A metal pillar formed through the first insulating layer in a thickness direction;
A second insulating layer stacked under the first insulating layer;
A pad embedded in the second insulating layer such that an upper surface thereof is exposed by the first cavity; And
And a first solder resist layer formed on the first insulating layer and having an opening exposing the upper surface of the metal pillar, the first solder resist layer having a second cavity located on the first cavity,
The thickness of the metal pillar is larger than the thickness of the first insulating layer,
Wherein the upper surface of the metal pillar is positioned between the upper surface of the first insulating layer and the upper surface of the first solder resist layer.
The method according to claim 1,
A first via penetrating through the second insulating layer to be connected to a lower portion of the pad; And
And a second via penetrating the second insulating layer to connect with the lower portion of the metal pillar.
3. The method of claim 2,
A third insulating layer stacked under the second insulating layer; And
And a third via connected to at least one of the first via and the second via.
The method of claim 3,
A circuit formed on a bottom surface of the third insulating layer to be electrically connected to the third via; And
And a second solder resist layer laminated on a bottom surface of the third insulating layer to cover the circuit.
The method according to claim 1,
The first cavity is formed in a plurality of,
The plurality of pads are formed,
Wherein at least one of the plurality of pads is exposed by a plurality of the first cavities.
The method according to claim 1,
And a circuit embedded in the second insulating layer.
The method according to claim 1,
Wherein the cross-sectional area of the first cavity decreases from the upper surface to the lower surface of the first insulating layer.
The method according to claim 1,
And a metal paste formed on the upper surface of the metal pillar.
Stacking a first solder resist layer on the carrier;
Patterning the first solder resist layer to form an opening and a cavity;
Inserting a metal pillar into the opening and inserting a metal block into the cavity;
Stacking a first insulating layer on the solder resist layer to cover the sides of the metal pillar and the metal block;
Forming a pad protruding from the first insulating layer on the surface of the metal block;
Stacking a second insulating layer on the first insulating layer to cover the pad; And
And removing the metal block such that the pad is exposed to the second insulating layer.
10. The method of claim 9,
Further comprising forming a metal paste on the opening and the bottom of the cavity,
Wherein the metal pillar and the metal block are located on the upper surface of the metal paste.
11. The method of claim 10,
After the step of removing the metal block,
And removing the metal paste.
12. The method of claim 11,
In the step of removing the metal paste,
And removing only the metal paste formed on the cavity, excluding the metal paste formed on the opening.
10. The method of claim 9,
After the step of laminating the second insulating layer,
Further comprising forming a first via in the second insulating layer and a second via in communication with the pad.
14. The method of claim 13,
Depositing a third insulating layer on the second insulating layer; And
Further comprising forming a third via in the third insulating layer, the third via being connected to at least one of the first via and the second via in the third insulating layer.
10. The method of claim 9,
The cavity is formed in a plurality of,
The plurality of pads are formed,
Wherein at least one of the plurality of pads is exposed by the plurality of cavities.
10. The method of claim 9,
Before the step of laminating the second insulating layer,
Further comprising forming a circuit on the first insulating layer,
In the step of laminating the second insulating layer,
And the second insulating layer covers the pad and the circuit.

Images