KR20190043342A - Printed circuit board and package substrate comprising same - Google Patents

Abstract

According to an embodiment of the present invention, a printed circuit board comprises: a first insulating layer; an electronic component arranged in the first insulating layer; a first pattern unit arranged on at least one surface of the first insulating layer; a second insulating layer arranged on upper and lower surfaces of the first insulating layer; a second pattern unit arranged on at least one surface of the second insulating layer; and a first via passing through the second insulating layer and connecting a terminal of the electronic component and the second pattern unit. The first pattern unit includes a first circuit pattern surrounding the first via at a position separated from the first via on the first insulating layer.

Description

[0001] DESCRIPTION [0002] PRINTED CIRCUIT BOARD AND PACKAGE SUBSTRATE COMPRISING SAME [0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, and more particularly to a printed circuit board with an embedded electronic component.

BACKGROUND ART With the miniaturization of electronic devices, electronic components include many functions or miniaturized sizes.

Particularly, in order to reduce the thickness of a portable terminal such as a cellular phone or a portable computer, a reduction in the thickness of components mounted thereon is highly desired. In order to miniaturize parts, there is a growing demand for reducing the thickness of a component package, and there is an increasing demand to implement a high performance by mounting a large number of integrated circuit chips for a multifunctionality in one component package. To this end, development of a component package technology such as a chip-embedded printed circuit board in which a chip is embedded between upper and lower printed circuit boards has been developed. The chip embedded printed circuit board technology can reduce the size of the whole package parts by incorporating a chip between the boards and improve the high frequency characteristics by increasing the mounting density of the components, thereby improving the electrical characteristics .

The electronic component built-in type printed circuit board includes a core substrate, a cavity on which the electronic component is to be placed, an electronic component inserted into the cavity, and an insulating layer pressed by the electronic component Thereby manufacturing a printed circuit board (PCB) containing the electronic parts.

After the electronic component is embedded, the electronic component is drilled for electrical connection between the terminal of the electronic component and an external circuit pattern, a cuplating process on an exposed substrate surface and an image transfer process A circuit pattern formation process is performed through the through hole.

Meanwhile, in the conventional printed circuit board, the cavity is processed by using a router or a laser on the core substrate, and the manufacturing process and cost of the cavity are increased.

In addition, according to the related art, there is a problem that a core substrate is used as a substrate on which the electronic component is embedded, and it is difficult to realize a fine pattern according to use of the core substrate.

In addition, according to the related art, a cavity insulating layer made of resin is formed in the cavity of the core substrate, bulge, dell, and panel warpage due to mismatch in thermal expansion coefficient between the core substrate and the cavity insulating layer occur , The problem of thickness irregularity due to the resin shortage occurs.

In the embodiment according to the present invention, a new printed circuit board with built-in electronic component is provided.

Further, in the embodiment according to the present invention, an electronic part-embedded printed circuit board not including a cavity is provided.

In addition, according to the embodiment of the present invention, it is possible to provide an electronic component-embedded printed circuit board capable of efficiently dissipating heat generated in an electronic component through a heat dissipation pattern.

According to another aspect of the present invention, there is provided an electronic component-embedded printed circuit board capable of improving the alignment of vias by forming a via alignment pattern around a via connected to a terminal of an electronic component.

It is to be understood that the technical objectives to be achieved by the embodiments are not limited to the technical matters mentioned above and that other technical subjects not mentioned are apparent to those skilled in the art to which the embodiments proposed from the following description belong, It can be understood.

A printed circuit board according to an embodiment includes a first insulating layer; An electronic component disposed in the first insulating layer; A first pattern portion disposed on at least one surface of the first insulating layer; A second insulating layer disposed on upper and lower surfaces of the first insulating layer; A second pattern portion disposed on at least one surface of the second insulating layer; And a first via passing through the second insulating layer and connecting the terminal of the electronic component to the second pattern portion, wherein the first pattern portion is formed on the first insulating layer so as to be spaced apart from the first via, And a first circuit pattern surrounding the periphery of the first via at a location.

The first insulating layer may include a first insulating part surrounding the electronic part and a second insulating part disposed on the first insulating part so as to cover the terminal of the electronic part, Is disposed on the second insulating part.

The first circuit pattern has an opening disposed on an upper surface of the second insulating part overlapping with the electronic component in the vertical direction and opening an area vertically overlapping with the terminal of the electronic component.

The first via may include a first via part disposed in the second insulating layer and a second via part disposed in the second insulating part of the first insulating layer.

Further, the electronic component includes a plurality of terminals, and the first circuit pattern surrounds the periphery of each of the plurality of first vias connected to the plurality of terminals, respectively.

In addition, the first circuit pattern has a single closed curve shape surrounding the periphery of the first via.

The first circuit pattern may include a first opening disposed in a central region and opening a region overlapping with the terminal of the electronic component in a vertical direction, and a second opening disposed in the edge region, As shown in Fig.

The first pattern portion may include a second circuit pattern disposed on the lower surface of the first insulating part, a third circuit pattern disposed on the upper surface of the second insulating part, and a second circuit pattern disposed on the first insulating part, And a second via portion connecting the second and third circuit patterns, wherein the first via portion and the second via portion are electrically connected to each other via the first via portion and the second via portion, , The first insulating part, and the second insulating part.

The second insulating part is an adhesive layer of the electronic component.

The first pattern part may further include a fourth circuit pattern disposed on an entire surface of the lower surface of the first insulating part that is vertically overlapped with the electronic component, A plurality of fifth circuit patterns arranged in a region of the lower surface of the second insulating layer which is vertically overlapped with the fourth circuit pattern, and a plurality of fifth circuit patterns arranged through the second insulating layer, And a third via including a plurality of via parts connecting the plurality of fifth circuit patterns.

The first insulating part includes a photocurable resin, and a plurality of electronic parts are disposed in the first insulating part, and the side surfaces of the plurality of electronic parts and the side surface of the second via are electrically connected to the light- And is in direct contact with one of the first insulating parts including the resin.

According to another aspect of the present invention, there is provided a package substrate comprising: a first insulating layer including a first insulating part and a second insulating part disposed on the first insulating part; A first electronic component disposed in the first insulating layer; A first pattern part disposed on a lower surface of the first insulating part and on an upper surface of the second insulating part; A second insulating layer including a third insulating part disposed on the lower surface of the first insulating part and a fourth insulating part disposed on the upper surface of the second insulating part; A second pattern part disposed on a lower surface of the third insulating part and on an upper surface of the fourth insulating part; A first via disposed to penetrate the fourth insulating part and the second insulating part, the first via connecting the terminal of the electronic part and the second pattern part; A protective layer disposed on the fourth insulating part and having a first opening exposing at least a part of a surface of the second pattern portion; An adhesive member disposed on the second pattern portion exposed through the opening of the protective layer; A second electronic component disposed on the adhesive member; And a molding part disposed on the protection layer so as to cover the second electronic part, wherein the first pattern part is disposed on an upper surface of the second insulating part overlapping with the first electronic part in a vertical direction, And a first circuit pattern having a second opening for opening a region overlapping vertically with the terminals of one electronic component.

In addition, the first electronic component includes an active element, and the second electronic component includes a passive element.

According to the embodiment of the present invention, it is possible to omit the step of forming the cavity in the insulating layer by forming the insulating layer after attaching the electronic parts on the carrier board, thereby shortening the cavity processing time and the degree of freedom in designing .

In addition, according to the embodiment of the present invention, it is possible to remove the cavity insulating layer to be disposed in the cavity in which the electronic component is embedded by using the resin, and to solve the reliability problem due to the resin shortage or the mismatch of the thermal expansion coefficient .

Further, according to the embodiment of the present invention, by inserting an electronic component using a low-priced photo-curable material not containing glass fibers, a via or circuit pattern formed in the insulating layer of the photo-curable material can be miniaturized.

In addition, according to the embodiment of the present invention, by forming a circuit pattern surrounding the vias around the vias connected to the electronic components, the alignment of the vias using the circuit patterns can be improved.

In addition, according to the embodiment of the present invention, the degree of freedom of the thickness of the insulating layer disposed at the portion opposite to the terminal of the electronic component can be secured, and the degree of freedom of design and heat dissipation property of the heat radiation pattern can be improved .

1 is a view illustrating a structure of a printed circuit board according to an embodiment of the present invention.
Fig. 2 is a view showing more specifically the portion A in Fig.
FIGS. 3 to 12 are views showing the manufacturing method of the printed circuit board 100 shown in FIG. 1 in the order of processes.
13 is a view for explaining a modified example of the 1-2 circuit pattern shown in Fig.
Figs. 14 and 15 are views for explaining still another modification of the circuit pattern 1-2 shown in Fig.
16 is a view illustrating a printed circuit board according to a second embodiment of the present invention.
17 is a view illustrating a printed circuit board according to a third embodiment of the present invention.
18 is a view illustrating a printed circuit board according to a fourth embodiment of the present invention.
19 is a view showing a package substrate according to an embodiment of the present invention.

Hereinafter, the configuration and operation according to the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same reference numerals denote the same elements regardless of the reference numerals, and redundant description thereof will be omitted. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure is formed "on" or "under" a substrate, each layer The terms " on " and " under " encompass both being formed "directly" or "indirectly" The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size. Hereinafter, embodiments will be described with reference to the accompanying drawings.

FIG. 1 is a view showing a structure of a printed circuit board according to an embodiment of the present invention, and FIG. 2 is a view showing a more detailed part A of FIG.

1 and 2, a printed circuit board 100 according to an embodiment of the present invention includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 150, The second via pattern 130, the second circuit pattern 160, the first via V1, the second via V2, the third via V3, the fourth via V4 and the electronic component 170.

The printed circuit board 100 can express the circuit pattern of the electric wiring connecting the electronic parts on the basis of the circuit design with wiring diagrams and reproduce the electric conductor on the insulating material. In addition, the printed circuit board 100 can embed electronic components and form circuit patterns for electrically connecting them, and mechanically fix components other than the electronic connection function of the electronic components.

The first insulating layer 110 may be a supporting substrate of a printed circuit board 100 on which a single circuit pattern is formed, It can mean area.

Preferably, the printed circuit board 100 has a four-layer structure, whereby the printed circuit board 100 largely comprises three layers of insulating layers.

The first insulating layer 110 is a central insulating layer of the printed circuit board 100 and is a core insulating layer of a conventional printed circuit board. The first insulating layer 110 and the second insulating layer 120 constitute the central insulating layer, and the first insulating layer 110 and The electronic component 170 is embedded in the second insulating layer 120.

The first insulating layer 110 covers the electronic component 170 and allows the electronic component 170 to be fixed therein and the second insulating layer 120 covers the electronic component 170 And the terminal 175 of the battery pack 200 is covered. The second insulating layer 120 may be an adhesive insulating layer for fixing and adhering the electronic component 170 in the manufacturing process of the printed circuit board 100.

Meanwhile, the first insulating layer 110 includes a photocurable resin. Preferably, the conventional central insulating layer includes an epoxy resin, a glass fiber, a silicon filler (Si filler), and a hardener. Thus, in the conventional central insulating layer, it is difficult to miniaturize a circuit pattern formed on the surface or vias penetrating both surfaces.

However, in the present invention, the first insulating layer 110 includes a photocurable resin instead of a core insulating layer containing the above-described material, thereby achieving miniaturization of the circuit pattern and vias.

For this, the first insulating layer 110 may include an epoxy resin, a photo initiator, a silicon filler, and a hardener.

In addition, an electronic component 170 is disposed in the first insulating layer 110. At this time, the first insulating layer 110 does not include a cavity into which the electronic component 170 is inserted.

That is, conventionally, after the cavity is formed on the central insulating layer, the electronic component is inserted, thereby forming a separate cavity insulating layer filling the cavity.

However, in the present invention, after the electronic component 170 is formed first, the first insulating layer 110 is formed using the photocurable resin to remove a cavity existing in the first insulating layer 110 .

Further, conventionally, a separate cavity insulating layer surrounds the periphery of the electronic component, so that the insulating material in the area where the via is formed and the insulating material surrounding the electronic part are different from each other.

However, in the present invention, the first insulating layer 110 surrounds the electronic component 170, and vias can be formed on the first insulating layer 110.

A second insulating layer 120 is disposed on the first insulating layer 110. In the present invention, the first insulating layer 110 and the second insulating layer 120 form a central insulating layer. The second insulating layer 120 may be an adhesive insulating layer of the electronic component 170 disposed on the first insulating layer 110.

The second insulating layer 120 may have an insulating function and may have adhesiveness for bonding the electronic component 170. The second insulating layer 120 may be formed of a nonconductive resin or a film having an insulating function. In addition, the second insulating layer 120 may be a polymer adhesive film, and may preferably be a nonconductive polymer adhesive film including a photo-curing resin.

Electronic components (170) are disposed in the first insulating layer (110) and the second insulating layer (120). A part of the electronic component 170 may be disposed in the first insulating layer 110 and a remaining portion may be disposed in the second insulating layer 120. The body of the electronic component 170 may be disposed on the first insulating layer 110 and the terminal 175 of the electronic component 170 may be disposed on the second insulating layer 120. [ have.

The electronic component 170 disposed in the first insulating layer 110 and the second insulating layer 120 may be any of electronic components such as various devices. The device may include any one of an active device and a passive device.

The active element refers to a device that positively uses a nonlinear portion, and the passive device refers to a device that does not use a nonlinear characteristic even if both linear and nonlinear characteristics exist. The passive element may include a transistor, an IC semiconductor chip, and the passive element may include a capacitor, a resistor, and an inductor. The passive element is mounted on a substrate together with a conventional semiconductor package in order to increase a signal processing speed of a semiconductor chip which is an active element, perform a filtering function, and the like.

Preferably, the electronic component may include a passive element formed by a structure in which an active element (not shown) having a terminal on one side and a terminal surround the side surface of the body of the electronic component 170.

The electronic component 170 of the present invention is composed of active elements, and is mounted in the first insulating layer 110 and the second insulating layer 120 by a flip chip bonding method. In other words, the terminal 175 of the electronic component 170 is not connected to the circuit pattern through a separate connecting member (for example, a wire) but has a structure directly connected to the circuit pattern.

A first circuit pattern 130 is disposed on the upper surface of the second insulating layer 120 and a lower surface of the first insulating layer 110, respectively. Preferably, the first circuit pattern 130 is disposed on at least one side of the central insulating layer in which the electronic component 170 is embedded.

The first circuit pattern 130 may include at least one metal selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) / RTI > material. The first circuit pattern 130 may include at least one selected from the group consisting of Au, Ag, Pt, Ti, Sn, Cu, And may be formed of a paste or a solder paste containing a metal material.

The first circuit pattern 130 may be formed by a conventional process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process ) Method, and a detailed description thereof is omitted here.

The first circuit pattern 130 may be divided into a first circuit pattern and a second circuit pattern according to functions. The first 1-1 circuit pattern serves as a wiring for signal transmission and the 1-2 circuit pattern 140 is used to align the fourth vias V4 at positions where the fourth vias V4 are formed .

To this end, the 1-2 circuit pattern 140 has an opening 145. That is, the first circuit pattern 140 has an opening 145 for inserting the fourth vias V4 therein. Accordingly, the 1-2 circuit pattern 140 is disposed so as to surround the fourth vias V4 as the fourth vias V4 are disposed in the openings 145. As shown in FIG.

That is, the first-second circuit pattern 140 includes the opening 145 therein and guides the fourth vias V4 through the opening 145 to be formed at a predetermined position. Accordingly, the 1-2 circuit pattern 140 may be disposed so as to surround the fourth vias V4 at a position spaced apart from the fourth vias V4 by a predetermined distance in the longitudinal direction.

2, the first and second circuit patterns 140 are formed on both surfaces of the first insulating layer 120 and the second insulating layer 120, (Not shown).

The first circuit pattern 140 may have a horizontal cross-sectional shape corresponding to a horizontal cross-sectional shape of the fourth vias V4. In other words, the horizontal cross-sectional shape of the fourth via V4 has a circular shape. Therefore, the first-second circuit pattern 140 may have a circular cross-sectional shape corresponding to the fourth vias V4.

That is, the 1-2 circuit pattern 140 may have a circular closed shape with a central portion opened.

The 1-2 circuit pattern 140 may be disposed on the second insulating layer 120 to correspond to the number of terminals 175 of the electronic component 170. That is, when the number of terminals 175 of the electronic component 170 is four, the first to fourth circuit patterns 140 may be disposed on the second insulating layer 120 at a predetermined interval . However, this is only an example, and the number of the terminals 175 and the number of the first-second circuit patterns 140 may increase or decrease depending on the embodiment.

The 1-2 circuit pattern 130 surrounds the area where the fourth vias V4 are to be formed by a metal material such as copper. Accordingly, in the process of forming the fourth vias V4, the fourth vias V4 can be formed at a predetermined position without being tilted.

A first via (V1) is formed in the first insulating layer (110) and the second insulating layer (120). The first vias V1 electrically connect the first insulating layer 110 disposed on the lower surface of the first insulating layer 110 and the surface of the second insulating layer 120, respectively. The first via V1 may include a first via part disposed in the first insulating layer 110 and a second via part disposed in the second insulating layer 120. [ The thickness of the second via part may be smaller than the thickness of the first via part. In other words, the thickness of the first insulating layer 110 may be greater than the thickness of the second insulating layer 120.

The first via V1 may be formed by filling a conductive material into the through hole (not shown) passing through the first insulating layer 110 and the second insulating layer 120.

The through-hole may be formed by any one of mechanical, laser, and chemical processing.

When the through holes are formed by machining, a method such as milling, drilling, and routing may be used. In the case where the through holes are formed by laser machining, UV or CO ₂ laser may be used In case of being formed by chemical processing, the first insulating layer 110 and the second insulating layer 120 may be opened using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method in which a part of a material is melted and evaporated by concentrating optical energy on the surface to take a desired shape, and complicated formation by a computer program can be easily processed. Difficult composite materials can be processed.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide range of thickness that can be processed.

As the laser processing drill, YAG (Yttrium Aluminum Garnet) laser, CO ₂ laser or ultraviolet (UV) laser is preferably used. The YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser capable of processing only the insulating layer.

When the through hole is formed, the first via (V1) is formed by filling the inside of the through hole with a conductive material. The conductive material forming the first via V1 is any one material selected from among copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium The conductive material filling can be performed by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting and dispensing, or a combination thereof. have.

A third insulating layer 150 is disposed on the upper surface of the second insulating layer 120 and the lower surface of the first insulating layer 110 to cover the first circuit pattern 130. The third insulating layer 150 may include an upper insulating layer disposed on the second insulating layer 120 and a lower insulating layer disposed under the first insulating layer 110.

A second circuit pattern 160 is disposed on the surface of the third insulating layer 150.

In the third insulating layer 150, a second via V2, a third via V3, and a fourth via V4 are disposed.

The second via (V2) is formed through the upper insulating layer, thereby forming a first circuit pattern (130) disposed on the second insulating layer (120) and a second circuit pattern (Not shown).

The third vias V3 may be formed through the lower insulating layer and may include a first circuit pattern 130 disposed below the first insulating layer 110 and a second circuit pattern 130 disposed below the lower insulating layer. The second circuit pattern 160 is electrically connected.

The fourth via (V4) is formed through the upper insulating layer. In other words, the fourth vias V4 are formed through the third insulating layer 150 disposed on the second insulating layer 120. [ In addition, a part of the fourth via V4 is disposed in the second insulating layer 120.

In other words, a part of the fourth via V4 is arranged to pass through the upper insulating layer, and the remaining part is disposed in the second insulating layer 120 and connected to the terminal 175 of the electronic component 170 do.

The fourth vias V4 are disposed in the openings 145 of the 1-2 circuit pattern 140. [ In other words, a part of the fourth via V4 disposed in the upper insulating layer is disposed in the opening 145 of the 1-2 circuit pattern 140.

At this time, the fourth vias V4 are formed by laser processing the upper insulating layer 120 and the second insulating layer 120 in the state that the 1-2 circuit patterns 140 are formed, And then filled. At this time, the laser is preferably a CO2 laser. That is, in the state that the 1-2 circuit pattern 140 is formed, a part of the through-hole is formed in the opening 145 of the 1-2 circuit pattern 140. At this time, the 1-2 circuit pattern 140 has a thickness of at least 5 탆 or more. The CO2 laser can stably penetrate through holes for the fourth vias V4 only in the openings 145 without damaging the 1-2 circuit patterns 140 having a thickness of 5 mu m or more .

As described above, according to the embodiment of the present invention, it is possible to omit the step of forming the cavity in the insulating layer by forming the insulating layer after attaching the electronic parts on the carrier board. As a result, The degree of design freedom can be secured.

In addition, according to the embodiment of the present invention, it is possible to remove the cavity insulating layer to be disposed in the cavity in which the electronic component is embedded by using the resin, and to solve the reliability problem due to the resin shortage or the mismatch of the thermal expansion coefficient .

Further, according to the embodiment of the present invention, by inserting an electronic component using a low-priced photo-curable material not containing glass fibers, a via or circuit pattern formed in the insulating layer of the photo-curable material can be miniaturized.

In addition, according to the embodiment of the present invention, by forming a circuit pattern surrounding the vias around the vias connected to the electronic components, the alignment of the vias using the circuit patterns can be improved.

Hereinafter, a method of manufacturing the printed circuit board 100 shown in FIG. 1 will be described with reference to the accompanying drawings.

FIGS. 3 to 12 are views showing the manufacturing method of the printed circuit board 100 shown in FIG. 1 in the order of processes.

Referring to FIG. 3, a carrier board C is prepared, and a metal layer 135 is formed on the prepared carrier board C. Preferably, the carrier board C may include the metal layer 135. The metal layer 135 may later be used to form the first circuit pattern 130 of the printed circuit board 100.

A second insulating layer 120 is formed on the metal layer 135.

The second insulating layer 120 may have an insulating function and may have adhesiveness for bonding the electronic component 170. The second insulating layer 120 may be formed of a nonconductive resin or a film having an insulating function. In addition, the second insulating layer 120 may be a polymer adhesive film, and may preferably be a nonconductive polymer adhesive film including a photo-curing resin.

A guide circuit (not shown) may be formed on the carrier board C including the metal layer 135 before the second insulating layer 120 is formed. The guide circuit may be formed in a dummy region of the metal layer 135. The guide circuit may be formed to easily separate the carrier board C from the metal layer 135. [ The guide circuit may be formed through the metal layer 135.

The second insulating layer 120 may have a thickness ranging from 2 탆 to 10 탆 and may be disposed on the metal layer 135.

Next, referring to FIG. 4, an electronic component 170 is attached to the second insulating layer 120. The electronic component 170 may be fixed on the second insulating layer 120 having adhesiveness. At this time, a part of the electronic component 170 may be disposed in the second insulating layer 120. That is, at least a part of the terminal 175 of the electronic component 170 may be disposed in the second insulating layer 120.

Referring to FIG. 5, a first insulating layer 110 and a metal layer 135 are formed on the second insulating layer 120 to cover the electronic component 170.

The first insulating layer 110 and the metal layer 135 may be formed by arranging the first insulating layer 110 and the metal layer 135 on the second insulating layer 120, And pressing process is performed.

Meanwhile, the first insulating layer 110 includes a photocurable resin. Preferably, the conventional central insulating layer includes an epoxy resin, a glass fiber, a silicon filler (Si filler), and a hardener. Thus, in the conventional central insulating layer, it is difficult to miniaturize a circuit pattern formed on the surface or vias penetrating both surfaces.

However, in the present invention, the first insulating layer 110 includes a photocurable resin instead of a core insulating layer containing the above-described material, thereby achieving miniaturization of the circuit pattern and vias.

For this, the first insulating layer 110 may include an epoxy resin, a photo initiator, a silicon filler, and a hardener. In addition, the first insulating layer 110 is formed after the electronic component 170 is mounted. Therefore, the first insulating layer 110 does not include a cavity. That is, conventionally, after the cavity is formed on the central insulating layer, the electronic component is inserted, thereby forming a separate cavity insulating layer filling the cavity. On the other hand, in the present invention, the first insulating layer 110 is formed by using the photocurable resin after the electronic component 170 is formed first, thereby forming a cavity existing in the first insulating layer 110 Can be deleted.

In addition, in the present invention, the first insulating layer 110 may be formed while the first insulating layer 110 surrounds the electronic component 170, and a cavity insulating Delete the layer.

Next, as shown in FIG. 6, when the first insulating layer 110 is formed, the carrier board C used for attaching the electronic component 170 is removed. The carrier board C can be stably separated from the metal layer 135 through the guide circuit.

When the carrier board C is removed, the substrate manufactured in FIG. 5 is turned upside down, and then the next step is performed.

7, at least one first through hole V1 is formed in the metal layer 135, the first insulating layer 110, and the second insulating layer 120. Referring to FIG. The first through hole V1 may be formed by any one of mechanical, laser, and chemical processing.

When the first through hole is formed by machining, a method such as milling, drilling, and routing may be used. In the case where the first through hole is formed by laser machining, a UV or CO ₂ laser And when it is formed by chemical processing, the first insulating layer 110 and the second insulating layer 120 may be opened by using a chemical containing aminosilane, ketone, or the like.

On the other hand, the processing by the laser is a cutting method in which a part of a material is melted and evaporated by concentrating optical energy on the surface to take a desired shape, and complicated formation by a computer program can be easily processed. Difficult composite materials can be processed.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide range of thickness that can be processed.

As the laser processing drill, YAG (Yttrium Aluminum Garnet) laser, CO ₂ laser or ultraviolet (UV) laser is preferably used. The YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser capable of processing only the insulating layer.

Next, as shown in FIG. 8, when the first through hole VH1 is formed, the first via hole VH1 is filled with a conductive material to form the first via V1. The conductive material forming the first via V1 is any one material selected from among copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium The conductive material filling can be performed by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting and dispensing, or a combination thereof. have.

The metal layer 135 is etched to form a first circuit pattern 130 on the upper surface of the second insulating layer 120 and a lower surface of the first insulating layer 110, respectively. At this time, the first circuit pattern 130 includes the 1-1 circuit pattern and the 1-2 circuit pattern 140 as described above.

Next, as shown in FIG. 9, an opening 145 is formed in the 1-2 circuit pattern 140 of the first circuit pattern 130. The position of the opening 145 may be determined according to the position of the terminal 175 of the electronic component 170. In other words, the opening 145 can open the surface of the second insulating layer 120 that is vertically overlapped with the terminal 175 of the electronic component 170 disposed in the first insulating layer 110 have. Preferably, the width of the opening 145 may be larger than the width of the overlapped region (corresponding to the width of the terminal).

Therefore, the first circuit pattern 130 may have a single closed curve shape in which an opening 145 is formed at the center.

10, a third insulating layer 150 and a metal layer 165 are disposed on the upper surface of the second insulating layer 120 and the lower surface of the first insulating layer 110, respectively, Proceed with the process. An upper insulating layer covering the first circuit pattern 130 and the first circuit pattern 140 on the second insulating layer 120; A third insulating layer 150 including a lower insulating layer covering the pattern 130 is formed.

Next, as shown in FIG. 11, a second via hole VH2 is formed in the upper insulating layer, and a third via hole VH3 is formed in the lower insulating layer.

A fourth via hole (VH4) is formed in the upper insulating layer and the second insulating layer (120).

Next, as shown in FIG. 12, the second to fourth via holes VH2, VH3, and VH4 are filled with a conductive material to form a second via V2, a third via V3, and a fourth via V4). The metal layer 165 is etched to form a second circuit pattern 160 on the surface of the third insulating layer 150.

Meanwhile, the fourth vias V4 are formed through the upper insulating layer. In other words, the fourth vias V4 are formed through the third insulating layer 150 disposed on the second insulating layer 120. [ In addition, a part of the fourth via V4 is disposed in the second insulating layer 120.

In other words, a part of the fourth via V4 is arranged to pass through the upper insulating layer, and the remaining part is disposed in the second insulating layer 120 and connected to the terminal 175 of the electronic component 170 do.

The fourth vias V4 are disposed in the openings 145 of the 1-2 circuit pattern 140. [ In other words, a part of the fourth via V4 disposed in the upper insulating layer is disposed in the opening 145 of the 1-2 circuit pattern 140.

At this time, the fourth vias V4 are formed by laser processing the upper insulating layer 120 and the second insulating layer 120 in the state that the 1-2 circuit patterns 140 are formed, And then filled. At this time, the laser is preferably a CO2 laser. That is, in the state that the 1-2 circuit pattern 140 is formed, a part of the through-hole is formed in the opening 145 of the 1-2 circuit pattern 140. At this time, the 1-2 circuit pattern 140 has a thickness of at least 5 탆 or more. The CO2 laser can stably penetrate through holes for the fourth vias V4 only in the openings 145 without damaging the 1-2 circuit patterns 140 having a thickness of 5 mu m or more .

According to the embodiment of the present invention, it is possible to omit the step of forming the cavity in the insulating layer by forming the insulating layer after attaching the electronic parts on the carrier board, thereby shortening the cavity processing time and the degree of freedom in designing .

In addition, according to the embodiment of the present invention, it is possible to remove the cavity insulating layer to be disposed in the cavity in which the electronic component is embedded by using the resin, and to solve the reliability problem due to the resin shortage or the mismatch of the thermal expansion coefficient .

Further, according to the embodiment of the present invention, by inserting an electronic component using a low-priced photo-curable material not containing glass fibers, a via or circuit pattern formed in the insulating layer of the photo-curable material can be miniaturized.

In addition, according to the embodiment of the present invention, by forming a circuit pattern surrounding the vias around the vias connected to the electronic components, the alignment of the vias using the circuit patterns can be improved.

13 is a view for explaining a modified example of the 1-2 circuit pattern shown in Fig.

Referring to FIG. 1, the 1-2 circuit pattern 140 has a ring shape and a single closed curve shape. However, this is only an example, and the 1-2 circuit pattern 140 may be formed of a single closed curve of various shapes other than the ring shape.

That is, as shown in FIG. 13A, the 1-2 circuit pattern 140 may be formed as a single closed curve having a rectangular shape. Alternatively, as shown in FIG. 13 (b), the 1-2 circuit pattern 140 may be formed as a single closed curve of a rhombus shape. Alternatively, as shown in FIG. 13C, the 1-2 circuit pattern 140 may be formed as a single closed curve of a triangular shape.

In addition to the shapes shown in the drawings, the first and second circuit patterns 140 may be formed into various shapes such as an ellipse shape, a fan shape, and a star shape.

Figs. 14 and 15 are views for explaining still another modification of the circuit pattern 1-2 shown in Fig.

In FIG. 1, the 1-2 circuit pattern 140 has a single closed curve shape. However, the 1-2 circuit pattern 140 may have a non-single closed curve shape rather than a single closed curve shape. In other words, the 1-2 circuit pattern 140 may include a first opening 145a and a second opening 145b.

The first opening 145a is disposed in a central region of the first-second circuit pattern 140 to open a pattern of a region in which the fourth vias V4 are to be formed. In addition, the second opening 145b is disposed in an edge area of the first-second circuit pattern 140. At this time, the second openings 145b may be formed in a single number, or may be formed in a plurality of different ways.

That is, although the second opening 145b is shown in FIG. 14 as being two, the second opening 145b may include only one of the two. At this time, the second opening 145b communicates with the first opening 145a.

In addition, when the second openings 145b are formed in two, the first circuit pattern 140 includes a first pattern 140a surrounding one side of the fourth vias V4, And a second pattern portion 140b physically separated from the first pattern portion 140a and disposed to surround the other side of the fourth via V4.

Also, as shown in FIG. 15, the second opening 145b may be formed in four, not two. In addition, the 1-2 circuit pattern 140 can be modified into various shapes

That is, as shown in FIG. 15A, the second opening 145b may be formed of four, and the first and second circuit patterns 140 may have a circular shape.

Alternatively, as shown in FIG. 15 (b), the second opening 145b may be formed in four, and the first and second circuit patterns 140 may have a rectangular shape.

16 is a view illustrating a printed circuit board according to a second embodiment of the present invention.

16, the printed circuit board 100A includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 150, a first circuit pattern 130, a second circuit pattern A first via 160 and a second via 170. The first and second vias V1 and V2 and the third and fourth vias V4 and V1 and V2 are connected to the first and second electronic components 170 and 170B.

Hereinafter, the same reference numerals are assigned to the components substantially the same as those in Fig. 1 and the detailed description thereof will be omitted.

Referring to FIG. 16, a plurality of electronic parts are embedded in the first insulating layer 110. That is, the first electronic component 170A and the second electronic component 170B are embedded in the first insulation layer 110 at a predetermined interval.

That is, in the present invention, since the cavity is not included, a plurality of electronic components 170, rather than one electronic component, are disposed on the second insulating layer 120, So that a plurality of electronic parts 170 can be embedded in the first insulating layer.

In addition, the 1-2 circuit patterns 140 among the first circuit patterns 130 may be disposed at positions where the plurality of electronic components are arranged. That is, when each of the plurality of parts includes four terminals, the first 1-2 circuit pattern 140 may be formed in correspondence with the positions of the terminals of the plurality of parts.

17 is a view illustrating a printed circuit board according to a third embodiment of the present invention.

17, the printed circuit board 100A includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 150, a first circuit pattern 130, a second circuit pattern A second via V1, a second via V2, a third via V3, a fourth via V4 and an electronic component 170. The first via V1, the second via V2,

Hereinafter, the same reference numerals are assigned to the components substantially the same as those shown in Fig. 1 and the detailed description thereof will be omitted.

In the present invention, the first insulation layer 110 disposed at the center is formed of a photo-curable resin, and the thickness of the first insulation layer 110 can be reduced, thereby improving the degree of design freedom. Accordingly, in the present invention, a heat dissipation pad for improving heat dissipation characteristics may be formed on a surface opposite to a surface on which the terminals of the electronic component 170 are disposed.

The heat dissipation pad may include a heat dissipation pattern 130A and a heat dissipation via V5. The heat radiation pattern 130A may be any one of the first circuit patterns 130 disposed on the lower surface of the first insulation layer 110. Preferably, the heat dissipation pattern 130A is disposed on a region of the lower surface of the first insulation layer 110 that is vertically overlapped with the electronic component 170. The heat dissipation pattern 130A may transmit the heat of the electronic component 170 transmitted through the first insulation layer 110 to the lower portion.

For this purpose, the heat dissipation pattern 130A may be formed of a metal material having high thermal conductivity.

It is preferable that the plane area of the heat radiation pattern 130A is larger than the plane area of the electronic component 170. [

A heat radiation via V5 is disposed below the heat radiation pattern 130A. The heat radiation vias V5 may be vias located below the heat radiation patterns 130A among the third vias V3. A plurality of the heat radiation vias V5 may be formed.

At this time, the plurality of heat radiation vias V5 are all connected to one common heat radiation pattern 130A. That is, the heat dissipation pattern 130A receives heat generated from the electronic component 170. [ The heat dissipation via V5 branches the heat transferred to the heat dissipation pattern 130A into a plurality of paths and transmits the heat to the lower part.

Accordingly, the heat dissipation via V5 may include a plurality of heat dissipation vias V5 disposed at positions spaced apart from each other by a predetermined distance.

In addition, according to the embodiment of the present invention, the degree of freedom of the thickness of the insulating layer disposed at the portion opposite to the terminal of the electronic component can be secured, and the degree of freedom of design and heat dissipation property of the heat radiation pattern can be improved .

18 is a view illustrating a printed circuit board according to a fourth embodiment of the present invention.

18, the printed circuit board 100A includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 150, a first circuit pattern 130, a second circuit pattern A second via V1, a second via V2, a third via V3, a fourth via V4 and an electronic component 170. The first via V1, the second via V2,

Hereinafter, the same constituent elements as those in Fig. 1 which are substantially the same as those in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

In the present invention, the first insulation layer 110 disposed at the center is formed of a photo-curable resin, and the thickness of the first insulation layer 110 can be reduced, thereby improving the degree of design freedom. Accordingly, in the present invention, a heat dissipation pad for improving heat dissipation characteristics may be formed on a surface opposite to a surface on which the terminals of the electronic component 170 are disposed.

The heat dissipation pad may include a heat dissipation pattern 130A and a heat dissipation via V5. The heat radiation pattern 130A may be any one of the first circuit patterns 130 disposed on the lower surface of the first insulation layer 110. Preferably, the heat dissipation pattern 130A is disposed on a region of the lower surface of the first insulation layer 110 that is vertically overlapped with the electronic component 170. The heat dissipation pattern 130A may transmit the heat of the electronic component 170 transmitted through the first insulation layer 110 to the lower portion.

For this purpose, the heat dissipation pattern 130A may be formed of a metal material having high thermal conductivity.

It is preferable that the plane area of the heat radiation pattern 130A is larger than the plane area of the electronic component 170. [

A heat radiation via V5 is disposed below the heat radiation pattern 130A. The heat radiation vias V5 may be vias located below the heat radiation patterns 130A among the third vias V3. A plurality of the heat radiation vias V5 may be formed.

At this time, the plurality of heat radiation vias V5 are all connected to one common heat radiation pattern 130A. That is, the heat dissipation pattern 130A receives heat generated from the electronic component 170. [ The heat dissipation via V5 branches the heat transferred to the heat dissipation pattern 130A into a plurality of paths and transmits the heat to the lower part.

Accordingly, the heat dissipation via V5 may include a plurality of heat dissipation vias V5 disposed at positions spaced apart from each other by a predetermined distance.

In addition, according to the embodiment of the present invention, the degree of freedom of the thickness of the insulating layer disposed at the portion opposite to the terminal of the electronic component can be secured, and the degree of freedom of design and heat dissipation property of the heat radiation pattern can be improved .

On the other hand, FIG. 18 shows a structure of the second circuit pattern 120 disposed on the surface of the second insulating layer 120, which is substantially the same as the structure of the substrate shown in FIG. 17, (140) was removed.

 That is, the first insulating layer 110 in the present invention does not include a cavity but includes a photocurable resin.

Accordingly, the degree of freedom in thickness in the direction opposite to the direction in which the terminal of the electronic component is directed in the first insulating layer 110 can be ensured, thereby maximizing the heat dissipation characteristic through the heat dissipating pad and the heat dissipating via Can be improved. In other words, in the present invention, the above-mentioned effects can be achieved by forming the first insulating layer 110 with a photocurable resin while removing the cavity in the first insulating layer 110, The via patterning characteristics through the second circuit pattern 140 can be improved.

19 is a view showing a package substrate according to an embodiment of the present invention.

The package substrate includes a printed circuit board 100 shown in FIG. 1, a first protective layer 210 disposed on the printed circuit board 100, an adhesive member 230, a second electronic component 240, (250).

The printed circuit board 100 includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 150, a first circuit pattern 130, a second circuit pattern 130, A second via V1, a second via V2, a third via V3, a fourth via V4 and an electronic component 170. The first via V1, the second via V2,

The electronic component 170 disposed in the printed circuit board 100 may be a first electronic component 170 and a plurality of the first electronic components 170 may be disposed in the first insulating layer 110 have.

The first electronic component 170 may be an active component, as described above.

A second electronic component 240 is disposed on the printed circuit board 100. The second electronic component 240 may be disposed on the printed circuit board 100.

In order for the second electronic component 240 to be disposed, a protective layer is disposed on both sides of the printed circuit board 100. The protective layer may include a first passivation layer 230 disposed on an upper insulating layer of the printed circuit board 100 and having an opening exposing at least a portion of a surface of the second circuit pattern 160 have. The first passivation layer 210 exposes a region of the upper surface of the second circuit pattern 160 where the second electronic component 240 is to be disposed.

The protective layer may include a second protective layer 220 disposed below the lower insulating layer of the printed circuit board 100 and having an opening exposing at least a part of the surface of the second circuit pattern 160, . The second passivation layer 220 may be formed on the second circuit layer 220 where a separate adhesive paste (e.g., solder ball) for attachment to the external substrate is to be formed when the package substrate is attached to an external substrate And has an opening exposing the surface of the pattern 160.

The first and second protective layers 210 and 220 may be formed of one or more layers using one or more of SR (solder resist), oxide, and Au.

An adhesive member 230 is disposed on the exposed surface of the second circuit pattern 160 disposed on the upper insulating layer through the opening of the first passivation layer 210. The adhesive member 230 may be a solder paste.

The solder paste is an adhesive for fixing the second electronic component 240. Accordingly, the adhesive member 230, which may be composed of the solder paste, may be called an adhesive. The adhesive may be a conductive adhesive. That is, the second electronic component 240 is disposed on the second circuit pattern 160 in a flip chip manner. Therefore, it is preferable that the adhesive member 230 has conductivity.

The conductive adhesive is divided into an anisotropic conductive adhesive and an isotropic conductive adhesive. The conductive adhesive is basically composed of conductive particles such as Ni, Au / polymer, or Ag, and conductive particles such as thermosetting, thermoplastic, And a blend type insulating resin mixed with the two characteristics.

The second electronic component 240 is disposed on the adhesive member 230. The second electronic component 240 is preferably a passive component as described above.

The second electronic component 240 may be mounted on the second circuit pattern 160 by the adhesive member 230.

A molding part 250 is disposed on the first passivation layer.

The molding unit 250 covers the first protection layer, the adhesive member 230, and the second electronic component 240, which are disposed on the printed circuit board 100.

According to the embodiment of the present invention, it is possible to omit the step of forming the cavity in the insulating layer by forming the insulating layer after attaching the electronic parts on the carrier board, thereby shortening the cavity processing time and the degree of freedom in designing .

In addition, according to the embodiment of the present invention, it is possible to remove the cavity insulating layer to be disposed in the cavity in which the electronic component is embedded by using the resin, and to solve the reliability problem due to the resin shortage or the mismatch of the thermal expansion coefficient .

Further, according to the embodiment of the present invention, by inserting an electronic component using a low-priced photo-curable material not containing glass fibers, a via or circuit pattern formed in the insulating layer of the photo-curable material can be miniaturized.

In addition, according to the embodiment of the present invention, by forming a circuit pattern surrounding the vias around the vias connected to the electronic components, the alignment of the vias using the circuit patterns can be improved.

In addition, according to the embodiment of the present invention, the degree of freedom of the thickness of the insulating layer disposed at the portion opposite to the terminal of the electronic component can be secured, and the degree of freedom of design and heat dissipation property of the heat radiation pattern can be improved .

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (13)

A first insulating layer;
An electronic component disposed in the first insulating layer;
A first pattern portion disposed on at least one surface of the first insulating layer;
A second insulating layer disposed on upper and lower surfaces of the first insulating layer;
A second pattern portion disposed on at least one surface of the second insulating layer; And
And a first via penetrating the second insulating layer and connecting the terminal of the electronic component and the second pattern portion,
Wherein the first pattern portion comprises:
And a first circuit pattern surrounding the first via at a location spaced apart from the first via on the first insulating layer
Printed circuit board. The method according to claim 1,
Wherein the first insulating layer
A first insulating part surrounding the electronic part,
And a second insulating part disposed on the first insulating part so as to cover the terminal of the electronic part,
Wherein the first circuit pattern includes:
Disposed over the second insulating part
Printed circuit board. 3. The method of claim 2,
Wherein the first circuit pattern includes:
And an opening disposed on an upper surface of the second insulating part overlapping with the electronic part in the vertical direction and opening an area vertically overlapping with the terminal of the electronic part
Printed circuit board. 3. The method of claim 2,
Wherein the first via comprises:
A first via part disposed in the second insulating layer,
And a second via portion disposed within the second insulating portion of the first insulating layer
Printed circuit board. The method according to claim 1,
The electronic component includes:
A plurality of terminals,
Wherein the first circuit pattern includes:
A plurality of first vias connected to the plurality of terminals,
Printed circuit board. The method according to claim 1,
Wherein the first circuit pattern includes:
The first via having a shape of a single closed curve surrounding the periphery of the first via
Printed circuit board. 3. The method of claim 2,
Wherein the first circuit pattern includes:
A first opening disposed in the central region for opening a region overlapping with the terminal of the electronic component in the vertical direction,
And at least one second opening disposed in the edge region and communicating with the first opening,
Printed circuit board. 3. The method of claim 2,
Wherein the first pattern portion comprises:
A second circuit pattern disposed on a lower surface of the first insulating part,
A third circuit pattern disposed on an upper surface of the second insulating part,
Further comprising a second via portion connecting the second and third circuit patterns, the first via portion passing through the first insulating portion, and the second via portion passing through the second insulating portion,
Wherein the first via-part and the second via-
Disposed on an area superimposed in a vertical direction on the first insulating part and the second insulating part
Printed circuit board. 9. The method of claim 8,
Wherein the second insulating part comprises:
The adhesive layer of the electronic component
Printed circuit board. 9. The method of claim 8,
Wherein the first pattern portion comprises:
Further comprising a fourth circuit pattern disposed on an entire surface of the lower surface of the first insulating part that overlaps the electronic component vertically,
Wherein the second pattern portion comprises:
A plurality of fifth circuit patterns disposed on a lower surface of the second insulating layer disposed on a lower surface of the first insulating part in a region vertically overlapping with the fourth circuit pattern,
And a third via disposed through the second insulating layer and including a plurality of via parts connecting the fourth circuit pattern and the plurality of fifth circuit patterns,
Printed circuit board. 9. The method of claim 8,
Wherein the first insulating part comprises:
And a photocurable resin,
A plurality of electronic parts are disposed in the first insulating part,
The side surfaces of the plurality of electronic parts and the side surface of the second via,
And a second insulating part comprising a photocurable resin
Printed circuit board. A first insulating layer including a first insulating part and a second insulating part disposed on the first insulating part;
A first electronic component disposed in the first insulating layer;
A first pattern part disposed on a lower surface of the first insulating part and on an upper surface of the second insulating part;
A second insulating layer including a third insulating part disposed on the lower surface of the first insulating part and a fourth insulating part disposed on the upper surface of the second insulating part;
A second pattern part disposed on a lower surface of the third insulating part and on an upper surface of the fourth insulating part;
A first via disposed to penetrate the fourth insulating part and the second insulating part, the first via connecting the terminal of the electronic part and the second pattern part;
A protective layer disposed on the fourth insulating part and having a first opening exposing at least a part of a surface of the second pattern portion;
An adhesive member disposed on the second pattern portion exposed through the opening of the protective layer;
A second electronic component disposed on the adhesive member; And
And a molding part covering the second electronic part on the protection layer,
Wherein the first pattern portion comprises:
And a first circuit pattern disposed on an upper surface of the second insulating part overlapping with the first electronic component in a vertical direction and having a second opening that opens a region vertically overlapping with the terminal of the first electronic component
Package substrate. 13. The method of claim 12,
The first electronic component includes:
Includes an active element,
Wherein the second electronic component comprises:
Including passive components
Package substrate.

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