JP5992676B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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JP5992676B2
JP5992676B2 JP2011258116A JP2011258116A JP5992676B2 JP 5992676 B2 JP5992676 B2 JP 5992676B2 JP 2011258116 A JP2011258116 A JP 2011258116A JP 2011258116 A JP2011258116 A JP 2011258116A JP 5992676 B2 JP5992676 B2 JP 5992676B2
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semiconductor element
resist layer
solder resist
solder
mounting portion
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JP2013115145A (en
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州平 藤尾
州平 藤尾
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

本発明は、半導体集積回路素子等の半導体素子を搭載するための高密度配線基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a high-density wiring board for mounting a semiconductor element such as a semiconductor integrated circuit element.

近年、携帯型のゲーム機や通信機器に代表される電子機器の小型、高機能化が進む中、それらに使用される配線基板にも小型、高機能化が要求されるようになっている。このような要求に対し、例えば半導体集積回路素子等の半導体素子を搭載する配線基板の上面に、さらに別の電気基板が半導体素子を覆うようにして積載された、いわゆるＰｏＰ（Ｐａｃｋａｇｅ ｏｎ Ｐａｃｋａｇｅ）とよばれる複合構造の電子部品がある。   In recent years, as electronic devices typified by portable game machines and communication devices have become smaller and more functional, wiring boards used for them have been required to be smaller and more functional. In response to such a request, for example, a so-called PoP (Package on Package) in which another electric substrate is stacked on the upper surface of a wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted so as to cover the semiconductor element. There is an electronic component with a so-called composite structure.

このような電子部品において、半導体素子を搭載するための下側の配線基板は、その上面中央部に半導体素子を搭載するための半導体素子搭載部が形成されているとともに、この半導体素子搭載部を取り囲む上面外周部に上側の電気基板が搭載される電気基板搭載部を有している。そして、半導体素子搭載部には半導体素子の下面に設けた電極が半田バンプを介して接続される半導体素子接続パッドが、例えば縦横の並びの格子状の配列で形成されている。また、電気基板搭載部には電気基板の下面外周部に設けた接続端子が半田ボールを介して接続される電気基板接続パッドが、例えば枠状に並ぶ格子状の配列で形成されている。さらに、配線基板の上面には半導体素子接続パッドおよび電気基板接続パッドを露出させる開口部を有するソルダーレジスト層が被着されている。   In such an electronic component, the lower wiring board for mounting the semiconductor element has a semiconductor element mounting portion for mounting the semiconductor element formed at the center of the upper surface thereof. An electric board mounting portion on which the upper electric board is mounted is provided on the outer peripheral portion of the upper surface surrounding the upper surface. In the semiconductor element mounting portion, semiconductor element connection pads to which electrodes provided on the lower surface of the semiconductor element are connected via solder bumps are formed, for example, in a lattice-like arrangement in vertical and horizontal directions. In the electric board mounting portion, electric board connection pads to which connection terminals provided on the outer periphery of the lower surface of the electric board are connected via solder balls are formed in a grid-like arrangement, for example, in a frame shape. Further, a solder resist layer having an opening for exposing the semiconductor element connection pad and the electric substrate connection pad is deposited on the upper surface of the wiring board.

このような電子部品に用いられる配線基板上面に半導体素子を搭載するときには、半導体素子接続パッド上に、半田バンプを予め溶着しておき、その半田バンプ上に半導体素子の電極を載せた後、リフロー処理により接続する周知のフリップチップ法が好適に用いられる。なお、半田バンプ上に半導体素子の電極を載せる際には、半田バンプの頭頂部を例えば配線基板よりも大きな平坦なプレス面を有する平坦化装置によりプレスして予め平坦化しておくことが一般的に行なわれている。半田バンプの頭頂部を予め平坦化しておくことによって、半導体素子の電極を半田バンプ上に載せた際に電極が半田バンプ上から滑り落ちることを有効に防止して安定した状態で載せることができる。また半導体素子を搭載した後は、半導体素子と配線基板との隙間にアンダーフィルと呼ばれる封止樹脂を注入する。さらに、半導体素子が搭載された配線基板に電気基板を搭載するときには、電気基板の下面の接続パッドに半田ボールを予め溶着させておくとともに、配線基板の電気基板接続パッド上に、電気基板に溶着させた半田ボールを載せた後、リフロー処理により接続する方法が用いられる。   When mounting a semiconductor element on the upper surface of a wiring board used for such an electronic component, solder bumps are pre-welded on the semiconductor element connection pads, and electrodes of the semiconductor element are placed on the solder bumps, and then reflow is performed. A known flip chip method for connecting by processing is preferably used. When placing the electrodes of the semiconductor elements on the solder bumps, it is generally pre-planarized by pressing the top of the solder bumps with, for example, a flattening device having a flat press surface larger than the wiring board. Has been done. By flattening the tops of the solder bumps in advance, it is possible to effectively prevent the electrodes from sliding off the solder bumps when the electrodes of the semiconductor element are placed on the solder bumps. After mounting the semiconductor element, a sealing resin called an underfill is injected into the gap between the semiconductor element and the wiring board. Furthermore, when mounting an electric board on a wiring board on which a semiconductor element is mounted, solder balls are previously welded to connection pads on the lower surface of the electric board, and are welded to the electric board on the electric board connection pads of the wiring board. A method is used in which the solder balls are placed and then connected by reflow processing.

ところで、上述したように、半導体素子の電極と半導体素子接続パッドとを接続した後は、半導体素子と配線基板との間に樹脂を注入して封止することで半導体素子の電極や接続パッドを保護する。このとき、封止用の樹脂は注入の際に流動性を有することから、一部が搭載部からはみ出して配線基板上の周囲に広がった後に固着することがある。しかし、この樹脂が、搭載部周囲の電気基板接続パッドにまで到達して固着すると、電気基板の接続に支障をきたしてしまう。そこで、そのような支障を回避するため、電気基板搭載部におけるソルダーレジスト層の厚みを半導体素子搭載部におけるソルダーレジスト層の厚みよりも１０〜３０μｍ程度厚くして半導体素子搭載部を厚みの厚いソルダーレジスト層で囲繞することによりアンダーフィル樹脂の半導体素子搭載部の外側への広がりを防止する構造をとる場合がある。   By the way, as described above, after connecting the electrode of the semiconductor element and the semiconductor element connection pad, resin is injected between the semiconductor element and the wiring board to seal the electrode and connection pad of the semiconductor element. Protect. At this time, since the sealing resin has fluidity at the time of injection, the resin may be fixed after partially protruding from the mounting portion and spreading around the wiring board. However, if this resin reaches the electric board connection pad around the mounting portion and adheres, it will hinder the connection of the electric board. Therefore, in order to avoid such troubles, the thickness of the solder resist layer in the electric board mounting portion is made about 10 to 30 μm thicker than the thickness of the solder resist layer in the semiconductor element mounting portion to make the semiconductor element mounting portion thicker. There is a case in which the underfill resin is prevented from spreading outside the semiconductor element mounting portion by being surrounded by a resist layer.

ところが、上述のように半導体素子搭載部を厚みの厚いソルダーレジスト層で囲繞すると、半導体素子接続パッドに半田バンプを溶着させた際に、半田バンプの頭頂部が半導体素子搭載部周囲のソルダーレジスト層の上面から突出する高さがその分、低くなってしまう。すると半田バンプの頭頂部を平坦化する際に、平坦化装置の平坦なプレス面が半導体素子搭載部周囲の厚みの厚いソルダーレジスト層の上面に当ってしまい、半田バンプの頭頂部を十分に平坦化することが困難となる。半田バンプの頭頂部における平坦化が不十分であると、半導体素子の電極を半田バンプ上に載せた際に電極が半田バンプ上から滑り落ちる危険性が高くなり安定した状態で載せることができなくなる。その結果、半導体素子の電極と半導体素子接続パッドとを電気的に良好に接続することができないおそれがあった。   However, when the semiconductor element mounting portion is surrounded by a thick solder resist layer as described above, when the solder bump is welded to the semiconductor element connection pad, the top of the solder bump is the solder resist layer around the semiconductor element mounting portion. The height protruding from the upper surface of the plate will be reduced accordingly. Then, when flattening the top part of the solder bump, the flat press surface of the flattening device hits the upper surface of the thick solder resist layer around the semiconductor element mounting part, and the top part of the solder bump is sufficiently flat. It becomes difficult to make it. If the top of the solder bump is insufficiently flattened, there is a high risk that the electrode slips from the solder bump when the electrode of the semiconductor element is placed on the solder bump, and the solder bump cannot be placed in a stable state. As a result, there is a possibility that the electrode of the semiconductor element and the semiconductor element connection pad cannot be electrically connected well.

特開平６−２２４５４７号公報JP-A-6-224547

本発明は、半導体素子を搭載する半導体素子搭載部の周囲が厚みの厚いソルダーレジスト層で囲繞されている場合であっても、半導体素子接続パッドに溶着された半田バンプの頭頂部を十分に平坦化することができ、それにより半田バンプ上に半導体素子の電極を安定した状態で載せて半導体素子の電極と半導体素子接続パッドとを電気的に良好に接続することが可能な配線基板の製造方法を提供することを課題とする。   Even if the periphery of the semiconductor element mounting portion for mounting the semiconductor element is surrounded by a thick solder resist layer, the top of the solder bump welded to the semiconductor element connection pad is sufficiently flat. Circuit board manufacturing method capable of stably placing electrodes of a semiconductor element on a solder bump and electrically connecting the electrodes of the semiconductor element and the semiconductor element connection pads. It is an issue to provide.

本発明における配線基板の製造方法は、上面中央部に半導体素子が搭載される半導体素子搭載部を有する絶縁基板と、半導体素子搭載部に配設された複数の半導体素子接続パッドと、絶縁基板の上面に、前記半導体素子接続パッドの各々を個別に露出させる複数の第１の開口部を有するように被着された第１のソルダーレジスト層と、第１のソルダーレジスト層上に、半導体素子搭載部を囲繞するとともに複数の半導体素子接続パッドを一括して露出させる第２の開口部を有するようにして被着されており、半導体素子接続パッドの上面より高い上面を有する第２のソルダーレジスト層と、半導体素子接続パッド上に溶着されており、頭頂部が平坦化された半田バンプとを備える配線基板の製造方法であって、絶縁基板の上面に半導体素子接続パッドおよび第１および第２のソルダーレジスト層を形成する工程と、半導体素子接続パッド上に第２のソルダーレジスト層の上面よりも突出する高さの半田バンプを溶着する工程と、第２のソルダーレジスト層上および半田バンプ上に、第２のソルダーレジスト層を弾性変形で凹ませつつ半田バンプの頭頂部を塑性変形で押し潰すように押圧ローラーを転動させることにより頭頂部を、第１のソルダーレジスト層の上面より高い位置となるとともに第２のソルダーレジスト層の上面より低い位置となるように平坦化する工程とを行なうことを特徴とするものである。
A method of manufacturing a wiring board according to the present invention includes an insulating substrate having a semiconductor element mounting portion in which a semiconductor element is mounted at the center of the upper surface, a plurality of semiconductor element connection pads disposed in the semiconductor element mounting portion, and an insulating substrate. A first solder resist layer deposited on the upper surface so as to have a plurality of first openings that individually expose each of the semiconductor element connection pads, and a semiconductor element mounted on the first solder resist layer A second solder resist layer having a top surface higher than the top surface of the semiconductor element connection pad, and is attached so as to have a second opening surrounding the portion and exposing the plurality of semiconductor element connection pads at once And a solder bump which is welded onto the semiconductor element connection pad and the top of which is flattened. A step of forming a pad and first and second solder resist layers, a step of welding a solder bump having a height protruding from the upper surface of the second solder resist layer on the semiconductor element connection pad, and a second solder On the resist layer and the solder bump, the second solder resist layer is dented by elastic deformation, and the pressure roller is rolled so that the top of the solder bump is crushed by plastic deformation. And a step of flattening so as to be higher than the upper surface of the solder resist layer and lower than the upper surface of the second solder resist layer.

本発明の配線基板の製造方法によれば、押圧ローラーが半導体素子搭載部を囲繞する第２のソルダーレジスト層を弾性変形で凹ませつつ半田バンプの頭頂部を塑性変形で押し潰すように転動させることから、押圧ローラーが転動した後の第２のソルダーレジスト層は弾性力により転動前の高さに復元するとともに、半田バンプの頭頂部は平坦に塑性変形される。これにより、半田バンプの頭頂部を安定的に平坦化することができ、それにより半田バンプ上に半導体素子の電極を安定した状態で載せて半導体素子の電極と半導体素子接続パッドとを電気的に良好に接続することが可能な配線基板の製造方法を提供することができる。


According to the method for manufacturing a wiring board of the present invention, the pressing roller rolls so that the top of the solder bump is crushed by plastic deformation while the second solder resist layer surrounding the semiconductor element mounting portion is recessed by elastic deformation. Therefore, the second solder resist layer after the pressing roller rolls is restored to the height before rolling by the elastic force, and the top of the solder bump is plastically deformed flat. As a result, the top of the solder bump can be stably flattened, whereby the electrode of the semiconductor element is stably placed on the solder bump, and the electrode of the semiconductor element and the semiconductor element connection pad are electrically connected. It is possible to provide a method of manufacturing a wiring board that can be satisfactorily connected.


図１は、本発明の配線基板の実施の形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２（ａ）〜（ｄ）は、本発明の配線基板の製造方法の実施形態の一例を示す概略断面図である。2A to 2D are schematic cross-sectional views showing an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図３（ｅ）〜（ｇ）は、本発明の配線基板の製造方法の実施形態の一例を示す概略断面図および概略側面図である。3E to 3G are a schematic cross-sectional view and a schematic side view showing an example of an embodiment of a method for manufacturing a wiring board according to the present invention.

次に、本発明の配線基板の製造方法の実施形態の一例を図１〜図３を基にして詳細に説明する。   Next, an example of an embodiment of a method for manufacturing a wiring board according to the present invention will be described in detail with reference to FIGS.

図１に本発明配線基板の製造方法により接続された配線基板１０を用いた電子部品の概略断面図を示す。配線基板１０は、コア用の絶縁層１の両主面にビルドアップ用の絶縁層３が複数層ずつ積層されて成る絶縁基板Ｓの内部および表面にコア用の配線導体２とビルドアップ用の配線導体４を配設して成る。コア用の絶縁層１は例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、コア用の配線導体２は例えば銅箔や銅めっき層から成る。またビルドアップ用の絶縁層３は例えばエポキシ樹脂やポリイミド樹脂などの熱硬化性樹脂を含有する電気絶縁材料から成り、ビルドアップ用の配線導体４は例えば銅めっき層から成る。   FIG. 1 shows a schematic cross-sectional view of an electronic component using a wiring board 10 connected by the method for manufacturing a wiring board of the present invention. The wiring substrate 10 includes a core wiring conductor 2 and a build-up layer on the inside and surface of an insulating substrate S in which a plurality of build-up insulating layers 3 are laminated on both main surfaces of the core insulating layer 1. A wiring conductor 4 is provided. The core insulating layer 1 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as epoxy resin or bismaleimide triazine resin, and the core wiring conductor 2 is made of, for example, a copper foil or a copper plating layer. . The build-up insulating layer 3 is made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin, and the build-up wiring conductor 4 is made of, for example, a copper plating layer.

配線基板１０の上面中央部には、半導体素子Ｅがフリップチップ接続により搭載される半導体素子搭載部１０ａが形成されている。半導体素子搭載部１０ａには、半導体素子Ｅの電極Ｔ１に接続される半導体素子接続パッド６が形成されている。また、配線基板１０の上面外周部には、電気基板Ｃが搭載される電気基板搭載部１０ｂが形成されている。電気基板搭載部１０ｂには電気基板Ｃの接続端子Ｔ２が接続される電気基板接続パッド７が形成されている。これらの半導体素子接続パッド６および電気基板接続パッド７は、最表層に形成された配線導体４の一部から形成されている。   A semiconductor element mounting portion 10a on which the semiconductor element E is mounted by flip chip connection is formed at the center of the upper surface of the wiring substrate 10. A semiconductor element connection pad 6 connected to the electrode T1 of the semiconductor element E is formed in the semiconductor element mounting portion 10a. Further, an electric board mounting portion 10 b on which the electric board C is mounted is formed on the outer peripheral portion of the upper surface of the wiring board 10. An electric board connection pad 7 to which a connection terminal T2 of the electric board C is connected is formed on the electric board mounting portion 10b. These semiconductor element connection pads 6 and electric board connection pads 7 are formed from a part of the wiring conductor 4 formed on the outermost layer.

さらに配線基板１０の上面には、半導体素子接続パッド６および電気基板接続パッド７を露出させる開口部を有するようにしてソルダーレジスト層５が形成されている。ソルダーレジスト層５は、半導体素子搭載部１０ａから電気基板搭載部１０ｂを含む領域にわたり形成された第１のソルダーレジスト層５ａと、この第１のソルダーレジスト５ａ上の電気基板搭載部１０ｂに半導体素子搭載部１０ａを囲繞するように形成された第２のソルダーレジスト層５ｂとを積層した２層構造を有しており、それにより半導体素子搭載部１０ａで薄く、その周囲で厚くなっている。なお、第１のソルダーレジスト層５ａの厚みは５〜２０μｍ程度である。また第２のソルダーレジスト層５ｂの厚みは１０〜３０μｍ程度である。このようなソルダーレジスト層５は、エポキシ樹脂やポリイミド樹脂などの熱硬化性樹脂を含有する電気絶縁材料から成り、好ましくは３〜６ＧＰａの弾性率を有する。   Further, a solder resist layer 5 is formed on the upper surface of the wiring substrate 10 so as to have openings for exposing the semiconductor element connection pads 6 and the electric substrate connection pads 7. The solder resist layer 5 includes a first solder resist layer 5a formed from the semiconductor element mounting portion 10a to a region including the electric substrate mounting portion 10b, and an electric substrate mounting portion 10b on the first solder resist 5a. It has a two-layer structure in which a second solder resist layer 5b formed so as to surround the mounting portion 10a is laminated, thereby being thin at the semiconductor element mounting portion 10a and thicker at the periphery thereof. In addition, the thickness of the 1st soldering resist layer 5a is about 5-20 micrometers. The thickness of the second solder resist layer 5b is about 10 to 30 μm. Such a solder resist layer 5 is made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin, and preferably has an elastic modulus of 3 to 6 GPa.

そして、半導体素子搭載部１０ａには半導体素子Ｅが半田バンプＢ１を介して搭載される。また、電気基板搭載部１０ｂには電気基板Ｃが半田ボールＢ２を介して搭載される。なお、半導体素子搭載部１０ａに半導体素子Ｅを搭載するには、半導体素子接続パッド６上に半田バンプＢ１を予め溶着しておくとともにその頭頂部を平坦化した後、半田バンプＢ１上に半導体素子Ｅの電極Ｔ１を載せてリフロー処理する方法が採用される。また電気基板搭載部１０ｂに電気基板Ｃを搭載するには、電気基板Ｃの接続端子Ｔ２に半田ボールＢ２を予め溶着しておくとともにその半田ボールＢ２を電気基板接続パッド７上に載せてリフロー処理する方法が採用される。なお半導体素子Ｅを搭載した後は、半導体素子Ｅと配線基板１０との間にアンダーフィルと呼ばれる封止樹脂Ｇを注入する。このとき、半導体素子搭載部１０ａは厚みの厚い第２のソルダーレジスト層５ｂで囲繞されているので、封止樹脂Ｇの広がりは第２のソルダーレジスト５ｂの内周面でせき止められて電気基板接続パッド７に到達することはない。したがって、封止樹脂Ｇが配線基板１０と電気基板Ｃとの接続に支障をきたすようなことはない。   The semiconductor element E is mounted on the semiconductor element mounting portion 10a via the solder bump B1. In addition, the electric substrate C is mounted on the electric substrate mounting portion 10b via the solder ball B2. In order to mount the semiconductor element E on the semiconductor element mounting portion 10a, the solder bump B1 is preliminarily welded on the semiconductor element connection pad 6 and the top is flattened, and then the semiconductor element E is mounted on the solder bump B1. A method of performing the reflow process by placing the electrode T1 of E is employed. In order to mount the electric substrate C on the electric substrate mounting portion 10b, the solder ball B2 is previously welded to the connection terminal T2 of the electric substrate C, and the solder ball B2 is placed on the electric substrate connection pad 7 to perform reflow processing. Is adopted. After mounting the semiconductor element E, a sealing resin G called underfill is injected between the semiconductor element E and the wiring board 10. At this time, since the semiconductor element mounting portion 10a is surrounded by the thick second solder resist layer 5b, the spreading of the sealing resin G is blocked by the inner peripheral surface of the second solder resist 5b, so that the electric substrate connection The pad 7 is never reached. Therefore, the sealing resin G does not hinder the connection between the wiring board 10 and the electric board C.

次に、本発明の配線基板の製造方法の一例について、図２（ａ）〜（ｄ）および図３（ｅ）〜（ｇ）を基にして詳細に説明する。なお、本説明においては、半田バンプの平坦化方法を中心に説明する。また、図１と同様の個所には同様の符号を付して説明する。   Next, an example of a method for manufacturing a wiring board according to the present invention will be described in detail based on FIGS. 2 (a) to 2 (d) and FIGS. 3 (e) to 3 (g). In this description, the method for flattening the solder bump will be mainly described. Further, the same parts as those in FIG.

まず、図２（ａ）に示すように、絶縁基板Ｓの上面に半導体素子接続パッド６および電気基板接続パッド７を形成する。このような半導体素子接続パッド６および電気基板接続パッド７は、例えば周知のセミアディティブ法を用いることにより形成できる。 First, as shown in FIG. 2A, the semiconductor element connection pads 6 and the electric substrate connection pads 7 are formed on the upper surface of the insulating substrate S. Such semiconductor element connection pads 6 and electrical substrate connection pads 7 can be formed by using, for example, a known semi-additive method.

次に、図２（ｂ）に示すように、絶縁基板Ｓの表面に半導体素子接続パッド６および電気基板接続パッド７の中央部を露出させる開口部を有する第１のソルダーレジスト層５ａを形成する。第１のソルダーレジスト層５ａの形成は、絶縁基板Ｓの表面にソルダーレジスト用の感光性の樹脂フィルムを貼着するとともに、これを周知のフォトリソグラフィ技術を用いて所定のパターンに露光および現像した後、硬化させることにより行なう。なお絶縁基板Ｓの上面中央部に配設された接続パッド６の形成領域は、半導体素子Ｅが搭載される半導体素子搭載部１０ａとなり、電気基板接続パッド７の形成領域は電気基板Ｃが搭載される電気回路搭載部１０ｂとなる。   Next, as shown in FIG. 2B, a first solder resist layer 5a having an opening exposing the central portion of the semiconductor element connection pad 6 and the electric substrate connection pad 7 is formed on the surface of the insulating substrate S. . Formation of the 1st soldering resist layer 5a stuck the photosensitive resin film for soldering resists on the surface of the insulated substrate S, and exposed and developed this to the predetermined pattern using the well-known photolithography technique. Then, it is performed by curing. In addition, the formation region of the connection pad 6 disposed in the central portion of the upper surface of the insulating substrate S becomes the semiconductor element mounting portion 10a on which the semiconductor element E is mounted, and the electric substrate C is mounted on the formation region of the electric substrate connection pad 7. The electric circuit mounting portion 10b.

次に、図２（ｃ）に示すように、電気基板搭載部１０ｂにおける第１のソルダーレジスト層５ａの上面に、電気基板接続パッド７を露出させる開口部を有するとともに半導体素子搭載部１０ａを囲繞する第２のソルダーレジスト層５ｂを形成する。ソルダーレジスト５ｂの形成は、ソルダーレジスト５ａの場合と同様の方法により行なえばよい。   Next, as shown in FIG. 2C, the upper surface of the first solder resist layer 5a in the electric substrate mounting portion 10b has an opening for exposing the electric substrate connection pad 7 and surrounds the semiconductor element mounting portion 10a. A second solder resist layer 5b is formed. The solder resist 5b may be formed by the same method as that for the solder resist 5a.

次に、図２（ｄ）に示すように、第１のソルダーレジスト層５ａの開口部から露出した接続パッド６上に半田バンプＢ１を溶着する。このとき、半田バンプＢ１の頭頂部が第２のソルダーレジスト層５ｂの上面よりも若干高く形成されるようにする。半田バンプＢ１は、周知の印刷技術により接続パッド６上に半田ペーストを塗布した後に、リフロー処理することにより形成される。   Next, as shown in FIG. 2D, solder bumps B1 are welded onto the connection pads 6 exposed from the openings of the first solder resist layer 5a. At this time, the top of the solder bump B1 is formed to be slightly higher than the upper surface of the second solder resist layer 5b. The solder bump B1 is formed by applying a solder paste on the connection pad 6 by a known printing technique and then performing a reflow process.

次に、図３（ｅ）および図３（ｆ）に示すように、第２のソルダーレジスト層５ｂ上および半田バンプＢ１上に押圧ローラーＲを上方から押さえながら転動させて、図３（ｇ）に示すように半田バンプＢ１の頭頂部を平坦化する。押圧ローラーＲは、例えば直径が１０〜３０ｍｍ程度の円柱状のステンレスから成る。なお、押圧ローラーＲが転動している方向の前面から見た状態を図３（ｅ）に示し、側面から見た状態を図３（ｆ）に示している。押圧ローラーＲは、第２のソルダーレジスト層５ｂおよび半田バンプＢ１を上方から押さえながら矢印の方向に転動しているが、このとき、押圧ローラーＲが第２のソルダーレジスト層５ｂを弾性変形で凹ませつつ半田バンプＢ１の頭頂部を塑性変形で押し潰すようにする。第２のソルダーレジスト層５ｂを弾性変形で凹ませながら押圧ローラーＲを転動させることにより、半導体素子搭載部１０ａ内の半田バンプＢ１の頭頂部をソルダーレジスト層５ａの上面よりも低い位置まで押しつぶして良好に平坦化することが可能となる。押圧ローラーＲが転動した後は、第２のソルダーレジスト層５ｂは弾性力により元の高さに復元するが、半田バンプＢ１の頭頂部は第２のソルダーレジスト層５ｂの上面よりも低い位置で平坦に塑性変形されたままとなる。したがって本発明によれば、半導体素子接続パッドに溶着された半田バンプの頭頂部を十分に平坦化することができ、それにより半田バンプ上に半導体素子の電極を安定した状態で載せて半導体素子の電極と半導体素子接続パッドとを電気的に良好に接続することが可能な配線基板の製造方法を提供することができる。   Next, as shown in FIG. 3 (e) and FIG. 3 (f), rolling is performed while pressing the pressure roller R from above on the second solder resist layer 5b and the solder bump B1. The top of the solder bump B1 is flattened as shown in FIG. The pressing roller R is made of, for example, a cylindrical stainless steel having a diameter of about 10 to 30 mm. In addition, the state seen from the front surface in the direction in which the pressing roller R rolls is shown in FIG. 3 (e), and the state seen from the side surface is shown in FIG. 3 (f). The pressing roller R rolls in the direction of the arrow while pressing the second solder resist layer 5b and the solder bump B1 from above. At this time, the pressing roller R elastically deforms the second solder resist layer 5b. The top of the solder bump B1 is crushed by plastic deformation while being recessed. By rolling the pressing roller R while denting the second solder resist layer 5b by elastic deformation, the top of the solder bump B1 in the semiconductor element mounting portion 10a is crushed to a position lower than the upper surface of the solder resist layer 5a. Can be satisfactorily flattened. After the pressing roller R rolls, the second solder resist layer 5b is restored to its original height by the elastic force, but the top of the solder bump B1 is lower than the upper surface of the second solder resist layer 5b. It remains flat and plastically deformed. Therefore, according to the present invention, the tops of the solder bumps welded to the semiconductor element connection pads can be sufficiently flattened, whereby the electrodes of the semiconductor element are stably placed on the solder bumps. It is possible to provide a method for manufacturing a wiring board capable of electrically and satisfactorily connecting an electrode and a semiconductor element connection pad.

なお、押圧ローラーＲの直径が１０ｍｍを未満であると、押圧ローラーＲ自体が転動に伴い撓んで半田バンプＢ１を良好に平坦化できなくなる危険性が高くなり、逆に３０ｍｍを超えると、ソルダーレジスト層５ｂ上を上方から押さえながら転動する際にソルダーレジスト層５ｂを弾性変形で良好に凹ますことが困難となる。したがって、押圧ローラーＲの直径は１０〜３０ｍｍの範囲が好ましい。   If the diameter of the pressing roller R is less than 10 mm, there is a high risk that the pressing roller R itself will be bent as it rolls and the solder bumps B1 cannot be satisfactorily flattened. When rolling while pressing on the resist layer 5b from above, it becomes difficult to dent the solder resist layer 5b well by elastic deformation. Therefore, the diameter of the pressing roller R is preferably in the range of 10 to 30 mm.

５ ソルダーレジスト層
６ 半導体素子接続パッド
１０ 配線基板
１０ａ 半導体素子搭載部
Ｂ１ 半田バンプ
Ｅ 半導体素子
Ｒ 押圧ローラー
Ｓ 絶縁基板 5 Solder resist layer 6 Semiconductor element connection pad 10 Wiring board 10a Semiconductor element mounting part B1 Solder bump E Semiconductor element R Pressing roller S Insulating substrate

Claims (1)

上面中央部に半導体素子が搭載される半導体素子搭載部を有する絶縁基板と、前記半導体素子搭載部に配設された複数の半導体素子接続パッドと、前記絶縁基板の上面に、前記半導体素子接続パッドの各々を個別に露出させる複数の第１の開口部を有するように被着された第１のソルダーレジスト層と、該第１のソルダーレジスト層上に、前記半導体素子搭載部を囲繞するとともに前記複数の半導体素子接続パッドを一括して露出させる第２の開口部を有するようにして被着されており、前記半導体素子接続パッドの上面より高い上面を有する第２のソルダーレジスト層と、前記半導体素子接続パッド上に溶着されており、頭頂部が平坦化された半田バンプとを備える配線基板の製造方法であって、前記絶縁基板の上面に前記半導体素子接続パッドおよび前記第１および第２のソルダーレジスト層を形成する工程と、前記半導体素子接続パッド上に前記第２のソルダーレジスト層の上面よりも突出する高さの半田バンプを溶着する工程と、前記第２のソルダーレジスト層上および前記半田バンプ上に、前記第２のソルダーレジスト層を弾性変形で凹ませつつ前記半田バンプの頭頂部を塑性変形で押し潰すように押圧ローラーを転動させることにより前記頭頂部を、前記第１のソルダーレジスト層の上面より高い位置となるとともに前記第２のソルダーレジスト層の上面より低い位置となるように平坦化する工程とを行なうことを特徴とする配線基板の製造方法。
An insulating substrate having a semiconductor element mounting portion on which a semiconductor element is mounted at the center of the upper surface, a plurality of semiconductor element connection pads disposed on the semiconductor element mounting portion, and the semiconductor element connection pad on the upper surface of the insulating substrate said a first solder resist layer which is deposited so as to have a plurality of first openings exposing individually each to the first solder resist layer, as well as surrounding the semiconductor element mounting portion A second solder resist layer having a top surface higher than the top surface of the semiconductor element connection pad, the second solder resist layer being deposited so as to have a second opening that exposes a plurality of semiconductor element connection pads collectively; A method of manufacturing a wiring board comprising solder bumps welded onto an element connection pad and having a flat top portion, wherein the semiconductor element connection is formed on the upper surface of the insulating substrate. Forming the first and second solder resist layers, and welding a solder bump having a height protruding from the upper surface of the second solder resist layer on the semiconductor element connection pad; Rolling the pressing roller on the second solder resist layer and the solder bumps so that the top of the solder bumps is crushed by plastic deformation while the second solder resist layer is recessed by elastic deformation. And a step of planarizing the top of the head so that the top of the head is higher than the upper surface of the first solder resist layer and lower than the upper surface of the second solder resist layer. A method for manufacturing a substrate.
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