TWI738898B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI738898B TWI738898B TW106136821A TW106136821A TWI738898B TW I738898 B TWI738898 B TW I738898B TW 106136821 A TW106136821 A TW 106136821A TW 106136821 A TW106136821 A TW 106136821A TW I738898 B TWI738898 B TW I738898B
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- nickel
- electroplating
- semiconductor device
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Abstract
本發明之目的在於令半導體裝置的可靠度提高。為了達成上述目的,本發明以覆蓋源極電極SE以及閘極電極GE的方式形成了絶緣膜(PA),並於該絶緣膜(PA),形成了露出源極電極SE的一部分的開口部(OPS)以及露出閘極電極GE的一部分的開口部(OPG)。在從開口部(OPS)露出的源極電極SE上,形成了電鍍層PLS,在從開口部(OPG)露出的閘極電極GE上,形成了電鍍層PLG。利用從開口部(OPS)露出之部分的源極電極SE與電鍍層PLS,形成源極焊墊(PDS),利用從開口部(OPG)露出之部分的閘極電極GE與電鍍層PLG,形成閘極焊墊(PDG)。閘極焊墊用的開口部(OPG)的面積,比源極焊墊用的開口部(OPS)的面積更小,電鍍層PLG的厚度,比電鍍層PLS的厚度更厚。
Description
本發明係關於一種半導體裝置以及其製造方法,其係可適當應用於例如具有結合焊墊的半導體裝置以及其製造方法者。
在形成了功率半導體元件的半導體晶片中,流經設置在主面側的焊墊與設置在背面側的背面電極之間的電流,可由形成於半導體晶片內的功率半導體元件進行控制。因此,該等半導體晶片,可應用於流過較大電流的開關元件等。當將該等半導體晶片封裝體化時,考慮到降低電阻,會於半導體晶片的焊墊透過焊料連接金屬板。
於日本特開2005-33130號公報(專利文獻1),記載了關於在鋁電極的表面形成了包含鎳電鍍層在內的外部連接用的金屬電極的半導體裝置的技術。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2005-33130號公報
[發明所欲解決的問題] 吾人期望在具有結合焊墊的半導體裝置中,令可靠度提高。
其他的問題與新穎性特徴,根據本說明書的記述以及所附圖式應可明瞭。 [解決問題的手段]
根據本發明一實施態樣,半導體裝置,具有:第1焊墊用的第1導電膜圖案以及第2焊墊用的第2導電膜圖案;以覆蓋該第1以及第2導電膜圖案的方式形成的絶緣膜;形成於該絶緣膜並露出該第1導電膜圖案的一部分的第1開口部;以及形成於該絶緣膜並露出該第2導電膜圖案的一部分的第2開口部。半導體裝置,更具有:形成於從該第1開口部露出之部分的該第1導電膜圖案上的第1電鍍層;以及形成於從該第2開口部露出之部分的該第2導電膜圖案上的第2電鍍層。利用從該第1開口部露出之部分的該第1導電膜圖案與該第1電鍍層,形成該第1焊墊,利用從該第2開口部露出之部分的該第2導電膜圖案與該第2電鍍層,形成該第2焊墊。該第2開口部的面積,比該第1開口部的面積更小,該第2電鍍層的厚度,比該第1電鍍層的厚度更厚。
另外,根據本發明一實施態樣,半導體裝置的製造方法,具有:形成第1焊墊用的第1導電膜圖案以及第2焊墊用的第2導電膜圖案的步驟;以覆蓋該第1以及第2導電膜圖案的方式形成絶緣膜的步驟;以及於該絶緣膜,形成露出該第1導電膜圖案的一部分的第1開口部與露出該第2導電膜圖案的一部分的第2開口部的步驟。半導體裝置的製造方法,更具有:在從該第1開口部露出之部分的該第1導電膜圖案上形成第1電鍍層,並在從該第2開口部露出之部分的該第2導電膜圖案上形成第2電鍍層的步驟。利用從該第1開口部露出之部分的該第1導電膜圖案與該第1電鍍層,形成該第1焊墊,利用從該第2開口部露出之部分的該第2導電膜圖案與該第2電鍍層,形成該第2焊墊。該第2開口部的面積,比該第1開口部的面積更小,該第2電鍍層的厚度,比該第1電鍍層的厚度更厚。 [發明的功效]
若根據本發明一實施態樣,便可令半導體裝置的可靠度提高。
在以下的實施態樣中,於便宜作法上有其必要時,會分割成複數個段落或實施態樣進行説明,惟除了特別明示的情況之外,該等內容並非互無相關,而係具有其中一方為另一方的部分或全部的變化實施例、詳細說明、補充説明等的關係。另外,在以下的實施態樣中,當提及要件的數目等(包含個數、數値、數量、範圍等)時,除了特別明示的情況以及在原理上明顯限定於特定數值的情況等之外,並非僅限於該特定的數目,在特定的數目以上或以下均可。再者,在以下的實施態樣中,其構成要件(亦包含要件步驟等),除了特別明示的情況以及認為在原理上明顯為必須的情況等之外,並非一定為必要構件,自不待言。同樣地,在以下的實施態樣中,當提及構成要件等的形狀、位置關係等時,除了特別明示的情況以及認為在原理上明顯並非如此的情況等之外,亦包含實質上與該形狀等近似或類似的態樣等。此點,針對上述數值以及範圍也是同樣。
以下,根據圖式詳細説明實施態樣。另外,在用來說明實施態樣的全部圖式中,具有相同功能的構件會附上相同的符號,其重複説明省略。另外,以下的實施態樣,除了特別有其必要時以外相同或同樣的部分的説明原則上不重複。
另外,在實施態樣所使用的圖式中,即使是剖面圖,為了令圖式容易檢視,有時也會省略影線。另外,即使是俯視圖,為了令圖式容易檢視,有時也會附上影線。
(實施態樣1) <關於半導體裝置(半導體晶片)的整體構造> 茲參照圖式説明本實施態樣的半導體裝置。
圖1以及圖2,係本實施態樣之半導體裝置(半導體晶片)CP的整體俯視圖,圖1,係表示半導體裝置CP的頂面側的整體俯視圖,圖2,係表示半導體裝置CP的背面(底面)側的整體俯視圖。
如圖1以及圖2所示的,本實施態樣之半導體裝置CP,具有:一側的主面,亦即頂面,以及頂面的相反側的主面,亦即背面(底面),於圖1,顯示出半導體裝置CP的頂面,於圖2,顯示出半導體裝置CP的背面。
半導體裝置CP,如圖1所示的,於頂面側,具有:作為第1端子的源極焊墊(源極用焊墊、源極用結合焊墊)PDS,以及作為控制用端子的閘極焊墊(閘極用焊墊、閘極用結合焊墊)PDG,另外,如圖2所示的,於背面側,具有作為第2端子的背面電極BE。源極焊墊PDS、閘極焊墊PDG以及背面電極BE,各自可發揮作為半導體裝置CP的外部連接用的端子的功能。
具體而言,於半導體裝置CP的頂面側的最上層,形成了作為表面保護膜的絶緣膜PA,源極焊墊PDS從設置於該絶緣膜PA的源極用的開口部OPS露出,閘極焊墊PDG從設置於絶緣膜PA的閘極用的開口部OPG露出。另外,半導體裝置CP的背面側的最上層為背面電極BE,於半導體裝置CP的背面全部形成了背面電極BE。
於構成半導體裝置CP的半導體基板SB,形成了控制形成於半導體裝置CP的頂面側的第1端子(在此為源極焊墊PDS)與形成於半導體裝置CP的背面側的第2端子(在此為背面電極BE)之間的導通的半導體元件。另外,構成半導體裝置CP的半導體基板SB,在圖1以及圖2中並未顯示,惟顯示於後述的圖11以及圖12。因此,半導體裝置CP,控制形成於半導體基板SB的半導體元件,藉此,控制頂面側的第1端子與背面側的第2端子之間的導通,電流便在頂面側的第1端子與背面側的第2端子之間流動。因此,半導體裝置CP,可作為較大電流流通的開關元件使用。閘極焊墊PDG,發揮作為控制第1端子與第2端子之間的導通的控制用端子的功能。
作為形成於半導體基板SB並控制半導體裝置CP的頂面側的第1端子與半導體裝置CP的背面側的第2端子之間的導通的半導體元件,可使用功率電晶體。作為功率電晶體,可使用例如溝槽閘極型的MISFET(Metal Insulator Semiconductor Field Effect Transistor,金屬絕緣體半導體場效電晶體),惟亦可使用溝槽閘極型的IGBT(Insulated Gate Bipolar Transistor,絶緣閘極型雙極電晶體)。當使用MISFET作為該半導體元件時,半導體裝置CP的頂面側的第1端子為源極端子,半導體裝置CP的背面側的第2端子為汲極端子,半導體裝置CP的頂面側的控制用端子為閘極端子。當使用IGBT作為該半導體元件時,半導體裝置CP的頂面側的第1端子為射極端子,半導體裝置CP的背面側的第2端子為集極端子,半導體裝置CP的頂面側的控制用端子為閘極端子。
<關於半導體封裝體構造> 接著,針對將上述半導體裝置(半導體晶片)CP封裝體化的半導體裝置(半導體封裝體)PKG進行説明。
圖3~圖8,係以示意方式表示將上述半導體裝置CP封裝體化的半導體裝置PKG的一例的頂面圖(圖3)、底面圖(圖4)、平面透視圖(圖5~圖7)以及剖面圖(圖8)。圖3,顯示出半導體裝置PKG的頂面側的整體俯視圖,圖4,顯示出半導體裝置PKG的底面(背面)側的整體俯視圖,圖5,顯示出從頂面側觀察半導體裝置PKG並將封裝部MR透視的俯視圖(頂面圖)。圖6,對應從圖5去除金屬板MP以及導線WA的圖式,圖7,對應從圖6更進一步去除半導體晶片CP1的圖式。圖5~圖7,將封裝部MR的外周圍位置以虛線表示。另外,圖5的A1-A1線的剖面圖,大致對應圖8。
使用於圖3~圖8所示之半導體裝置(半導體封裝體)PKG的半導體晶片CP1,係與上述圖1以及圖2所示之半導體裝置(半導體晶片)CP相同者,故在此,針對半導體晶片CP1的構造的重複説明省略。
如圖3~圖8所示的,半導體裝置PKG,具有:半導體晶片CP1;搭載半導體晶片CP1的晶片焊墊(晶片搭載部)DP;與半導體晶片CP1的源極焊墊PDS接合的金屬板(導體板)MP;由導電體所形成的引線LD;導電性的導線(結合導線)WA;以及將該等構件封裝的封裝部(封裝樹脂部)MR。
封裝部MR,係由例如熱硬化性樹脂材料等的樹脂材料等所構成,亦可含有填料等。例如,可用含有填料的環氧樹脂等形成封裝部MR。除了環氧系的樹脂以外,基於低應力化等理由,亦可使用添加了例如苯酚系硬化劑、矽氧橡膠以及填料等的聯苯系的熱硬化性樹脂,作為封裝部MR的材料。
封裝部MR,具有:一側的主面,亦即頂面MRa;頂面MRa的相反側的主面,亦即底面MRb;還有與頂面MRa以及底面MRb交叉的側面MRc1、MRc2、MRc3、MRc4。亦即,封裝部MR的外觀,形成被頂面MRa、底面MRb以及側面MRc1、MRc2、MRc3、MRc4所包圍的薄板狀。封裝部MR的頂面MRa以及底面MRb的平面形狀,形成例如矩形形狀,亦可於該矩形的角部帶有圓形。在封裝部MR的側面MRc1、MRc2、MRc3、MRc4之中,側面MRc1與側面MRc3互相對向,側面MRc2與側面MRc4互相對向,側面MRc1與側面MRc2、MRc4互相交叉,側面MRc3與側面MRc2、MRc4互相交叉。
引線(引線部)LD,係由導電體所構成,宜由銅(Cu)或銅合金等的金屬材料所構成。引線LD,一部分被封裝在封裝部MR內,另一部分從封裝部MR的側面向封裝部MR的外部突出。以下,在各引線LD中,將位在封裝部MR內的部分稱為內引線部,將位在封裝部MR外的部分稱為外引線部。
另外,本實施態樣之半導體裝置PKG,構成引線LD的一部分(外引線部)從封裝部MR的側面突出的構造,以下係根據該構造進行説明,惟並非僅限於該構造,例如,亦可採用引線LD幾乎並未從封裝部MR的側面突出,且引線LD的一部分在封裝部MR的底面MRb露出的構造(QFN型的構造)等。
引線LD,配置於封裝部MR的側面MRc1側,引線LD的外引線部,從封裝部MR的側面MRc1向封裝部MR外突出。在圖8的情況下,引線LD的外引線部呈平坦狀,惟作為另一態樣,引線LD的外引線部,亦可受到彎曲加工,而令外引線部的端部附近的底面與封裝部MR的底面MRb大致位在同一平面上。
在封裝部MR的底面MRb,晶片焊墊DP的底面(背面)露出。在封裝部MR的頂面MRa,晶片焊墊DP並未露出。晶片焊墊DP,係搭載半導體晶片CP1的晶片搭載部。
晶片焊墊DP係由導電體所構成,宜由銅(Cu)或銅合金等的金屬材料所構成。若晶片焊墊DP與引線LD以相同材料形成,更佳,藉此,便更容易製得半導體裝置PKG。
在晶片焊墊DP的頂面上,搭載了半導體晶片CP1。於半導體晶片CP1的表面,形成了源極焊墊PDS以及閘極焊墊PDG,於半導體晶片CP1的背面,形成了背面電極(背面汲極電極)BE。在此,在半導體晶片CP1中,在彼此位於相反側的2個主面之中,將形成了源極焊墊PDS以及閘極焊墊PDG的該側的主面,稱為半導體晶片CP1的表面,並將該表面的相反側且形成了背面電極BE的該側的主面,稱為半導體晶片CP1的背面。
半導體晶片CP1,以半導體晶片CP1的表面向上,半導體晶片CP1的背面(背面電極BE)面向晶片焊墊DP的頂面的狀態,搭載在晶片焊墊DP的頂面上。半導體晶片CP1的背面,透過導電性的接合層(接合材料)BD1與晶片焊墊DP的頂面接合固定。因此,透過導電性的接合層BD1,半導體晶片CP1的背面電極BE與晶片焊墊DP接合固定,同時電連接。接合層BD1,具有導電性,例如,由銀(Ag)糊膏等的導電性糊膏型的接合材料或是焊料等所構成。半導體晶片CP1,被封裝在封裝部MR內,並未從封裝部MR露出。
在半導體晶片CP1動作時所產生的熱,便可大部分從半導體晶片CP1的背面通過晶片焊墊DP向外部散熱。因此,晶片焊墊DP,宜比搭載於其上的半導體晶片CP1的面積更大,藉此,便可令散熱性提高。
半導體晶片CP1的閘極焊墊PDG與引線LD的內引線部,透過導電性連接構件(亦即導線WA)電連接。具體而言,半導體晶片CP1的閘極焊墊PDG與導線WA的一方的端部連接,該導線WA的另一方的端部,與引線LD的內引線部連接,透過該導線WA,半導體晶片CP1的閘極焊墊PDG與引線LD電連接。並未被封裝部MR所覆蓋而露出之部分的引線LD(亦即引線LD的外引線部),可發揮作為與半導體晶片CP1的閘極焊墊PDG電連接的外部端子的功能。
導線WA,係導電性的連接構件,更特定而言係導電性的導線,宜由金(Au)線、銅(Cu)線或鋁(Al)線等的金屬線(金屬細線)所構成。導線WA,被封裝在封裝部MR內,並未從封裝部MR露出。
半導體晶片CP1的源極焊墊PDS,透過導電性的接合層(接合材料)BD2,與金屬板MP接合固定,同時電連接。接合層BD2,具有導電性,宜由焊料所構成。因此,金屬板MP,透過由焊料所構成的接合層BD2,與半導體晶片CP1的源極焊墊PDS電連接。因此,半導體晶片CP1的源極焊墊PDS,係用來連接金屬板MP的焊墊(結合焊墊),半導體晶片CP1的閘極焊墊PDG,係用來連接導線WA的焊墊(結合焊墊)。
金屬板MP,一部分從封裝部MR露出。具體而言,金屬板MP的一部分,從封裝部MR的側面MRc3向封裝部MR外突出。亦即,金屬板MP,具有位在封裝部MR外的部分與位在封裝部MR內的部分,位在封裝部MR內的部分的金屬板MP,透過接合層BD2,與半導體晶片CP1的源極焊墊PDS接合。並未被封裝部MR所覆蓋而露出之部分的金屬板MP,可發揮作為與半導體晶片CP1的源極焊墊PDS電連接的外部端子的功能。
金屬板MP,宜由導電性以及熱傳導性較高的金屬(金屬材料)所形成,可由例如銅(Cu)或銅(Cu)合金所形成,較為適當。從加工容易、熱傳導性高,以及價格比較低廉等觀點來看,金屬板MP若由銅(Cu)或銅(Cu)合金所形成,為較佳的態樣。另外,亦可利用鋁(Al)或鋁(Al)合金形成金屬板MP。金屬板MP的寬度,比導線WA的寬度(直徑)更大(寬)。半導體晶片CP1的源極焊墊PDS與電阻比導線WA更低的金屬板MP連接,故可降低形成於半導體晶片CP1的半導體元件(在此縱型的MISFET)的導通電阻。因此,在半導體裝置PKG中,可降低封裝體電阻,並可減少導通損失。另外,取代由金(Au)所形成的導線,使用由價格比金更低廉之金屬材料所形成的金屬板MP,可降低半導體裝置PKG的製造成本。
另外,在圖3~圖8的情況下,金屬板MP的一部分從封裝部MR露出,發揮作為外部端子的功能。作為另一態樣,亦可於半導體裝置PKG設置追加的引線,並在封裝部MR內,將金屬板MP透過導電性的接合材料(宜為焊料)接合於該追加的引線。此時,半導體晶片CP1的源極焊墊PDS,透過導電性的接合層BD2與金屬板MP電連接,該金屬板MP,透過導電性的接合材料與追加的引線電連接,故半導體晶片CP1的源極焊墊PDS便透過金屬板MP等與追加的引線電連接。因此,此時,追加的引線的一部分從封裝部MR露出並發揮作為外部端子的功能,故金屬板MP並未從封裝部MR露出也沒有關係。另外,在此所述之追加的引線,亦可與引線LD同樣具有導電性,並由與引線LD相同的材料所形成。
晶片焊墊DP的底面,從封裝部MR的底面MRb露出。另外,晶片焊墊DP的一部分,從封裝部MR的側面MRc3向封裝部MR外突出。晶片焊墊DP與金屬板MP,彼此並未接觸。並未被封裝部MR所覆蓋而露出之部分的晶片焊墊DP,可發揮作為與半導體晶片CP1的背面電極BE電連接的外部端子的功能。
當令金屬板MP的一部分與晶片焊墊DP的一部分,從封裝部MR的同一側面MRc3突出時,從封裝部MR的側面MRc3突出的部分的金屬板MP,與從封裝部MR的側面MRc3突出的部分的晶片焊墊DP,宜在俯視下並未重疊。藉此,便更容易將外部裝置等連接於半導體裝置PKG的源極端子(亦即金屬板MP)與汲極端子(亦即晶片焊墊DP)。另外,在圖3~圖8的情況下,晶片焊墊DP的一部分係從封裝部MR的側面MRc3向封裝部MR外突出,惟作為另一態樣,晶片焊墊DP的一部分並未從封裝部MR的側面MRc3突出的態樣,亦為可能。
形成於半導體晶片CP1的半導體元件的導通電流(ON電流),主要流經金屬板MP與晶片焊墊DP之間,藉由在導通路徑使用金屬板MP,便可降低導通損失。另外,導線WA的電阻比金屬板MP更高,惟若相較於從源極焊墊PDS到金屬板MP的導電路徑而言,流過從閘極焊墊PDG到引線LD的導電路徑的電流較小,故閘極焊墊PDG與引線LD之間,可用導線WA電連接。
圖9,係表示半導體裝置PKG的安裝態樣的一例的剖面圖。於圖9,顯示出與上述圖8對應的剖面。
如圖9所示的,半導體裝置PKG,例如,可搭載在金屬平板(散熱片)HS上。金屬平板HS,例如,係具備水冷機構的金屬平板。在圖9的情況下,半導體裝置PKG,係以晶片焊墊DP的底面對向金屬平板HS的頂面的方式,透過導熱膏GR搭載在金屬平板HS的頂面上。因此,於半導體裝置PKG的晶片焊墊DP與金屬平板HS之間,隔著導熱膏GR。在圖9的情況下,半導體裝置PKG的半導體晶片CP1所產生的熱,大部分可經由導電性的接合層BD1、晶片焊墊DP以及導熱膏GR,散熱到金屬平板HS。
接著,針對半導體裝置PKG的製造步驟進行説明。
欲製造半導體裝置PKG,應準備一體地具有晶片焊墊DP以及引線LD的引線框架。在引線框架中,晶片焊墊DP以及引線LD,各自與引線框架的框架框(圖中未顯示)連結成一體。
接著,實行晶片結合步驟,將半導體晶片CP1,透過接合材料(該接合材料成為上述接合層BD1)搭載並接合在引線框架的晶片焊墊DP的頂面上。藉此,半導體晶片CP1的背面,透過導電性的接合層(接合材料)BD1與晶片焊墊DP的頂面接合固定。
接著,實行導線結合步驟,將半導體晶片CP1的閘極焊墊PDG與引線框架的引線LD之間透過上述導線WA連接。
接著,將上述金屬板MP,透過接合材料(該接合材料成為上述接合層BD2)接合固定於半導體晶片CP1的源極焊墊PDS。此時所使用的接合材料(接合層BD2),係導電性的接合材料,宜為焊料。
之後,實行模製步驟,形成上述封裝部MR,然後,將上述晶片焊墊DP以及引線LD從引線框架切離,並因應需要對引線LD的外引線部進行彎曲加工,藉此,便可製得半導體裝置PKG。
另外,在此,係針對在導線結合步驟之後實行將上述金屬板MP接合於半導體晶片CP1的源極焊墊PDS的步驟的態樣進行説明,惟亦可改換順序,在實行了將上述金屬板MP接合於半導體晶片CP1的源極焊墊PDS的步驟之後,實行導線結合步驟。
另外,在此,係針對半導體裝置PKG具有1個半導體晶片CP1的態樣進行説明,惟並非僅限於此,半導體裝置PKG,亦可具有複數個半導體晶片。圖10,係表示半導體裝置PKG的變化實施例的平面透視圖,在圖10的情況下,半導體裝置PKG,包含半導體晶片CP1、CP2。另外,圖10,與上述圖5同樣,顯示出將封裝部MR1透視的頂面圖。
圖10所示之變化實施例的半導體裝置PKG,不僅相當於上述半導體裝置CP的半導體晶片CP1,亦具有另一半導體晶片CP2,並在封裝部MR1內封裝了半導體晶片CP1、CP2。半導體晶片CP2,例如,係具有用來控制半導體晶片CP1的控制電路的半導體晶片。在此,將圖10所示之半導體裝置PKG,附上符號PKG1,稱為半導體裝置PKG1。
圖10所示之半導體裝置PKG1的概略構造,如以下所述。
亦即,半導體裝置PKG1,具有:半導體晶片CP1、CP2;搭載半導體晶片CP1的晶片焊墊DP1;搭載半導體晶片CP2的晶片焊墊DP2;與半導體晶片CP1的源極焊墊PDS接合的金屬板MP1;複數條導電性的引線LD1、LD2;複數條導電性的導線WA1;以及將該等構件封裝的封裝部(封裝樹脂部)MR1。晶片焊墊DP1、DP2相當於上述晶片焊墊DP,金屬板MP1相當於上述金屬板MP,引線LD1、LD2相當於上述引線LD,導線WA1相當於上述導線WA,封裝部MR1相當於上述封裝部MR。
金屬板MP1透過焊料,與半導體晶片CP1的源極焊墊PDS接合固定,同時電連接。金屬板MP1的另一端,透過焊料,與引線LD1接合並電連接。因此,半導體晶片CP1的源極焊墊PDS,透過金屬板MP1與引線LD1電連接。半導體晶片CP1的上述背面電極BE,透過導電性的接合層與晶片焊墊DP1接合固定,同時電連接。
半導體晶片CP1,可為具有源極焊墊PDS以及閘極焊墊PDG以外的焊墊(結合焊墊)的態樣以及不具有的態樣。在圖10的情況下,半導體晶片CP1,更具有源極焊墊PDS以及閘極焊墊PDG以外的焊墊(結合焊墊)PD1。閘極焊墊PDG以及焊墊PD1的各自的面積(平面尺寸),比源極焊墊PDS的面積更小。半導體晶片CP1的閘極焊墊PDG以及焊墊PD1,各自透過導線WA1,與半導體晶片CP2的焊墊PD2電連接。因此,半導體晶片CP1的源極焊墊PDS,係用來連接金屬板MP1的焊墊,半導體晶片CP1的閘極焊墊PDG以及焊墊PD1,係用來連接導線WA1的焊墊。半導體晶片CP2的其他的焊墊PD3,透過導線WA1,與引線LD2電連接。
<關於半導體晶片的內部構造> 接著,針對上述半導體裝置(半導體晶片)CP的內部構造,參照圖式進行説明。
圖11以及圖12,係本實施態樣之半導體裝置CP的主要部位剖面圖。圖11,大致對應在上述圖1以及圖13的B-B線的位置的剖面圖,圖12,對應將閘極焊墊PDG横切的剖面圖。另外,圖13以及圖14,係本實施態樣之半導體裝置CP的平面透視圖,其顯示出從頂面側觀察半導體晶片CP,並將絶緣膜PA透視的俯視圖(頂面圖)。
另外,在圖13中,為了令源極電極SE、閘極電極GE以及閘極配線GEW的形成位置容易理解,將源極電極SE、閘極電極GE以及閘極配線GEW附上影線表示之,另外,將開口部OP(OPG、OPS)的位置以虛線表示之。另外,在圖14中,為了令電鍍層PL(PLG、PLS)的形成位置容易理解,將電鍍層PL(PLG、PLS)附上影線表示之。如後所述的,係在從開口部OP露出之導電體膜CD上形成了電鍍層PL,故比較圖13與圖14亦可知,在俯視下,開口部OP的形成位置與電鍍層PL的形成位置一致。
如亦於圖11以及圖12所示的,構成半導體裝置(半導體晶片)CP的半導體基板SB,係由導入了例如砷(As)等的n型雜質的n型單晶矽等所構成。亦可使用在由n型單晶矽基板所構成的基板本體上形成了由雜質濃度比其更低的n-
型單晶矽所構成的磊晶層的半導體基板(所謂磊晶晶圓),作為半導體基板SB。
於構成半導體裝置(半導體晶片)CP的半導體基板SB,形成了溝槽閘極型的MISFET。溝槽閘極型的MISFET,係具有溝槽型閘極構造(埋入設置於基板之溝槽的閘極電極構造)的MISFET。針對形成於半導體基板SB的溝槽閘極型的MISFET的具體構造,在以下進行説明。
於半導體基板SB的主面,形成了構成功率電晶體(功率半導體元件)的溝槽閘極型的MISFET。具體而言,於半導體基板SB的主面,形成了複數個單位電晶體單元Q1,形成於半導體基板SB的複數個單位電晶體單元Q1並聯連接,藉此,形成1個功率電晶體。各單位電晶體單元Q1,係由溝槽閘極型的MISFET所構成。在此,在半導體基板SB的主面,形成了構成功率電晶體的複數個單位電晶體單元Q1的平面區域,被稱為電晶體單元區域。
半導體基板SB,具有作為上述單位電晶體單元Q1的汲極區域的功能。在半導體基板SB的背面全面上,形成了汲極用的背面電極BE。背面電極BE,發揮作為汲極端子的功能。
背面電極BE,例如,可由從半導體基板SB的背面依序堆疊之鈦(Ti)層、鎳(Ni)層以及金(Au)層的堆疊膜所形成。
另外,在半導體基板SB中,將形成了溝槽閘極電極TG用的溝槽(trench)的該側的相反側的主面,稱為半導體基板SB的背面。
在電晶體單元區域的半導體基板SB中,形成了p型半導體區域PR,該p型半導體區域PR,具有作為上述單位電晶體單元Q1的通道形成區域的功能。
另外,在電晶體單元區域的半導體基板SB中,在p型半導體區域PR的上部形成了n+
型半導體區域NR,該n+
型半導體區域NR,具有作為上述單位電晶體單元Q1的源極區域的功能,因此,係源極用的半導體區域。於n+
型半導體區域NR之下,存在著p型半導體區域PR。隔設在p型半導體區域PR與背面電極BE之間的部分的半導體基板SB,維持n型的導電型,並具有作為上述單位電晶體單元Q1之汲極區域的功能。
於半導體基板SB,形成了從其主面朝半導體基板SB的厚度方向延伸的溝槽(trench)TR,在溝槽TR內,隔著閘極絶緣膜GF埋入了溝槽閘極電極TG。於溝槽TR的底面以及側面,形成了由氧化矽膜等的絶緣膜所構成的閘極絶緣膜GF,故形成「在埋入溝槽TR的溝槽閘極電極TG與半導體基板SB之間,隔設著閘極絶緣膜GF」的狀態。溝槽閘極電極TG,係由埋入半導體基板SB的溝槽TR內的導電膜所構成,其係由例如摻雜多晶矽膜所構成。圖式雖省略,惟在半導體基板SB的主面,溝槽TR在俯視下形成例如條紋狀或格子狀。
溝槽TR,以從半導體基板SB的頂面,貫通n+
型半導體區域NR與p型半導體區域PR,且端部位在n型的半導體基板SB中的方式形成。因此,溝槽TR的底面,比n+
型半導體區域NR的底面更深,且比p型半導體區域PR的底面更深,而位在n型的半導體基板SB的深度方向的中間部位。
圖11所示之各溝槽TR以及埋入於其的各溝槽閘極電極TG,在與圖11的紙面垂直的方向上延伸,各溝槽閘極電極TG之間,在圖11以及圖12的剖面圖所未顯示的區域連結成一體。形成於半導體基板SB的複數個單位電晶體單元Q1的溝槽閘極電極TG,互相電連接,同時與後述的閘極配線GEW電連接。
接著,針對比半導體基板SB更上層的構造進行説明。
在半導體基板SB的頂面上,以覆蓋溝槽閘極電極TG的方式,形成了絶緣膜(層間絶緣膜)IL。絶緣膜IL係層間絶緣膜,由例如氧化矽膜所構成。
於絶緣膜IL形成了接觸孔(開口部、貫通孔)CT1、CT2。接觸孔CT1,係源極用的接觸孔,形成於在俯視下相鄰的溝槽TR之間。
接觸孔CT2,係閘極用的接觸孔。在圖12的情況下,令與溝槽閘極電極TG形成一體的閘極拉出部(閘極拉出用配線部)TGL在溝槽TR的外部的半導體基板SB上延伸,並在該閘極拉出部TGL之上形成接觸孔CT2,在接觸孔CT2的底部,閘極拉出部TGL的一部分露出。在閘極拉出部TGL與半導體基板SB之間,隔設著與閘極絶緣膜GF同一層的絶緣膜。
在絶緣膜IL上,形成了源極電極SE、閘極電極GE以及閘極配線GEW。源極電極SE、閘極電極GE以及閘極配線GEW,係由形成圖案的導電體膜所形成。具體而言,源極電極SE、閘極電極GE以及閘極配線GEW,係在形成了接觸孔CT1、CT2的絶緣膜IL上以填埋接觸孔CT1、CT2的方式形成導電體膜CD,然後令該導電體膜CD形成圖案所形成。
導電體膜(金屬膜)CD,係由以鋁(Al)為主成分的金屬膜所構成,具體而言,係由鋁膜或鋁合金膜所構成。當使用鋁合金膜作為導電體膜CD時,可使用添加了矽(Si)的鋁合金膜,亦即Al-Si合金膜,或是,添加了銅(Cu)的鋁合金膜,亦即Al-Cu合金膜等,較為適當。
另外,當使用鋁合金膜作為導電體膜CD時,宜為富含鋁(Al)的鋁合金膜。在此,富含鋁(Al),係指鋁(Al)的組成比比50原子%更大。因此,導電體膜CD的鋁(Al)含有率,宜比50原子%更多,更宜在98原子%以上。另外,導電體膜CD的厚度,可為例如3000~5000nm左右。
閘極電極GE與閘極配線GEW係形成一體,源極電極SE,則與閘極電極GE以及閘極配線GEW分離。亦即,閘極電極GE與閘極配線GEW,係形成一體並互相連結,惟源極電極SE,並未與閘極電極GE或閘極配線GEW連結。
源極電極SE,形成於絶緣膜IL上,同時源極電極SE的一部分,埋入源極用的接觸孔CT1內。將源極電極SE之中的埋入源極用的接觸孔CT1內的部分,稱為「源極電極SE的介層部」或「源極用介層部」。
閘極配線GEW,形成於絶緣膜IL上,同時閘極配線GEW的一部分,埋入閘極用的接觸孔CT2內。將閘極配線GEW之中的埋入閘極用的接觸孔CT2內的部分,稱為「閘極配線GEW的介層部」或「閘極用介層部」。
另外,在此,係針對源極用介層部與源極電極SE形成一體,閘極用介層部與閘極配線GEW形成一體的情況進行説明。作為另一態樣,亦可將源極用介層部(埋入源極用的接觸孔CT1內的導電部)與源極電極SE以不同的步驟形成,並將閘極用介層部(埋入閘極用的接觸孔CT2內的導電部)與閘極配線GEW以不同的步驟形成。
源極電極SE,形成於複數個單位電晶體單元Q1所形成之平面區域(電晶體單元區域)的全部。源極用的接觸孔CT1,在電晶體單元區域中,在俯視下,形成於各溝槽TR之間的半導體基板SB的上方,貫通絶緣膜IL以及n+
型半導體區域NR,接觸孔CT1的底部到達p型半導體區域PR。因此,埋入源極用的接觸孔CT1內的源極用介層部,亦貫通絶緣膜IL以及n+
型半導體區域NR,源極用介層部的底部到達p型半導體區域PR。源極用介層部的下部側面與n+
型半導體區域NR接觸,源極用介層部的底面與p型半導體區域PR接觸,故源極用介層部,與n+
型半導體區域NR以及p型半導體區域PR電連接。
源極用的接觸孔CT1,於電晶體單元區域形成了複數個,透過埋入該等複數個接觸孔CT1的源極用介層部,設置於電晶體單元區域的複數個單位電晶體單元Q1的源極區域(n+
型半導體區域NR)以及通道形成區域(p型半導體區域PR),與共通的源極電極SE電連接。因此,源極焊墊PDS,透過源極電極SE,與設置於電晶體單元區域的複數個單位電晶體單元Q1的源極區域(n+
型半導體區域NR)以及通道形成區域(p型半導體區域PR)電連接。
閘極電極GE以及閘極配線GEW,在俯視下,形成於與源極電極SE並未重疊的位置。例如,閘極配線GEW,在俯視下,於電晶體單元區域的周圍,以包圍電晶體單元區域的方式形成,因此,閘極配線GEW,以包圍源極電極SE的方式形成。閘極電極GE,在俯視下,配置在電晶體單元區域的外側,且與閘極配線GEW形成一體。閘極電極GE,係用來形成閘極焊墊PDG的電極部(導體部),閘極電極GE的寬度,比閘極配線GEW的寬度更大。閘極電極GE與閘極配線GEW,形成一體,因此,閘極電極GE與閘極配線GEW,互相電連接。
在閘極拉出部TGL上形成了閘極用的接觸孔CT2,故閘極用介層部,與閘極拉出部TGL接觸並電連接。因此,閘極電極GE,透過閘極配線GEW、閘極用介層部以及閘極拉出部TGL,與設置於電晶體單元區域的複數個單位電晶體單元Q1的溝槽閘極電極TG電連接。因此,閘極焊墊PDG,透過閘極電極GE以及閘極配線GEW,與設置於電晶體單元區域的複數個單位電晶體單元Q1的溝槽閘極電極TG電連接。
導電體膜CD(源極電極SE、閘極電極GE以及閘極配線GEW),被用來保護表面的絶緣膜(保護膜、鈍化膜)PA所覆蓋。亦即,在絶緣膜IL上,以覆蓋導電體膜CD(源極電極SE、閘極電極GE以及閘極配線GEW)的方式,形成了絶緣膜PA。該絶緣膜PA,係半導體裝置CP的最上層的膜層(絶緣膜)。絶緣膜PA,例如,係由聚醯亞胺樹脂等的樹脂膜所構成。
於絶緣膜PA形成了複數個開口部OP,導電體膜CD的一部分,從各開口部OP露出。在從開口部OP露出的導電體膜CD上,形成了電鍍層PL。電鍍層PL,選擇性地形成於從開口部OP露出的導電體膜CD上,在被絶緣膜PA所覆蓋之部分的導電體膜CD上,並未形成電鍍層PL。電鍍層PL,宜由鎳(Ni)電鍍層PL1與其上的金(Au)電鍍層PL2的堆疊膜所構成。從開口部OP露出的導電體膜CD與形成於其上的電鍍層PL,成為焊墊電極(結合焊墊),源極焊墊PDS,係由從開口部OPS露出的導電體膜CD與其上的電鍍層PL所形成,閘極焊墊PDG,係由從開口部OPG露出的導電體膜CD與其上的電鍍層PL所形成。
亦即,在形成於絶緣膜PA的開口部OP之中,從用來形成源極用的結合焊墊的開口部OPS,源極電極SE露出,並在從開口部OPS露出之部分的源極電極SE上形成了電鍍層PL。利用從絶緣膜PA的開口部OPS露出的部分的源極電極SE與其上的電鍍層PL,形成了源極用的結合焊墊,亦即源極焊墊PDS。另外,在形成於絶緣膜PA的開口部OP之中,從用來形成閘極用的結合焊墊的開口部OPG,閘極電極GE露出,並在從開口部OPG露出之部分的閘極電極GE上,形成了電鍍層PL。利用從絶緣膜PA的開口部OPG露出的部分的閘極電極GE與其上的電鍍層PL,形成了閘極用的結合焊墊,亦即閘極焊墊PDG。在俯視下,開口部OPS被源極電極SE包含在內,且開口部OPG被閘極電極GE包含在內。閘極配線GEW,並未從開口部OP露出,全部被絶緣膜PA所覆蓋。
在俯視下,源極電極SE,以遍及電晶體單元區域的幾乎全部的方式形成,故源極電極SE的面積,比閘極電極GE的面積更大。反映此點,開口部OPS的面積,比開口部OPG的面積更大。開口部OPG、OPS的各自的平面形狀,為例如矩形。另外,閘極電極GE的平面形狀,亦為例如矩形。另外,源極電極SE的平面形狀,亦可為矩形,惟亦可因應電晶體單元區域的平面形狀適當變更之。若列舉開口部OPG、OPS的平面尺寸的一例,則開口部OPG的平面尺寸,在1mm2
以下,開口部OPS的平面尺寸,在9mm2
左右或其以上。
在電鍍層PL之中,鎳電鍍層PL1,具有作為防止在對結合焊墊實行焊料連接時其焊料成分往構成結合焊墊的配線側擴散的障蔽層(焊料障蔽層)的功能,另外,亦具有確保焊料的接合強度的功能。另外,金電鍍層PL2,係為了防止鎳電鍍層PL1的氧化並令焊料的潤濕性良好而設置。另外,當對結合焊墊實行導線結合時,金電鍍層PL2,亦具有令導線容易連接的功能。對結合焊墊實行焊料連接,對應將像上述金屬板MP那樣的導電性的連接構件,透過焊料(對應接合層BD2)接合於源極焊墊PDS的態樣。
在此,將形成於從開口部OPS露出之部分的源極電極SE上的電鍍層PL,稱為源極焊墊用的電鍍層PLS,並將形成於從開口部OPG露出之部分的閘極電極GE上的電鍍層PL,稱為閘極焊墊用的電鍍層PLG。另外,將構成源極焊墊用的電鍍層PLS的鎳電鍍層PL1以及金電鍍層PL2,分別稱為源極焊墊用的鎳電鍍層PLS1以及源極焊墊用的金電鍍層PLS2。另外,將構成閘極焊墊用的電鍍層PLG的鎳電鍍層PL1以及金電鍍層PL2,分別稱為閘極焊墊用的鎳電鍍層PLG1以及閘極焊墊用的金電鍍層PLG2。
因此,在從開口部OPS露出之部分的源極電極SE上,源極焊墊用的鎳電鍍層PLS1與源極焊墊用的金電鍍層PLS2由下往上依序形成,利用該等鎳電鍍層PLS1以及金電鍍層PLS2,形成了源極焊墊用的電鍍層PLS。另外,在從開口部OPG露出之部分的閘極電極GE上,閘極焊墊用的鎳電鍍層PLG1與閘極焊墊用的金電鍍層PLG2由下往上依序形成,利用該等鎳電鍍層PLG1以及金電鍍層PLG2,形成了閘極焊墊用的電鍍層PLG。利用從絶緣膜PA的開口部OPS露出的部分的源極電極SE與其上的源極焊墊用的電鍍層PLS,形成源極焊墊PDS,利用從絶緣膜PA的開口部OPG露出的部分的閘極電極GE與其上的閘極焊墊用的電鍍層PLG,形成閘極焊墊PDG。
在本實施態樣中,形成於從開口部OPS露出之部分的源極電極SE上的電鍍層PL(PLS)的厚度T1,與形成於從開口部OPG露出之部分的閘極電極GE上的電鍍層PL(PLG)的厚度T2,彼此相異,閘極焊墊用的電鍍層PLG的厚度T2,比源極焊墊用的電鍍層PLS的厚度T1更厚(亦即T2>T1)。另外,閘極焊墊用的鎳電鍍層PLG1的厚度T4,比源極焊墊用的鎳電鍍層PLS1的厚度T3更厚(亦即T4>T3)。另外,在源極焊墊用的電鍍層PLS與閘極焊墊用的電鍍層PLG各自之中,鎳電鍍層PL1的厚度,比金電鍍層PL2的厚度更厚。若列舉一例,則鎳電鍍層PL1的厚度,為例如2~3μm左右,金電鍍層PL2的厚度,為例如0.03~0.1μm左右。
另外,在本實施態樣中,閘極用的開口部OPG的面積,比源極用的開口部OPS的面積更小,因此,閘極焊墊用的電鍍層PLG的面積(平面尺寸),比源極焊墊用的電鍍層PLS的面積更小。亦即,閘極焊墊PDG的面積,比源極焊墊PDS的面積更小。另外,當提及開口部OPG、OPS或電鍍層PLG、PLS的面積時,係對應在俯視下的面積。另外,當針對半導體裝置CP的構成要件提及俯視時,係對應在與構成該半導體裝置CP的半導體基板SB的主面大略平行的平面上觀察的態樣。
在該等構造的半導體裝置中,功率電晶體的動作電流,在源極焊墊PDS(源極電極SE)與汲極用的背面電極BE之間流動。亦即,形成於電晶體單元區域的溝槽閘極型的MISFET的動作電流,在半導體基板SB的厚度方向上流動。因此,形成於電晶體單元區域的溝槽閘極型的MISFET,亦為縱型的電晶體。在此,縱型的電晶體,係對應動作電流在半導體基板(SB)的厚度方向上流動的電晶體。
另外,本實施態樣,係針對適用溝槽閘極型的MISFET作為形成於半導體基板SB的半導體元件的態樣進行説明,惟並非僅限於此,亦可將其他種類的半導體元件形成於半導體基板SB。
例如,亦可於半導體基板SB,取代溝槽閘極型的MISFET,形成溝槽閘極型的IGBT。當適用溝槽閘極型的IGBT時,係於半導體基板SB的背面側形成集極用的半導體區域(p型半導體區域)。另外,當適用溝槽閘極型的IGBT時,背面電極BE發揮作為集極電極的功能,上述n+
型半導體區域NR發揮作為射極用的半導體區域的功能,上述源極電極SE發揮作為射極電極的功能,上述源極焊墊PDS發揮作為射極焊墊(射極用結合焊墊)的功能。
另外,亦可於半導體基板SB,取代溝槽閘極型的MISFET,形成LDMOSFET(Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor,橫向擴散金屬氧化物半導體場效電晶體)等。
另外,當在半導體基板SB的主面上,形成包含複數個配線層在內的配線構造(多層配線構造)時,亦可適用本實施態樣。此時,係於該配線構造所包含的複數個配線層之中的最上層的配線層,形成結合焊墊。
圖15以及圖16,係將半導體裝置CP封裝體化的上述半導體裝置PKG的主要部位剖面圖。於圖15,顯示出相當於圖11的剖面,於圖16,顯示出相當於上述圖12的剖面。
如參照上述圖3~圖9所説明的,金屬板MP透過由焊料所構成的接合層BD2與源極焊墊PDS接合。因此,於圖15,顯示出金屬板MP透過焊料SD(接合層BD2)與源極焊墊PDS接合的狀態。焊料SD,係對應上述接合層BD2的構件。另外,如參照上述圖3~圖9所説明的,導線WA與閘極焊墊PDG接合。因此,於圖16,顯示出導線WA與閘極焊墊PDG接合的狀態。
另外,於圖15,顯示出在焊料SD與鎳電鍍層PLS1之間,殘留金電鍍層PLS2的態樣。作為另一態樣,亦可為構成源極焊墊PDS的最上層的金電鍍層PLS2,與焊料SD發生反應而被導入焊料SD內並合金化的態樣。此時,構成源極焊墊PDS的最上層的金電鍍層PLS2,形成與焊料SD混合的狀態,實行了焊料連接(焊料SD所致之金屬板MP的連接)之後的源極焊墊PDS的最上層,並非金電鍍層PLS2,而係鎳電鍍層PLS1。
<關於半導體裝置(半導體晶片)的製造步驟> 參照圖17~圖34説明本發明一實施態樣之半導體裝置(半導體晶片)CP的製造步驟。圖17~圖34,係本實施態樣之半導體裝置(半導體晶片)的製造步驟中的主要部位剖面圖。另外,在圖17~圖34之中,於圖17~圖23、圖25、圖27、圖29、圖31以及圖33,顯示出相當於上述圖11的剖面,於圖24、圖26、圖28、圖30、圖32以及圖34,顯示出相當於上述圖12的剖面。
欲製造半導體裝置,首先,如圖17所示的,準備由例如n型單晶矽等所構成的半導體基板SB(半導體晶圓)。作為半導體基板SB,亦可使用所謂的磊晶晶圓。
接著,如圖18所示的,於半導體基板SB的主面,形成溝槽TR。溝槽TR,可用微影技術以及蝕刻技術形成。
接著,用例如熱氧化法等,在溝槽TR的側面以及底面上,還有,在半導體基板SB的頂面上,形成由較薄之氧化矽膜等所構成的絶緣膜GF1。
接著,在半導體基板SB的主面全面上,以填埋溝槽TR內部的方式,用CVD法等形成導入雜質(例如n型雜質)以設置成低電阻率的多晶矽膜(摻雜多晶矽膜)等的導電膜PS。
接著,將覆蓋形成閘極拉出部TGL的預定區域並露出除此以外的區域的光阻圖案(圖中未顯示)形成於導電膜PS上,然後,以該光阻圖案作為蝕刻遮罩,用異向性蝕刻技術回蝕導電膜PS。藉由該回蝕,在溝槽TR內與上述光阻圖案之下殘留導電膜PS,並將除此以外的導電膜PS除去。之後,光阻圖案被除去。於圖19,顯示出該階段。殘留在溝槽TR內的絶緣膜GF1成為閘極絶緣膜GF,殘留在溝槽TR內的導電膜PS成為溝槽閘極電極TG。另外,殘留在上述光阻圖案之下的導電膜PS,成為閘極拉出部TGL,惟該閘極拉出部TGL,與溝槽閘極電極TG形成一體。另外,有時也會在導電膜PS的回蝕步驟,將半導體基板SB的頂面的絶緣膜GF1除去。
接著,如圖20所示的,對半導體基板SB的主面注入p型的雜質離子等,藉此,形成p型半導體區域PR。p型半導體區域PR,形成於半導體基板SB的上層部。
接著,對半導體基板SB的主面注入n型的雜質離子等,藉此,形成n+
型半導體區域NR。n+
型半導體區域NR的深度,比p型半導體區域PR的深度更淺,n+
型半導體區域NR形成於p型半導體區域PR的上部。n+
型半導體區域NR以及p型半導體區域PR,形成得比溝槽TR更淺,故溝槽TR,形成貫通n+
型半導體區域NR以及p型半導體區域PR,且端部位在其下的半導體基板SB之中的狀態。
接著,實行用來令到此為止所導入之雜質活性化的熱處理,亦即活性化退火處理。
接著,如圖21所示的,在半導體基板SB的主面上(主面全面上),以覆蓋溝槽閘極電極TG以及閘極拉出部TGL的方式,形成絶緣膜IL作為層間絶緣膜。
接著,如圖22所示的,以用微影法形成於絶緣膜IL的光阻圖案(圖中未顯示)作為蝕刻遮罩,蝕刻絶緣膜IL,然後,蝕刻半導體基板SB,藉此,形成源極用的接觸孔CT1。源極用的接觸孔CT1,形成於在俯視下相鄰的溝槽TR之間。在源極用的接觸孔CT1的底面,p型半導體區域PR露出,在源極用的接觸孔CT1的側面的下部,n+
型半導體區域NR露出。另外,亦可在形成了源極用的接觸孔CT1之後,對從源極用的接觸孔CT1的底面露出的p型半導體區域PR注入p型雜質離子。
接著,以用微影法形成於絶緣膜IL上的另一光阻圖案(圖中未顯示)作為蝕刻遮罩,蝕刻絶緣膜IL,藉此,在閘極拉出部TGL之上形成閘極用的接觸孔CT2。
接著,如圖23以及圖24所示的,在半導體基板SB的主面全面上,亦即,在包含接觸孔CT1、CT2內部在內的絶緣膜IL上,用濺鍍法等形成以鋁(Al)為主成分的導電體膜(金屬膜)CD。
接著,如圖25以及圖26所示的,用微影技術以及蝕刻技術令導電體膜CD形成圖案,藉此,形成源極電極SE、閘極電極GE以及閘極配線GEW。具體而言,在導電體膜CD上用微影技術形成光阻圖案(圖中未顯示),然後,將該光阻圖案當作蝕刻遮罩使用,蝕刻導電體膜CD。藉此,形成由形成圖案之導電體膜CD所構成的源極電極SE、閘極電極GE以及閘極配線GEW,之後,將光阻圖案除去。如上所述的,閘極電極GE與閘極配線GEW,互相連結,形成一體。
源極電極SE,形成於絶緣膜IL上,同時源極電極SE的一部分(源極用介層部),埋入源極用的接觸孔CT1內。另外,閘極電極GE,形成於絶緣膜IL上,同時閘極電極GE的一部分(閘極用介層部),埋入閘極用的接觸孔CT2內。
作為另一態樣,亦可將源極用介層部與源極電極SE以不同的步驟形成,並將閘極用介層部與閘極配線GEW以不同的步驟形成。此時,係在形成了接觸孔CT1、CT2之後,在絶緣膜IL上,以填埋接觸孔CT1、CT2內部的方式形成導電膜,然後,用CMP法等將接觸孔CT1、CT2的外部的導電膜除去,藉此,形成埋入接觸孔CT1、CT2內的導電性栓塞。埋入接觸孔CT2內的導電性栓塞相當於閘極用介層部,埋入接觸孔CT1內的導電性栓塞相當於射極用介層部。之後,只要在埋入了導電性栓塞的絶緣膜IL上形成導電體膜CD,然後,用微影技術以及蝕刻技術令該導電體膜CD形成圖案,以形成源極電極SE、閘極電極GE以及閘極配線GEW即可。
接著,如圖27以及圖28所示的,在半導體基板SB的主面上(主面全面上),亦即在絶緣膜IL上,以覆蓋源極電極SE、閘極電極GE以及閘極配線GEW的方式,形成絶緣膜PA。絶緣膜PA,例如,係由聚醯亞胺系樹脂等的樹脂膜所構成。在形成了絶緣膜PA的階段,源極電極SE、閘極電極GE以及閘極配線GEW,全部被絶緣膜PA所覆蓋。
接著,如圖29以及圖30所示的,令絶緣膜PA形成圖案,藉此,於絶緣膜PA形成開口部OP(OPG、OPS)。
絶緣膜PA的形成圖案步驟,可藉由將絶緣膜PA形成為感光性樹脂膜,並在由感光性樹脂所構成的絶緣膜PA上形成光阻圖案(圖中未顯示),然後,對該由感光性樹脂所構成的絶緣膜PA進行曝光、顯影處理,藉此,將成為開口部OP的部分的絶緣膜PA選擇性地除去,而實行之。或者,絶緣膜PA的形成圖案步驟,可藉由在絶緣膜PA上形成光阻圖案(圖中未顯示),然後,將該光阻圖案當作蝕刻遮罩使用,蝕刻絶緣膜PA,藉此,將成為開口部OP的部分的絶緣膜PA選擇性地除去,而實行之。此時,絶緣膜PA,亦可並非感光性樹脂膜。在開口部OP之中,開口部OPS形成於源極電極SE上,開口部OPG形成於閘極電極GE上,源極電極SE在開口部OPS的底部露出,閘極電極GE在開口部OPG的底部露出。在俯視下,開口部OPS被源極電極SE包含在內,開口部OPG被閘極電極GE包含在內。開口部OPS與開口部OPG,並未連結,彼此分離。
接著,如圖31以及圖32所示的,在從開口部OP露出的導電體膜CD上,亦即,在從開口部OPS露出的源極電極SE上,以及,在從開口部OPG露出的閘極電極GE上,用電鍍法形成電鍍層PL。電鍍層PL,宜由鎳電鍍層PL1與其上的金電鍍層PL2的堆疊膜所構成,可用電鍍法(宜為無電解電鍍法)形成。亦即,在從開口部OP露出的導電體膜CD上,用電鍍法(宜為無電解電鍍法)依序形成鎳電鍍層PL1與金電鍍層PL2,藉此,便可形成由鎳電鍍層PL1與金電鍍層PL2的堆疊膜所構成的電鍍層PL。藉由使用電鍍法,便可在從開口部OP露出的導電體膜CD上選擇性地形成電鍍層PL。在被絶緣膜PA所覆蓋之部分的導電體膜CD上,或在絶緣膜PA上,並不會形成電鍍層PL。
接著,因應需要,研削或研磨半導體基板SB的背面,令半導體基板SB的厚度減薄。
接著,如圖33以及圖34所示的,於半導體基板SB的整個背面形成背面電極BE。背面電極BE,例如,係由從靠近半導體基板SB的背面的該側開始依序為鈦(Ti)膜、鎳(Ni)膜以及金(Au)膜的堆疊金屬膜等所構成,可用例如蒸鍍法等形成。
之後,利用切割步驟等分割(分離、切斷)半導體基板SB,以從半導體基板SB取得各個半導體晶片(半導體裝置CP)。
以該等方式,製造出本實施態樣的半導體裝置CP。
<關於電鍍層PL形成步驟> 參照圖35以及圖36,針對上述電鍍層PL的形成步驟,更詳細地進行説明。圖35,係表示電鍍層PL形成步驟的詳細內容的流程圖,圖36,係電鍍層PL形成步驟的説明圖。於圖36,係以示意方式顯示出處理裝置(電鍍裝置)的剖面圖,惟為了令圖式容易檢視,省略了影線。
上述電鍍層PL的形成步驟所使用的處理裝置(電鍍裝置)MS,係批次式的處理裝置。處理裝置MS,具有複數個處理槽(藥液槽)BH,惟為了簡化圖式,圖36,係顯示出在處理裝置MS所具有的複數個處理槽BH之中的鎳電鍍層PL1形成步驟所使用的處理槽BH1作為代表。另外,在圖36中,係以箭號示意地表示藥液的流向。
處理裝置MS的各處理槽BH,可從處理槽BH的底部將藥液導入處理槽BH內。另外,相對於各處理槽BH設置了外槽(回收槽)GB。在各處理槽BH中,從處理槽BH的底部導入的藥液,會儲存在該處理槽BH內,從處理槽BH的上部溢出(溢流)的藥液,會被外槽GB回收。另外,在各處理槽BH內,配置了可保持晶圓的晶圓保持部WH。在各處理槽BH內,可於晶圓保持部WH,配置(收納)複數個晶圓(半導體晶圓)WF。另外,在此所使用的晶圓WF,對應上述半導體基板SB。另外,處理裝置MS,雖在圖中並未顯示,惟係配置在連接了排氣用配管的處理室內。
在各處理槽BH中,將所欲處理的複數個晶圓WF,浸漬在處理槽BH內所儲存的藥液中,並配置於晶圓保持部,藉此,令複數個晶圓WF浸漬在處理槽BH內的藥液中的狀態維持既定的時間,以實行對各晶圓WF的處理(圖35所示的其中任一項的處理)。圖35的各步驟的處理,各自可在用來實行該步驟的專用處理槽BH實行之。另外,在各處理槽BH中,在實行了藥液處理之後,可對晶圓WF實行純水洗淨處理。
茲針對上述電鍍層PL的形成步驟,具體進行説明。
在如上所述的於絶緣膜PA形成了開口部OP(OPG、OPS)之後,實行例如Ar(氬)電漿處理等,藉此,將從開口部OP露出之導電體膜CD的表面的自然氧化膜或有機物除去。該Ar電漿處理,可用電漿處理裝置(圖中未顯示)實行之。
接著,在處理裝置MS,對晶圓WF實行脱脂處理(脱脂洗淨處理)(圖35的步驟S1)。脱脂處理,可在脱脂處理用的處理槽BH實行之。利用該脱脂處理,令從開口部OP露出之導電體膜CD的表面潔淨化。在脱脂處理之後,對晶圓WF實行純水洗淨處理。
接著,實行酸洗淨(圖35的步驟S2a),之後,實行第1鋅酸鹽處理(圖35的步驟S2)。
步驟S2的第1鋅酸鹽處理,令鋅酸鹽液接觸從開口部OP露出之導電體膜CD的表面,利用A1(鋁)與Zn(鋅)的置換反應,於從開口部OP露出之導電體膜CD的表面形成Zn膜(鋅膜)。具體而言,係將晶圓WF(半導體基板SB)浸漬於第1鋅酸鹽處理用的處理槽BH內所儲存的鋅酸鹽液,以實行第1鋅酸鹽處理,而於從開口部OP露出之導電體膜CD的表面形成Zn膜。
接著,用稀硝酸等實行酸洗淨(圖35的步驟S3),將從開口部OP露出之導電體膜CD的表面的Zn膜剝離。
接著,實行第2鋅酸鹽處理(圖35的步驟S4)。步驟S4的第2鋅酸鹽處理,令鋅酸鹽液接觸從開口部OP露出之導電體膜CD的表面,利用A1(鋁)與Zn(鋅)的置換反應,於從開口部OP露出之導電體膜CD的表面形成Zn膜(鋅膜)。具體而言,係將晶圓WF(半導體基板SB)浸漬於第2鋅酸鹽處理用的處理槽BH內所儲存的鋅酸鹽液,以實行第2鋅酸鹽處理,而於從開口部OP露出之導電體膜CD的表面形成Zn膜。藉由像這樣重複2次鋅酸鹽處理,便可形成緻密且均勻的Zn膜。
接著,實行Ni電鍍處理(圖35的步驟S5),以Zn膜(圖中未顯示)的Zn為核,令電鍍膜(Ni膜)成長。亦即,令形成了Zn膜(圖中未顯示)的導電體膜CD的表面(從開口部OP露出的表面),與Ni電鍍用的電鍍液接觸,藉此,形成鎳電鍍層PL1。具體而言,使用次亞磷酸系的電鍍液作為電鍍液,將晶圓WF(半導體基板SB)浸漬於Ni電鍍用的處理槽BH1內所儲存的85℃左右的電鍍液,以實行電鍍處理(Ni電鍍處理),而形成例如2.5μm左右的膜厚的鎳電鍍層PL1。該鎳電鍍層PL1,選擇性地在從開口部OP露出之導電體膜CD的表面上成長。因此,在步驟S5,在從開口部OPS露出的源極電極SE上,形成了源極焊墊用的鎳電鍍層PLS1,在從開口部OPG露出的閘極電極GE上,形成了閘極焊墊用的鎳電鍍層PLG1。
鎳電鍍層PL1,宜為含磷(P)的無電解鎳電鍍層。作為所使用之電鍍液,可例示出含有硫酸鎳,並含有次亞磷酸鹽作為還原劑的電鍍液。電鍍液的溫度,可為例如80~90℃左右,pH可為例如4~5左右,Ni濃度可為例如5~6.5g/l(克/公升)左右。
接著,實行Au(金)電鍍處理(圖35的步驟S6),令電鍍膜(Au膜)成長。
作為步驟S6的Au電鍍處理,首先,可實行置換Au電鍍處理(圖35的步驟S6a)。在步驟S6a的置換Au電鍍處理中,令鎳電鍍層PL1的表面,與Au電鍍用的電鍍液接觸,藉此,形成金電鍍層(Au電鍍層)。具體而言,係將晶圓WF(半導體基板SB)浸漬於置換Au電鍍用的處理槽BH內所儲存的置換Au電鍍用的電鍍液,以實行電鍍處理(Au電鍍處理),而在鎳電鍍層PL1上形成金電鍍層。該金電鍍層,選擇性地在從開口部OP露出之導電體膜CD上所形成的鎳電鍍層PL1上成長。作為此時的置換Au電鍍,可適用無氰化物型的置換Au電鍍。另外,無氰化物型的置換Au電鍍,係使用不含有氰化合物的電鍍液。作為所使用之電鍍液,可例示出含有亞硫酸金鈉的電鍍液。電鍍液的溫度,可為例如60~70℃左右,pH可為例如8~9左右,Au濃度可為例如1.5~2.5g/l(克/公升)左右。
置換Au電鍍,通常,在置換反應完成之後Au膜的成膜便停止,故當欲將Au膜形成得比較厚(例如0.05μm以上)時,可在步驟S6a的置換Au電鍍處理之後,實行還原Au電鍍處理(圖35的步驟S6b)。亦即,在步驟S6a的置換Au電鍍處理所形成的Au膜之上用步驟S6b的還原Au電鍍處理形成具有吾人所期望的膜厚的Au膜。在步驟S6b的還原Au電鍍處理中,令步驟S6a所形成之Au膜的表面,與還原Au電鍍用的電鍍液接觸,藉此,更進一步形成金電鍍層。具體而言,係將晶圓WF(半導體基板SB)浸漬於還原Au電鍍用的處理槽BH內所儲存的還原Au電鍍用的電鍍液,以實行電鍍處理(Au電鍍處理),而在步驟S6a所形成的Au膜上更進一步形成金電鍍層。作為此時的還原Au電鍍,可適用無氰化物型的還原Au電鍍。另外,無氰化物型的還原Au電鍍,係使用不含有氰化合物的電鍍液。作為所使用的電鍍液,可例示出含有亞硫酸金鈉,更含有還原劑與安定劑的電鍍液。電鍍液的溫度,可為例如45~55℃左右,pH可為例如7~7.5左右,Au濃度可為例如2.5~3.5g/l(克/公升)左右。
當實行步驟S6a與步驟S6b雙方時,係利用步驟S6a所形成的Au膜與步驟S6b所形成的Au膜,形成上述金電鍍層PL2。另外,當在實行了步驟S6a之後並未實行步驟S6b時,則係利用步驟S6a所形成的Au膜,形成上述金電鍍層PL2。因此,步驟S6,在鎳電鍍層PLS1上,形成源極焊墊用的金電鍍層PLS2,並在鎳電鍍層PLG1上,形成閘極焊墊用的金電鍍層PLG2。
<關於檢討的歷程> 本發明人,針對結合焊墊進行檢討。在半導體晶片所具備的複數個結合焊墊中,有時面積會不同。亦即,有時會於半導體晶片,設置小面積的結合焊墊與大面積的結合焊墊。例如,在內建功率MISFET的半導體晶片中,源極用的結合焊墊(亦即源極焊墊)的面積,比閘極用的結合焊墊(亦即閘極焊墊)的面積,更大許多。如是,在將內建功率MISFET的半導體晶片封裝體化時,便可將導線連接於閘極焊墊,同時將金屬板連接於源極焊墊。功率MISFET會流通較大的電流,若將金屬板連接於源極焊墊,則相較於導線,金屬板的電阻較低,該金屬板,可發揮作為流通較大之電流的電流路徑的功能,故可降低流通較大之電流的電流路徑的電阻,並可減少導通損失。
結合焊墊,於表面具有電鍍層。連接導線的結合焊墊,若表面的電鍍層較薄,則可能會因為導線結合時的物理性衝撃,而於該電鍍層產生裂縫。另一方面,連接金屬板的結合焊墊,即使表面的電鍍層較薄,也不會在連接金屬板時發生裂縫。這是因為,當將金屬板連接於結合焊墊時,比起將導線連接於結合焊墊的情況而言,對結合焊墊所施加之物理性衝撃較小的關係。若於結合焊墊的表面的電鍍層發生裂縫,則半導體裝置(半導體封裝體)的可靠度會降低,故防止於結合焊墊的表面的電鍍層發生裂縫,為吾人所期望。
連接導線的結合焊墊,若令表面的電鍍層增厚,則對導線結合時的壓力(物理性衝撃)的耐久性會提高,故不易因為導線結合時的物理性衝撃而發生裂縫。另一方面,面積較大的結合焊墊(連接金屬板的結合焊墊),若令表面的電鍍層增厚,則該電鍍層的應力會變大,可能會發生翹曲(半導體基板的翹曲)的問題。這是因為,相較於連接導線的結合焊墊,連接金屬板的結合焊墊其面積較大,結合焊墊的面積越大,電鍍層的面積也越大,該電鍍層的應力的影響也會變大的關係。若因為電鍍層的應力而於半導體基板發生翹曲,則可能會在各步驟發生不良情況。此可能會導致所製造之半導體裝置(半導體晶片或半導體封裝體)的可靠度降低,或者,半導體裝置的製造產能降低,故防止因為結合焊墊的表面的電鍍層而發生翹曲,為吾人所期望。
圖37以及圖38,係本發明人所檢討之檢討例的半導體裝置(半導體晶片)的主要部位剖面圖,於圖37,顯示出相當於上述圖11的剖面,於圖38,顯示出相當於上述圖12的剖面。
圖37以及圖38的檢討例的態樣,在從開口部OPS露出之部分的源極電極SE上,與從開口部OPG露出之部分的閘極電極GE上,形成了相當於上述電鍍層PL的電鍍層PL100。另外,電鍍層PL100,係由鎳(Ni)電鍍層PL101與其上的金(Au)電鍍層PL102的堆疊膜所構成。
在此,在圖37以及圖38的檢討例中,將形成於從開口部OPS露出之部分的源極電極SE上的電鍍層PL100,稱為源極焊墊(PDS101)用的電鍍層PLS100,將形成於從開口部OPG露出之部分的閘極電極GE上的電鍍層PL100,稱為閘極焊墊(PDG101)用的電鍍層PLG100。另外,在圖37以及圖38的檢討例中,將構成源極焊墊用的電鍍層PLS100的鎳電鍍層PL101以及金電鍍層PL102,分別稱為源極焊墊用的鎳電鍍層PLS101以及源極焊墊用的金電鍍層PLS102。另外,在圖37以及圖38的檢討例中,將構成閘極焊墊用的電鍍層PLG100的鎳電鍍層PL101以及金電鍍層PL102,分別稱為閘極焊墊用的鎳電鍍層PLG101以及閘極焊墊用的金電鍍層PLG102。
圖37以及圖38的檢討例的半導體裝置與上述圖11以及圖12的本實施態樣的半導體裝置的不同點,在於結合焊墊用的電鍍層的厚度。
亦即,在圖37以及圖38的檢討例的情況下,源極焊墊用的電鍍層PLS100的厚度T101,與閘極焊墊用的電鍍層PLG100的厚度T102,彼此相同(T101=T102)。另外,源極焊墊用的鎳電鍍層PLS101的厚度T103,與閘極焊墊用的鎳電鍍層PLG101的厚度T104,彼此相同(T103=T104),另外,源極焊墊用的金電鍍層PLS102的厚度,與閘極焊墊用的金電鍍層PLG102的厚度,彼此相同。
在圖37以及圖38的檢討例的情況下,源極焊墊用的電鍍層PLS100的厚度T101與閘極焊墊用的電鍍層PLG100的厚度T102彼此相同,故當令閘極焊墊用的電鍍層PLG100的厚度T102減薄時,源極焊墊用的電鍍層PLS100的厚度T101也必然減薄。另外,當令閘極焊墊用的電鍍層PLG100的厚度T102增厚時,源極焊墊用的電鍍層PLS100的厚度T101也必然增厚。
然而,在圖37以及圖38的檢討例中,若令閘極焊墊用的電鍍層PLG100的厚度T102與源極焊墊用的電鍍層PLS100的厚度T101減薄,則在將導線連接於閘極焊墊PDG101時,可能會因為導線結合時的物理性衝撃,而於閘極焊墊用的電鍍層PLG100產生裂縫。
另一方面,在圖37以及圖38的檢討例中,若令閘極焊墊用的電鍍層PLG100的厚度T102與源極焊墊用的電鍍層PLS100的厚度T101增厚,以令導線結合時的裂縫變得不容易發生,則可能會因為大面積的源極焊墊用的電鍍層PLS100的應力,而發生翹曲(半導體基板的翹曲)的問題。
<關於主要特徴與功效> 本實施態樣之半導體裝置CP,具有:半導體基板SB;形成於半導體基板SB的主面上的層間絶緣膜(在此為絶緣膜IL);形成於該層間絶緣膜(IL)上的源極電極SE與閘極電極GE;以及在該層間絶緣膜(IL)上,以覆蓋源極電極SE以及閘極電極GE的方式形成的絶緣膜PA。在此,源極電極SE,係源極焊墊PDS(第1焊墊)用的導電膜圖案(第1導電膜圖案),閘極電極GE,係閘極焊墊PDG(第2焊墊)用的導電膜圖案(第2導電膜圖案)。於絶緣膜PA,形成了露出源極電極SE的一部分的源極焊墊PDS(第1焊墊)用的開口部OPS(第1開口部),以及露出閘極電極GE的一部分的閘極焊墊PDG(第2焊墊)用的開口部OPG(第2開口部)。在從絶緣膜PA的開口部OPS露出的部分的源極電極SE上,形成了源極焊墊用的電鍍層PLS(第1電鍍層),在從絶緣膜PA的開口部OPG露出的部分的閘極電極GE上,形成了閘極焊墊用的電鍍層PLG(第2電鍍層)。利用從絶緣膜PA的開口部OPS露出之部分的源極電極SE(第1導電膜圖案)與其上的電鍍層PLS(第1電鍍層),形成源極焊墊PDS(第1焊墊)。另外,利用從絶緣膜PA的開口部OPG露出之部分的閘極電極GE(第2導電膜圖案)與其上的電鍍層PLG(第2電鍍層),形成閘極焊墊PDG(第2焊墊)。
本實施態樣的主要特徴的其中之一,係開口部OPG(第2開口部)的面積,比開口部OPS(第1開口部)的面積更小。換言之,閘極焊墊PDG(第2焊墊)的面積,比源極焊墊PDS(第1焊墊)的面積更小。本實施態樣的主要特徴的其中另一個,係閘極焊墊用的電鍍層PLG(第2電鍍層)的厚度T2,比源極焊墊用的電鍍層PLS(第1電鍍層)的厚度T1更厚(亦即T2>T1)。
在本實施態樣中,閘極焊墊用的電鍍層PLG的厚度T2,比源極焊墊用的電鍍層PLS的厚度T1更厚,藉此,便可針對面積較小的閘極焊墊PDG,令電鍍層PL(PLG)的厚度增厚,並針對面積較大的源極焊墊PDS,令電鍍層PL(PLS)的厚度減薄。
若針對面積較小的閘極焊墊PDG,令電鍍層PL(PLG)的厚度增厚,則對導線結合時的壓力(物理性衝撃)的耐久性會提高,故會變得不易因為導線結合時的物理性衝撃而發生裂縫。因此,針對面積較小的閘極焊墊PDG,可抑制或防止在導線結合時於電鍍層PL(PLG)發生裂縫。因此,可令半導體裝置(包含半導體晶片在內的半導體封裝體)的可靠度提高。
另一方面,若針對面積比閘極焊墊PDG更大的源極焊墊PDS,令電鍍層PL(PLS)的厚度減薄,則可抑制該電鍍層PL(PLS)的應力,並可改善可能會因為電鍍層PL(PLS)的應力而產生的問題。例如,可抑制或防止因為電鍍層PL(PLS)的應力而發生半導體基板的翹曲。藉此,便可防止在各步驟發生不良情況。因此,可令所製造之半導體裝置(半導體晶片或半導體封裝體)的可靠度提高。另外,可令半導體裝置的製造產能提高。
在閘極焊墊PDG與源極焊墊PDS之中,就面積較大的源極焊墊PDS而言,其電鍍層PL(PLS)的面積較大,因此,該電鍍層PL(PLS)的應力變大,容易因為電鍍層PL(PLS)的應力而發生問題(例如半導體基板的翹曲的問題)。於是,本實施態樣,在閘極焊墊PDG與源極焊墊PDS之中,針對面積較大的源極焊墊PDS,為了抑制電鍍層PL(PLS)的應力,而令電鍍層PL(PLS)的厚度減薄。另外,在閘極焊墊PDG與源極焊墊PDS之中,就面積較小的閘極焊墊PDG而言,其電鍍層PL(PLG)面積較小,因此,該電鍍層PL(PLG)的應力受到抑制,故不易因為電鍍層PL(PLG)的應力而發生問題(例如半導體基板的翹曲的問題)。於是,本實施態樣,在閘極焊墊PDG與源極焊墊PDS之中,針對面積較小的閘極焊墊PDG,令電鍍層PL(PLG)的厚度增厚,藉此,提高對導線結合時的壓力(物理性衝撃)的耐久性。
針對面積較大的源極焊墊用的電鍍層PLS令厚度減薄,針對面積較小的閘極焊墊用的電鍍層PLG,令其比源極焊墊用的電鍍層PLS更厚,藉此,便可抑制可能會影響源極焊墊用的電鍍層PLS的應力,另外,就閘極焊墊PDG而言可提高導線結合時的耐久性。藉此,便可令半導體裝置的綜合可靠度提高。另外,可令半導體裝置的製造產能提高。
另外,電鍍層PL,包含形成於從開口部OP露出之部分的導電體膜CD上的鎳電鍍層PL1。亦即,源極焊墊用的電鍍層PLS,包含形成於從開口部OPS露出之部分的源極電極SE上的鎳電鍍層PLS1,另外,閘極焊墊用的電鍍層PLG,包含形成於從開口部OPG露出之部分的閘極電極GE上的鎳電鍍層PLG1。閘極焊墊用的鎳電鍍層PLG1的厚度T4,宜比源極焊墊用的鎳電鍍層PLS1的厚度T3更厚(T4>T3)。
鎳(Ni)係較硬的金屬材料,相較之下,鋁(Al)係較軟的金屬材料。因此,鎳電鍍層PL1,比導電體膜CD更硬,導電體膜CD,比鎳電鍍層PL1更軟。因此,鎳電鍍層PL1,係在導線結合時因為物理性衝撃而發生裂縫的風險較高的膜層。因此,在導線結合時受到物理性衝撃的導線連接用的結合焊墊(在此為閘極焊墊PDG)中,令鎳電鍍層PL1(PLG1)增厚,以提高對導線結合時的壓力(物理性衝撃)的耐久性,為吾人所期望。另外,鎳電鍍層PL1,係「由較硬的金屬材料所構成,故當應力變大時,容易發生半導體基板的翹曲」的膜層。因此,若在面積較大的結合焊墊(在此為源極焊墊PDS)中,令鎳電鍍層PL1(PLS1)增厚,則該鎳電鍍層PL1(PLS1)的應力會變大,可能會發生半導體基板的翹曲,故令鎳電鍍層PL1(PLS1)的厚度減薄,為吾人所期望。因此,當結合焊墊用的電鍍層PL包含鎳電鍍層PL1時,因應結合焊墊控制該鎳電鍍層PL1的厚度,特別重要。
於是,本實施態樣,宜令面積較小的閘極焊墊用的鎳電鍍層PLG1的厚度T4,比面積較大的源極焊墊用的鎳電鍍層PLS1的厚度T3更厚(亦即T4>T3)。亦即,本實施態樣,令閘極焊墊用的電鍍層PLG,比源極焊墊用的電鍍層PLS更厚,尤其,令閘極焊墊用的鎳電鍍層PLG1,比源極焊墊用的鎳電鍍層PLS1更厚。針對面積較小的閘極焊墊PDG,尤其,令鎳電鍍層PL1(PLG1)的厚度增厚,藉此,便可有效地提高對導線結合時的壓力(物理性衝撃)的耐久性,並可確實地抑制或防止在導線結合時於鎳電鍍層PL1(PLG1)發生裂縫。另一方面,針對面積比閘極焊墊PDG更大的源極焊墊PDS,令鎳電鍍層PL1(PLS1)的厚度減薄,藉此,便可抑制該鎳電鍍層PL1(PLS1)的應力,並可改善可能會因為鎳電鍍層PL1(PLS1)的應力而產生的問題。例如,可確實地抑制或防止因為鎳電鍍層PL1(PLS1)的應力而發生半導體基板的翹曲。因此,可確實地令所製造之半導體裝置(包含半導體晶片在內的半導體封裝體)的可靠度提高。
金(Au),相較於鎳(Ni)係較軟的金屬材料。另外,在各結合焊墊中,金電鍍層PL2的厚度,比鎳電鍍層PL1的厚度更薄許多。因此,相較於鎳電鍍層PL1,就金電鍍層PL2而言,關於鎳電鍍層PL1可能會發生的問題(導線結合時的裂縫或半導體基板的翹曲的問題),其發生的風險較小。因此,因應結合焊墊而控制鎳電鍍層PL1的厚度很重要,只要令閘極焊墊用的鎳電鍍層PLG1的厚度,比源極焊墊用的鎳電鍍層PLS1的厚度更厚即可。因此,閘極焊墊用的金電鍍層PLG2的厚度,與源極焊墊用的金電鍍層PLS2的厚度,可彼此相同,或者亦可彼此相異,另外,閘極焊墊用的金電鍍層PLG2的厚度,亦可比源極焊墊用的金電鍍層PLS2的厚度更厚。
閘極焊墊用的鎳電鍍層PLG1的厚度T4,若在源極焊墊用的鎳電鍍層PLS1的厚度T3的1.2倍以上(亦即T4≧T3×1.2),為較佳的態樣,若在源極焊墊用的鎳電鍍層PLS1的厚度T3的1.3倍以上(亦即T4≧T3×1.3),為更佳的態樣。
將鎳電鍍層以無電解電鍍法形成時的厚度的差異,頂多為5%左右。在本實施態樣中,令閘極焊墊用的鎳電鍍層PLG1的厚度,積極地(刻意地)比源極焊墊用的鎳電鍍層PLS1的厚度更厚,宜在源極焊墊用的鎳電鍍層PLS1的厚度的1.2倍以上,更宜在源極焊墊用的鎳電鍍層PLS1的厚度的1.3倍以上。藉此,便可有效地發揮令閘極焊墊用的鎳電鍍層PLG1的厚度增厚的功效(提高導線結合時的耐久性),以及令源極焊墊用的鎳電鍍層PLS1的厚度減薄的功效(防止半導體基板的翹曲)。
另外,本實施態樣,針對面積較小的結合焊墊(在此為閘極焊墊PDG),令電鍍層PL(尤其是鎳電鍍層PL1)的厚度增厚,針對面積較大的結合焊墊(在此為源極焊墊PDS),令電鍍層PL(尤其是鎳電鍍層PL1)的厚度減薄,藉此,便可獲得如上所述的功效。面積較小的結合焊墊(在此為閘極焊墊PDG)與面積較大的結合焊墊(在此為源極焊墊PDS)的面積比越大,該等功效越顯著。因此,本實施態樣,若適用於開口部OPS的面積在開口部OPG的面積的9倍以上的態樣,更為適當。若是如此,因應結合焊墊而控制電鍍層PL(尤其是鎳電鍍層PL1)的厚度所得到的功效會變得非常大。
另外,源極焊墊PDS的面積,與開口部OPS的面積大致一致,另外,閘極焊墊PDG的面積,與開口部OPG的面積大致一致。因此,「開口部OPS的面積在開口部OPG的面積的9倍以上」此特徵點,對應「源極焊墊PDS的面積在閘極焊墊PDG的面積的9倍以上」此特徵點。亦即,本實施態樣,若適用於源極焊墊PDS的面積在閘極焊墊PDG的面積的9倍以上的態樣,更為適當。
另外,當半導體裝置CP,除了閘極焊墊PDG以外,亦更具有比源極焊墊PDS更小且用來連接導線的焊墊(例如上述圖10的焊墊PD1)時,該導線連接用的焊墊(PD1)的電鍍層PL的構造(層構造、材料以及厚度),可與閘極焊墊用的電鍍層PLG相同。藉此,便可令導線連接用的焊墊(PDG、PD1)的電鍍層PL的厚度,比源極焊墊用的電鍍層PLS的厚度更厚,尤其,可令導線連接用的焊墊(PDG、PD1)的鎳電鍍層PL1的厚度,比源極焊墊用的鎳電鍍層PLS1的厚度更厚。藉此,便可在導線連接用的焊墊(PDG、PD1)中,防止導線結合時的裂縫。
本實施態樣,刻意地令閘極焊墊用的鎳電鍍層PLG1的厚度,比源極焊墊用的鎳電鍍層PLS1的厚度更厚,茲針對其具體的方法,在以下進行説明。
如上述<關於電鍍層PL形成步驟>的欄位所説明的,在上述步驟S5中,將晶圓WF浸漬於Ni電鍍用的處理槽BH1內所儲存的電鍍液中,並將晶圓WF浸漬在電鍍液中的狀態維持既定的時間,藉此,形成鎳電鍍層PL1。鎳電鍍層PL1,在從開口部OP露出之導電體膜CD的表面上,亦即,在從開口部OPG露出之閘極電極GE的表面上與從開口部OPS露出之源極電極SE的表面上,選擇性地成長。所使用的電鍍液,例如,含有硫酸鎳,並含有次亞磷酸鹽作為還原劑。
無電解Ni電鍍步驟(步驟S5),如以下的式1所示的反應式,藉由來自還原劑(在此為次亞磷酸鹽)的電子的供給,Ni金屬在從開口部OP露出的導電體膜CD上析出。
Ni2 +
+H2
PO2 -
+H2
O→Ni+H2
PO3 -
+2H+
...(式1)。由式1亦可知,當還原劑的供給減少時,鎳電鍍膜的成膜速度會下降。
於是,本實施態樣,令鎳電鍍層PL1(PLS1、PLG1)以「相較於從開口部OPG露出之閘極電極GE的附近,在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的濃度較低」的狀態成長。藉此,閘極焊墊用的鎳電鍍層PLG1的成膜速度(成膜速率),比源極焊墊用的鎳電鍍層PLS1的成膜速度(成膜速率)更大(快),其結果,便可令形成於從開口部OPG露出之閘極電極GE上的鎳電鍍層PLG1的厚度,比形成於從開口部OPS露出之源極電極SE上的鎳電鍍層PLS1的厚度更厚。
具體而言,在將晶圓WF浸漬於處理槽BH1內所儲存的電鍍液中,並配置於晶圓保持部WH之後,令電鍍液的流速降低(例如從18L/min下降到10L/min),不晃動晶圓WF,令其處於靜止狀態。藉此,相對於從開口部OP露出之導電體膜CD的表面,其表面附近的電鍍液,處於幾乎靜止不動的狀態,並將該狀態維持既定的時間。利用上述式1的反應,Ni金屬在從開口部OPG露出之閘極電極GE的表面上與從開口部OPS露出之源極電極SE的表面上析出,反映開口部OPS的面積比開口部OPG的面積更大此點,相較於從開口部OPG露出之閘極電極GE的附近,在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的消耗量更多。
一般的無電解Ni電鍍步驟,電鍍液的流速比較大,另外,會在電鍍液中令晶圓WF上下晃動。因此,在閘極電極GE的附近與源極電極SE的附近,各自所消耗的還原劑立即獲得補充,在從開口部OPG露出之閘極電極GE的附近,與在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的濃度大致相同。
然而,本實施態樣,在無電解Ni電鍍步驟中,係令電鍍液的流速降低,另外,並未在電鍍液中令晶圓WF晃動,而係令其靜止。因此,在閘極電極GE的附近與源極電極SE的附近,各自所消耗的還原劑並未立即獲得補充,在從開口部OPG露出之閘極電極GE的附近,與在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的濃度並不相同。亦即,在相較於閘極電極GE的附近區域還原劑的消耗量比較大的源極電極SE的附近區域,電鍍液中的還原劑的濃度降低,因此,相較於從開口部OPG露出之閘極電極GE的附近,在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的濃度較低。若在該狀態下,Ni金屬的析出進行,則閘極焊墊用的鎳電鍍層PLG1的成膜速度,會比源極焊墊用的鎳電鍍層PLS1的成膜速度更大(快)。藉此,便可在完成無電解Ni電鍍步驟的階段,令形成於從面積較小之開口部OPG露出的閘極電極GE上的鎳電鍍層PLG1的厚度,比形成於從面積較大之開口部OPS露出的源極電極SE上的鎳電鍍層PLS1的厚度更厚。
圖39,係表示結合焊墊用的開口部(相當於上述開口部OP)的面積與形成於從該開口部露出之導電體膜(相當於上述導電體膜CD)上的鎳電鍍層(相當於上述鎳電鍍層PL1)的成膜速度的相關關係的圖形。圖39的圖形的横軸,對應結合焊墊用的開口部的面積,圖39的圖形的縱軸,對應鎳電鍍層的成膜速度。另外,圖39的圖形,將實行一般的無電解Ni電鍍步驟的態樣(對應圖形中的白點),顯示為「一般的無電解Ni電鍍」,並將實行本實施態樣的無電解Ni電鍍步驟的態樣(對應圖形中的黑點),顯示為「本實施態樣」。另外,圖39的圖形所示的一般的無電解Ni電鍍步驟的態樣,令電鍍液的流速比較大,而且,在電鍍液中令晶圓上下晃動。再者,圖39的圖形所示的本實施態樣的無電解Ni電鍍步驟,令電鍍液的流速降低,而且,並未在電鍍液中令晶圓晃動,而係令其靜止。
如圖39的圖形所示的,一般的無電解Ni電鍍步驟的態樣,並未相依於結合焊墊用的開口部(相當於上述開口部OP)的面積,鎳電鍍層的成膜速度,大致一定。吾人認為,這是因為即便無電解Ni電鍍進行,在較小的開口部的附近,與在較大的開口部的附近,電鍍液中的還原劑的濃度仍大致相同的關係。因此,在一般的無電解Ni電鍍步驟的態樣中,形成於從較小之開口部露出的導電體膜上的鎳電鍍層的厚度,與形成於從較大之開口部露出的導電體膜上的鎳電鍍層的厚度,大致相同。
如圖39的圖形所示的,本實施態樣的無電解Ni電鍍步驟的態樣,隨著結合焊墊用的開口部(相當於上述開口部OP)的面積變大,鎳電鍍層的成膜速度會變小。亦即,相較於形成於從較小之開口部露出的導電體膜上的鎳電鍍層,形成於從較大之開口部露出的導電體膜上的鎳電鍍層,成膜速度較小。在圖39的圖形的情況下,當較大之開口部與較小之開口部其開口部的面積比為9倍左右時,在較大之開口部與較小之開口部的鎳電鍍層的成膜速度相差22%左右,另外,當較大之開口部與較小之開口部其開口部的面積比為26倍左右時,在較大之開口部與較小之開口部的鎳電鍍層的成膜速度相差32%左右。吾人認為,這是因為若無電解Ni電鍍進行,則在較小之開口部的附近與較大之開口部的附近,電鍍液中的還原劑的濃度會產生差異,相較於從較小之開口部露出的導電體膜的附近區域,在從較大之開口部露出的導電體膜的附近區域,其電鍍液中的還原劑的濃度較低的關係。因此,在本實施態樣之無電解Ni電鍍步驟的態樣中,相較於形成於從較小之開口部露出的導電體膜上的鎳電鍍層(相當於上述鎳電鍍層PLG1)的厚度,形成於從較大之開口部露出的導電體膜上的鎳電鍍層(相當於上述鎳電鍍層PLS1)的厚度較薄。
像這樣,本實施態樣,在鎳電鍍層PL1的成膜步驟(電鍍步驟)中,係以閘極焊墊用的鎳電鍍層PLG1的成膜速度比源極焊墊用的鎳電鍍層PLS1的成膜速度更大(快)的方式,形成鎳電鍍層PL1。令閘極焊墊用的鎳電鍍層PLG1的成膜速度,比源極焊墊用的鎳電鍍層PLS1的成膜速度更大(快),藉此,便可在完成鎳電鍍層PL1的成膜步驟的階段,令閘極焊墊用的鎳電鍍層PLG1的厚度,比源極焊墊用的鎳電鍍層PLS1的厚度更厚。
另外,本實施態樣,在鎳電鍍層PL1的成膜步驟(電鍍步驟),鎳電鍍層PL1(PLS1、PLG1)係以「相較於從開口部OPG露出之閘極電極GE的附近,在從開口部OPS露出之源極電極SE的附近,其電鍍液中的還原劑的濃度較低」的狀態成長。藉此,閘極焊墊用的鎳電鍍層PLG1的成膜速度,比源極焊墊用的鎳電鍍層PLS1的成膜速度更大(快),其結果,便可令閘極焊墊用的鎳電鍍層PLG1的厚度,比源極焊墊用的鎳電鍍層PLS1的厚度更厚。
圖40以及圖41,係表示針對是否發生半導體基板的翹曲以及是否在導線結合時發生裂縫進行調查的結果表。在圖40以及圖41之中,圖40,係顯示出相當於上述檢討例的情況,圖41,係顯示出相當於本實施態樣的情況。
在此,在圖40以及圖41的表格中,大面積焊墊,係相當於源極焊墊(PDS、PDS101)者,小面積焊墊,係相當於閘極焊墊(PDG、PDG101)者。因此,在圖40(檢討例)的表格中,大面積焊墊的Ni電鍍層的厚度,相當於上述源極焊墊用的鎳電鍍層PLS101的厚度,小面積焊墊的Ni電鍍層的厚度,相當於上述閘極焊墊用的鎳電鍍層PLG101的厚度。另外,在圖41(本實施態樣)的表格中,大面積焊墊的Ni電鍍層的厚度,相當於上述源極焊墊用的鎳電鍍層PLS1的厚度,小面積焊墊的Ni電鍍層的厚度,相當於上述閘極焊墊用的鎳電鍍層PLG1的厚度。另外,在圖40(檢討例)的態樣中,大面積焊墊的Ni電鍍層的厚度,與小面積焊墊的Ni電鍍層的厚度,彼此相同。在圖41(本實施態樣)的態樣中,相較於大面積焊墊的Ni電鍍層的厚度,小面積焊墊的Ni電鍍層的厚度更厚,小面積焊墊的Ni電鍍層的厚度,約為大面積焊墊的Ni電鍍層的厚度的1.3倍。此時(圖41的態樣),大面積焊墊的面積,約為小面積焊墊的面積的26.1倍。
另外,若改變大面積焊墊與小面積焊墊的面積比,則大面積焊墊的Ni電鍍層的厚度與小面積焊墊的Ni電鍍層的厚度的比也會改變。圖42,顯示出針對改變圖41的大面積焊墊與小面積焊墊的面積比的態樣進行檢討的結果,作為本實施態樣的變化實施例,其與上述圖40以及圖41同樣,亦顯示出針對是否發生半導體基板的翹曲以及是否在導線結合時發生裂縫進行調查的結果表。在圖42的態樣中,小面積焊墊的Ni電鍍層的厚度,約為大面積焊墊的Ni電鍍層的厚度的1.2倍,此時(圖42的態樣)的大面積焊墊的面積,約為小面積焊墊的面積的9.1倍。
從抑制半導體基板的翹曲的觀點來看,大面積焊墊的Ni電鍍層的厚度,宜比例如3μm更薄。因此,在圖40~圖42的表格中,當大面積焊墊的Ni電鍍層的厚度比3μm更薄時,於「半導體基板的翹曲」的欄位顯示「○」,當大面積焊墊的Ni電鍍層的厚度在3μm以上時,於「半導體基板的翹曲」的欄位顯示「×」。
另外,實行導線結合的小面積焊墊,從提高對導線結合時的壓力(物理性衝撃)的耐久性以防止發生裂縫的觀點來看,小面積焊墊的Ni電鍍層的厚度,宜在例如3μm以上。因此,在圖40~圖42的表格中,當小面積焊墊的Ni電鍍層的厚度在3μm以上時,於「導線結合時的裂縫」的欄位顯示「○」,當小面積焊墊的Ni電鍍層的厚度小於3μm時,於「導線結合時的裂縫」的欄位顯示「×」。
由圖40的表格可知,當大面積焊墊的Ni電鍍層的厚度與小面積焊墊的Ni電鍍層的厚度相同時,可能會發生半導體基板的翹曲的問題或導線結合時的裂縫的問題。相對於此,相較於大面積焊墊的Ni電鍍層的厚度令小面積焊墊的Ni電鍍層的厚度更厚的本實施態樣,由圖41以及圖42的表格可知,可解決半導體基板的翹曲的問題與導線結合時的裂縫的問題二者。例如,在圖41的表格中,當令大面積焊墊的Ni電鍍層的厚度為2.3~2.9μm,且令小面積焊墊的Ni電鍍層的厚度為3~3.8μm時(亦即試料No.10、11、12),可解決半導體基板的翹曲的問題與導線結合時的裂縫的問題二者。另外,在圖42的表格中,當令大面積焊墊的Ni電鍍層的厚度為2.5~2.9μm,且令小面積焊墊的Ni電鍍層的厚度為3~3.5μm時(亦即試料No.18、19),可解決半導體基板的翹曲的問題與導線結合時的裂縫的問題二者。
另外,若比較圖41的態樣與圖42的態樣,則圖41的態樣,可一邊抑制大面積焊墊的Ni電鍍層的厚度,一邊令小面積焊墊的Ni電鍍層的厚度更大,故從盡可能提高對導線結合時的壓力(物理性衝撃)的耐久性以更確實地防止裂縫發生的觀點來看,圖41的態樣,可謂更佳。
另外,圖40~圖42的態樣,從抑制半導體基板的翹曲的觀點來看,大面積焊墊的Ni電鍍層的厚度宜比3μm更薄,從防止在導線結合時發生裂縫的觀點來看,小面積焊墊的Ni電鍍層的厚度宜在3μm以上。然而,令大面積焊墊的Ni電鍍層的厚度減薄,雖可抑制半導體基板的翹曲,惟半導體基板的翹曲容易度,亦相依於半導體基板的厚度。另外,令實行導線結合的小面積焊墊的Ni電鍍層的厚度增厚,雖可防止導線結合時的裂縫,惟導線結合時的裂縫的發生容易度,亦相依於在導線結合時對結合焊墊所施加的結合壓力(物理性衝撃)的大小。近年來,隨著半導體基板趨向薄型化以及導線結合技術的改善,導線結合時的結合壓力的大小也跟著改變。因此,在此雖提及大面積焊墊的Ni電鍍層的厚度宜比3μm更薄,小面積焊墊的Ni電鍍層的厚度宜在3μm以上,惟大面積焊墊的Ni電鍍層的厚度的較佳範圍,與小面積焊墊的Ni電鍍層的厚度的較佳範圍,可因應半導體基板的厚度或導線結合時的結合壓力而改變。
(實施態樣2)圖43以及圖44,係本實施態樣2之半導體裝置(半導體晶片)CP的主要部位剖面圖。圖43,顯示出相當於上述實施態樣1的上述圖11的剖面,於圖44,顯示出相當於上述實施態樣1的上述圖12的剖面。
在上述實施態樣1中,電鍍層PL,係由形成於從開口部OP露出之部分的導電體膜CD上的鎳電鍍層PL1與形成於該鎳電鍍層PL1上的金電鍍層PL2的堆疊膜所構成。
在本實施態樣2中,電鍍層PL,係由形成於從開口部OP露出之部分的導電體膜CD上的鎳電鍍層PL1、形成於該鎳電鍍層PL1上的鈀(Pd)電鍍層PL3,以及形成於該鈀電鍍層PL3上的金電鍍層PL2的堆疊膜所構成。亦即,本實施態樣2,在電鍍層PL中,在鎳電鍍層PL1與金電鍍層PL2之間設置了鈀電鍍層PL3,此點與上述實施態樣1並不相同,除此以外,本實施態樣2,與上述實施態樣1大致相同。因此,本實施態樣2,以與上述實施態樣1的相異點為中心進行説明,關於與上述實施態樣1相同的特徵點,省略重複説明。
在此,將構成源極焊墊用的電鍍層PLS的鈀電鍍層PL3,稱為源極焊墊用的鈀電鍍層PLS3。另外,將構成閘極焊墊用的電鍍層PLG的鈀電鍍層PL3,稱為閘極焊墊用的鈀電鍍層PLG3。因此,源極焊墊用的鈀電鍍層PLS3,形成於源極焊墊用的鎳電鍍層PLS1與源極焊墊用的金電鍍層PLS2之間,另外,閘極焊墊用的鈀電鍍層PLG3,形成於閘極焊墊用的鎳電鍍層PLG1與閘極焊墊用的金電鍍層PLG2之間。利用鎳電鍍層PLS1、其上的鈀電鍍層PLS3以及其上的金電鍍層PLS2,形成了源極焊墊用的電鍍層PLS,另外,利用鎳電鍍層PLG1、其上的鈀電鍍層PLG3以及其上的金電鍍層PLG2,形成了閘極焊墊用的電鍍層PLG。
在本實施態樣2之半導體裝置CP的製造步驟中,只要在對應上述圖31以及圖32的步驟,在從開口部OP露出之導電體膜CD上,依序形成鎳電鍍層PL1、鈀電鍍層PL3以及金電鍍層PL2即可。亦即,只要在上述實施態樣1的製造步驟中,在鎳電鍍層PL1形成步驟(上述步驟S5)與金電鍍層PL2形成步驟(上述步驟S6)之間,實行鈀電鍍層PL3形成步驟即可。在鈀電鍍層PL3形成步驟中,係在源極焊墊用的鎳電鍍層PLS1上形成源極焊墊用的鈀電鍍層PLS3,並在閘極焊墊用的鎳電鍍層PLG1上形成閘極焊墊用的鈀電鍍層PLG3。然後,在金電鍍層PL2形成步驟(上述步驟S6)中,係在源極焊墊用的鈀電鍍層PLS3上形成源極焊墊用的金電鍍層PLS2,並在閘極焊墊用的鈀電鍍層PLG3上形成閘極焊墊用的金電鍍層PLG2。藉此,便會在從開口部OP露出之導電體膜CD上,形成由鎳電鍍層PL1、鎳電鍍層PL1上的鈀電鍍層PL3以及鈀電鍍層PL3上的金電鍍層PL2的堆疊膜所構成的電鍍層PL。鎳電鍍層PL1、鈀電鍍層PL3以及金電鍍層PL2,可各自用電鍍法(宜為無電解電鍍法)形成。除此以外,本實施態樣2之半導體裝置CP的製造步驟,與上述實施態樣1基本上相同。
茲針對鈀電鍍層PL3形成步驟,在以下具體進行説明。
在參照上述圖35所説明的流程中,本實施態樣2,在步驟S5的Ni電鍍處理之後,且在步驟S6的Au電鍍處理之前,實行Pd電鍍處理,令電鍍膜(Pd膜)成長。具體而言,本實施態樣2,令鎳電鍍層PL1的表面與Pd電鍍用的電鍍液接觸,以形成鈀電鍍層(Pd電鍍層)PL3。更具體而言,係將晶圓WF(半導體基板SB)浸漬於Pd電鍍用的處理槽BH內所儲存的Pd電鍍用的電鍍液,藉此,實行電鍍處理(Pd電鍍處理),以在鎳電鍍層PL1上形成鈀電鍍層PL3。該鈀電鍍層PL3,選擇性地於形成於從開口部OP露出之導電體膜CD上的鎳電鍍層PL1上成長。
作為鈀電鍍層PL3,可為由純鈀所構成的無電解鈀電鍍層,以及含有磷(P)的無電解鈀電鍍層。當鈀電鍍層PL3為由純鈀所構成的無電解鈀電鍍層時,作為所使用的電鍍液,可例示出含有鈀鹽,並含有蟻酸鹽作為還原劑的電鍍液。電鍍液的溫度,可為例如60~80℃左右,pH可為例如5~7左右,Pd濃度可為例如1.5~2.5g/l(克/公升)左右。當鈀電鍍層PL3為含有磷(P)的無電解鈀電鍍層時,作為所使用的電鍍液,可例示出含有鈀鹽,並含有次亞磷酸鹽作為還原劑的電鍍液。電鍍液的溫度,可為例如45~55℃左右,pH可為例如6.5~7.5左右,Pd濃度可為例如0.4~0.8g/l(克/公升)左右。
在本實施態樣2中,亦可獲得如上述實施態樣1所説明的功效。
若簡單説明,則在本實施態樣2中,亦與上述實施態樣1同樣,針對面積較大的源極焊墊用的電鍍層PLS令厚度減薄,針對面積較小的閘極焊墊用的電鍍層PLG,令其比源極焊墊用的電鍍層PLS更厚。藉此,便可抑制可能會影響源極焊墊用的電鍍層PLS的應力,另外,就閘極焊墊PDG而言,可提高對導線結合時的壓力(物理性衝撃)的耐久性。藉此,便可令半導體裝置的綜合可靠度提高,另外,可令半導體裝置的製造產能提高。
另外,無論在上述實施態樣1與本實施態樣2的其中哪一個態樣,在電鍍層PL的各層中,厚度具支配性質者,係鎳電鍍層PL1,例如,鎳電鍍層PL1的厚度,佔電鍍層PL整體的厚度的過半。另外,無論在上述實施態樣1與本實施態樣2的其中哪一個態樣,在構成電鍍層PL的各層之中,容易因為導線結合時的壓力(物理性衝撃)而破裂者,係較硬的鎳電鍍層PL1。另外,無論在上述實施態樣1與本實施態樣2的其中哪一個態樣,在構成電鍍層PL的各層之中,容易成為半導體基板的翹曲的原因者,係鎳電鍍層PL1。因此,本實施態樣2,亦與上述實施態樣1同樣,宜令面積較小的閘極焊墊用的鎳電鍍層PLG1的厚度,比面積較大的源極焊墊用的鎳電鍍層PLS1的厚度更厚。針對面積較小的閘極焊墊PDG,尤其,令鎳電鍍層PL1(PLG1)的厚度增厚,藉此,便可有效地提高對導線結合時的壓力(物理性衝撃)的耐久性,並可確實地抑制或防止在導線結合時於鎳電鍍層PL1(PLG1)發生裂縫。另一方面,針對相較於閘極焊墊PDG面積更大的源極焊墊PDS,令鎳電鍍層PL1(PLS1)的厚度減薄,藉此,便可抑制該鎳電鍍層PL1(PLS1)的應力,並可改善可能會因為鎳電鍍層PL1(PLS1)的應力而產生的問題。例如,可確實地抑制或防止因為鎳電鍍層PL1(PLS1)的應力而發生半導體基板的翹曲。因此,可令所製造之半導體裝置(包含半導體晶片在內的半導體封裝體)的可靠度確實地提高。
另外,相較於鎳電鍍層PL1,鈀電鍍層PL3,產生關於鎳電鍍層PL1可能會發生之問題(導線結合時的裂縫或半導體基板的翹曲的問題)的風險較小。因此,與上述實施態樣1同樣,在本實施態樣2中,因應結合焊墊而控制鎳電鍍層PL1的厚度也很重要。因此,閘極焊墊用的鈀電鍍層PLG3的厚度,與源極焊墊用的鈀電鍍層PLS3的厚度,可彼此相同,亦可彼此相異,另外,閘極焊墊用的鈀電鍍層PLG3的厚度,亦可比源極焊墊用的鈀電鍍層PLS3的厚度更厚。另外,在本實施態樣2中,閘極焊墊用的金電鍍層PLG2的厚度與源極焊墊用的金電鍍層PLS2的厚度的關係,亦可與上述實施態樣1相同。
本實施態樣2,藉由設置鈀電鍍層PL3,更可獲得以下的功效。
本實施態樣2,在鎳電鍍層PL1與金電鍍層PL2之間設置了鈀電鍍層PL3。鈀電鍍層亦可發揮作為焊料障蔽層的功能,惟作為焊料障蔽層的功能,鎳電鍍層比鈀電鍍層更優異。然而,鈀(Pd),相較於鎳(Ni),彈性係數更低,另外,熱膨脹係數也較低一些。因此,像本實施態樣2這樣在鎳電鍍層PL1上形成鈀電鍍層PL3,便可緩和作用於導電體膜CD的應力。另外,像本實施態樣2這樣在鎳電鍍層PL1上形成鈀電鍍層PL3,便可令鎳電鍍層PL1的厚度減薄,故亦可令鎳電鍍層PL1的應力減小。因此,像本實施態樣2這樣在鎳電鍍層PL1上形成鈀電鍍層PL3,便可更確實地抑制或防止因為鎳電鍍層PL1的應力而導致半導體基板翹曲。因此,可令半導體裝置(半導體裝置CP以及使用了該半導體裝置CP的半導體封裝體)的可靠度更進一步提高。
以上,係根據實施態樣具體説明本發明人之發明,惟本發明並非僅限於該等實施態樣,在不超出其發明精神的範圍內可作出各種變更,自不待言。
A1-A1、B-B‧‧‧剖面線BD1、BD2‧‧‧接合層BE‧‧‧背面電極BH、BH1‧‧‧處理槽CD‧‧‧導電體膜CP1、CP2‧‧‧半導體晶片CP、CP101‧‧‧半導體裝置CT1、CT2‧‧‧接觸孔DB、DB1、DB2‧‧‧晶片焊墊DP、DP1、DP2‧‧‧晶片焊墊GB‧‧‧外槽GEW‧‧‧閘極配線GE‧‧‧閘極電極GF1、IL、PA‧‧‧絶緣膜GF‧‧‧閘極絶緣膜GR‧‧‧導熱膏HS‧‧‧金屬平板LD、LD1、LD2‧‧‧引線MP1、MP‧‧‧金屬板MR、MR1‧‧‧封裝部MRa‧‧‧頂面MRb‧‧‧底面MRc1、MRc2、MRc3、MRc4‧‧‧側面MS‧‧‧處理裝置NR‧‧‧n+型半導體區域OP、OPG、OPS‧‧‧開口部PD1、PD2、PD3‧‧‧焊墊PDG、PDG101‧‧‧閘極焊墊PDS、PDS101‧‧‧源極焊墊PKG、PKG1‧‧‧半導體裝置PL、PLG、PLS、PL100、PLS100、PLG100‧‧‧電鍍層PL1、PLG1、PLS1、PL101、PLS101、PLG101‧‧‧鎳電鍍層PL2、PLG2、PLS2、PL102、PLS102、PLG102‧‧‧金電鍍層PL3、PLG3、PLS3‧‧‧鈀電鍍層PR‧‧‧p型半導體區域PS‧‧‧導電膜Q1‧‧‧單位電晶體單元S1~S6、S2a、S6a、S6b‧‧‧步驟SB‧‧‧半導體基板SD‧‧‧焊料SE‧‧‧源極電極T1、T2、T3、T4、T101、T102、T103、T104‧‧‧厚度TGL‧‧‧閘極拉出部TG‧‧‧溝槽閘極TR‧‧‧溝槽WA、WA1‧‧‧導線WF‧‧‧晶圓WH‧‧‧晶圓保持部
[圖1]係一實施態樣之半導體裝置的整體俯視圖。 [圖2]係一實施態樣之半導體裝置的整體俯視圖。 [圖3]係一實施態樣之半導體裝置的頂面圖。 [圖4]係一實施態樣之半導體裝置的底面圖。 [圖5]係一實施態樣之半導體裝置的平面透視圖。 [圖6]係一實施態樣之半導體裝置的平面透視圖。 [圖7]係一實施態樣之半導體裝置的平面透視圖。 [圖8]係一實施態樣之半導體裝置的剖面圖。 [圖9]係表示一實施態樣之半導體裝置的安裝態樣的一例的剖面圖。 [圖10]係表示變化實施例之半導體裝置的平面透視圖。 [圖11]係一實施態樣之半導體裝置的主要部位剖面圖。 [圖12]係一實施態樣之半導體裝置的主要部位剖面圖。 [圖13]係一實施態樣之半導體裝置的平面透視圖。 [圖14]係一實施態樣之半導體裝置的平面透視圖。 [圖15]係一實施態樣之半導體裝置的主要部位剖面圖。 [圖16]係一實施態樣之半導體裝置的主要部位剖面圖。 [圖17]係一實施態樣之半導體裝置的製造步驟中的主要部位剖面圖。 [圖18]係接續圖17之半導體裝置的製造步驟中的主要部位剖面圖。 [圖19]係接續圖18之半導體裝置的製造步驟中的主要部位剖面圖。 [圖20]係接續圖19之半導體裝置的製造步驟中的主要部位剖面圖。 [圖21]係接續圖20之半導體裝置的製造步驟中的主要部位剖面圖。 [圖22]係接續圖21之半導體裝置的製造步驟中的主要部位剖面圖。 [圖23]係接續圖22之半導體裝置的製造步驟中的主要部位剖面圖。 [圖24]係與圖23相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖25]係接續圖23之半導體裝置的製造步驟中的主要部位剖面圖。 [圖26]係與圖25相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖27]係接續圖26之半導體裝置的製造步驟中的主要部位剖面圖。 [圖28]係與圖27相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖29]係接續圖27之半導體裝置的製造步驟中的主要部位剖面圖。 [圖30]係與圖29相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖31]係接續圖30之半導體裝置的製造步驟中的主要部位剖面圖。 [圖32]係與圖31相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖33]係接續圖31之半導體裝置的製造步驟中的主要部位剖面圖。 [圖34]係與圖33相同之半導體裝置的製造步驟中的主要部位剖面圖。 [圖35]係表示電鍍層形成步驟的詳細內容的流程圖。 [圖36]係電鍍層形成步驟的説明圖。 [圖37]係檢討例之半導體裝置的主要部位剖面圖。 [圖38]係檢討例之半導體裝置的主要部位剖面圖。 [圖39]係表示結合焊墊用的開口部的面積與形成於從該開口部露出之導電體膜上的鎳電鍍層的成膜速度的相關關係的圖形。 [圖40]係表示針對是否發生半導體基板的翹曲以及是否在導線結合時發生裂縫進行調查的結果表。 [圖41]係表示針對是否發生半導體基板的翹曲以及是否在導線結合時發生裂縫進行調查的結果表。 [圖42]係表示針對是否發生半導體基板的翹曲以及是否在導線結合時發生裂縫進行調查的結果表。 [圖43]係另一實施態樣之半導體裝置的主要部位剖面圖。 [圖44]係另一實施態樣之半導體裝置的主要部位剖面圖。
CP‧‧‧半導體裝置
GEW‧‧‧閘極配線
GE‧‧‧閘極電極
PL、PLG、PLS‧‧‧電鍍層
SE‧‧‧源極電極
Claims (16)
- 一種半導體裝置的製造方法,其特徵為包含:(a)在半導體基板的主面上形成層間絶緣膜的步驟;(b)在該層間絶緣膜上,形成第1焊墊用的第1導電膜圖案以及第2焊墊用的第2導電膜圖案的步驟;(c)在該層間絶緣膜上,以覆蓋該第1以及第2導電膜圖案的方式,形成絶緣膜的步驟;(d)於該絶緣膜,形成露出該第1導電膜圖案的一部分的該第1焊墊用的第1開口部,以及露出該第2導電膜圖案的一部分的該第2焊墊用的第2開口部的步驟;以及(e)在從該第1開口部露出之部分的該第1導電膜圖案上透過電鍍而形成第1電鍍層,並在從該第2開口部露出之部分的該第2導電膜圖案上透過電鍍而形成第2電鍍層的步驟;該第2開口部的面積,比該第1開口部的面積更小;該第2電鍍層的厚度,比該第1電鍍層的厚度更厚;並且當透過電鍍而形成該第1電鍍層及該第2電鍍層時,使該半導體基板保持靜止而不晃動。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,該第1以及第2導電膜圖案,係由以鋁為主成分的導電材料所構成。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,該第1電鍍層,包含第1鎳電鍍層; 該第2電鍍層,包含第2鎳電鍍層;該(e)步驟,包含:(e1)在從該第1開口部露出之部分的該第1導電膜圖案上形成該第1鎳電鍍層,並在從該第2開口部露出之部分的該第2導電膜圖案上形成該第2鎳電鍍層的步驟;該第2鎳電鍍層的厚度,比該第1鎳電鍍層的厚度更厚。
- 如申請專利範圍第3項之半導體裝置的製造方法,其中,在該(e1)步驟中,該第2鎳電鍍層的成膜速度,比該第1鎳電鍍層的成膜速度更大。
- 如申請專利範圍第3項之半導體裝置的製造方法,其中,該第2鎳電鍍層的厚度,為該第1鎳電鍍層的厚度的1.2倍以上。
- 如申請專利範圍第3項之半導體裝置的製造方法,其中,該第1電鍍層,包含:該第1鎳電鍍層;以及第1金電鍍層,形成於該第1鎳電鍍層上;該第2電鍍層,包含:該第2鎳電鍍層;以及第2金電鍍層,形成於該第2鎳電鍍層上;該(e)步驟,更包含:(e2)在該(e1)步驟之後,在該第1鎳電鍍層上形成該第1金電鍍層,並在該第2鎳電鍍層上形成該第2金電鍍層的步驟。
- 如申請專利範圍第3項之半導體裝置的製造方法,其中,該第1電鍍層,包含:該第1鎳電鍍層;第1鈀電鍍層,形成於該第1鎳電鍍層上;以及第1金電鍍層,形成於該第1鈀電鍍層上;該第2電鍍層,包含:該第2鎳電鍍層;第2鈀電鍍層,形成於該第2鎳電鍍層上;以及第2金電鍍層,形成於該第2鈀電鍍層上;該(e)步驟,更包含:(e2)在該(e1)步驟之後,在該第1鎳電鍍層上形成該第1鈀電鍍層,並在該第2鎳電鍍層上形成該第2鈀電鍍層的步驟;以及(e3)在該(e2)步驟之後,在該第1鈀電鍍層上形成該第1金電鍍層,並在該第2鈀電鍍層上形成該第2金電鍍層的步驟。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,在該(a)步驟之前,更包含:(a1)於該半導體基板形成半導體元件的步驟;在該(e)步驟之後,更包含:(f)在該半導體基板的該主面之相反側的背面上形成背面電極的步驟。
- 如申請專利範圍第8項之半導體裝置的製造方法,其中,該半導體元件係功率MISFET; 該第1導電膜圖案,係源極用的導電膜圖案;該第2導電膜圖案,係閘極用的導電膜圖案;該背面電極,係汲極用的背面電極。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,該第1導電膜圖案及該第1電鍍層,係用來連接金屬板的結合焊墊;該第2導電膜圖案及該第2電鍍層,係用來連接導線的結合焊墊。
- 如申請專利範圍第3項之半導體裝置的製造方法,其中,在該(e1)步驟中,該第1鎳電鍍層以及該第2鎳電鍍層,係以「相較於從該第2開口部露出之部分的該第2導電膜圖案的附近,在從該第1開口部露出之部分的該第1導電膜圖案的附近,其電鍍液中的還原劑的濃度較低的狀態」成長。
- 如申請專利範圍第1項之半導體裝置的製造方法,其中,在該(e)步驟中,使電鍍液的流速降低。
- 如申請專利範圍第12項之半導體裝置的製造方法,其中,在該(e)步驟中,使該電鍍液的流速從18L/min降低至10L/min。
- 如申請專利範圍第12項之半導體裝置的製造方法,其中,該電鍍液的溫度為80至90℃。
- 如申請專利範圍第14項之半導體裝置的製造方法,其中,該電鍍液的pH為4至5。
- 如申請專利範圍第15項之半導體裝置的製造方法,其中,該電鍍液含有硫酸鎳,並且Ni濃度為5至6.5g/L。
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US10566267B2 (en) * | 2017-10-05 | 2020-02-18 | Texas Instruments Incorporated | Die attach surface copper layer with protective layer for microelectronic devices |
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JP7472435B2 (ja) * | 2019-05-13 | 2024-04-23 | 富士電機株式会社 | 半導体モジュールの製造方法 |
JP7189846B2 (ja) | 2019-07-16 | 2022-12-14 | 株式会社東芝 | 半導体装置の製造方法および金属の積層方法 |
IT201900013743A1 (it) | 2019-08-01 | 2021-02-01 | St Microelectronics Srl | Dispositivo elettronico di potenza incapsulato, in particolare circuito a ponte comprendente transistori di potenza, e relativo procedimento di assemblaggio |
CN111403341B (zh) * | 2020-03-28 | 2023-03-28 | 电子科技大学 | 降低窄控制栅结构栅电阻的金属布线方法 |
IT202000016840A1 (it) | 2020-07-10 | 2022-01-10 | St Microelectronics Srl | Dispositivo mosfet incapsulato ad alta tensione e dotato di clip di connessione e relativo procedimento di fabbricazione |
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