TWI714183B - 半導體記憶裝置及其製造方法 - Google Patents

半導體記憶裝置及其製造方法 Download PDF

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TWI714183B
TWI714183B TW108126126A TW108126126A TWI714183B TW I714183 B TWI714183 B TW I714183B TW 108126126 A TW108126126 A TW 108126126A TW 108126126 A TW108126126 A TW 108126126A TW I714183 B TWI714183 B TW I714183B
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藤塚良太
山田健太
山中孝紀
岡田貴行
石垣寛和
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日商東芝記憶體股份有限公司
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Abstract

本發明之實施形態係關於一種半導體記憶裝置及其製造方法。 一實施形態之半導體記憶裝置具備：半導體基板；積層體，其於半導體基板上將複數個電極層積層而成；記憶膜，其於積層體內具有相對於電極層沿垂直方向配置之第1阻擋絕緣膜、與第1阻擋絕緣膜對向之電荷蓄積膜、與電荷蓄積膜對向之穿隧絕緣膜、及與穿隧絕緣膜對向之通道膜；及障壁層，其設置於複數個電極層與記憶膜之界面、及記憶膜內之界面之至少一者，且以碳作為主成分。

Description

半導體記憶裝置及其製造方法
本發明之實施形態係關於一種半導體記憶裝置及其製造方法。
作為半導體記憶裝置之一之三維積層型半導體記憶裝置具備由複數個電極層積層而成之積層體、及設置於該積層體內之記憶膜。於記憶膜設置有多種膜。
本發明之實施形態提供一種可提高可靠性之半導體記憶裝置及其製造方法。
一實施形態之半導體記憶裝置具備：半導體基板；積層體，其於半導體基板上將複數個電極層積層而成；記憶膜，其於積層體內具有相對於電極層沿垂直方向配置之第1阻擋絕緣膜、與第1阻擋絕緣膜對向之電荷蓄積膜、與電荷蓄積膜對向之穿隧絕緣膜、及與穿隧絕緣膜對向之通道膜；及障壁層，其設置於複數個電極層與記憶膜之界面、及記憶膜內之界面之至少一者，且以碳作為主成分。
以下，一面參照圖式一面對實施形態進行說明。
(第1實施形態) 圖1係表示第1實施形態之半導體記憶裝置之主要部分之構成之俯視圖。圖2係沿著圖1所示之剖切線A-A之剖視圖。
圖1及圖2所示之半導體記憶裝置1具備半導體基板10、積層體20、及記憶膜30。半導體基板10例如為矽基板，亦可於矽基板上形成各種電路元件或配線層。於半導體基板10上設置有積層體20。
如圖2所示，積層體20具有複數個電極層21及複數個絕緣層22。複數個電極層21及複數個絕緣層22於與半導體基板10正交之Z方向上交替地積層。
各電極層21具有金屬層211、障壁金屬層212、及阻擋絕緣膜213(第2阻擋絕緣膜)。金屬層211例如包含鎢(W)，並作為字元線發揮功能。障壁金屬層212例如包含氮化鈦(TiN)，並覆蓋金屬層211。可藉由障壁金屬層212防止金屬層211中所包含之金屬材料或雜質擴散。阻擋絕緣膜213例如包含氧化鋁(Al 2O 3)，並覆蓋障壁金屬層212。
各絕緣層22例如包含氧化矽(SiO 2)，並將各電極層21絕緣分離。
如圖2所示，記憶膜30係於積層體20內沿Z方向延伸之柱狀體，具有障壁層31、阻擋絕緣膜32(第1阻擋絕緣膜)、電荷蓄積膜33、穿隧絕緣膜34、通道膜35、及芯絕緣膜36。
障壁層31含有碳作為主成分，並設置於各電極層21之阻擋絕緣膜213與阻擋絕緣膜32之界面、及絕緣層22與阻擋絕緣膜32之界面。可藉由障壁層31抑制鋁自阻擋絕緣膜213向阻擋絕緣膜32(例如矽氧化膜)擴散而導致阻擋絕緣膜32之絕緣性劣化。
由於阻擋絕緣膜32之帶隙寬於電荷蓄積膜33之帶隙，故而蓄積於電荷蓄積膜33中之電子通常不會向電極層21側漏出。但是，當阻擋絕緣膜32之絕緣性劣化時，可能會發生上述電子通過阻擋絕緣膜32之劣化部位後向電極層21側漏出之現象。
另一方面，於本實施形態中，如上所述，藉由障壁層31抑制阻擋絕緣膜32之劣化。其結果為可避免於保持資料時電子自電荷蓄積膜33漏出。再者，障壁層31除含有碳以外，亦可含有矽、氮、及氧。
於障壁層31中，當碳之濃度過高時不易確保絕緣性。因此，期待碳之濃度為0.1～10.0 atomic%之範圍內。又，為了確保上述絕緣性，期待障壁層31之厚度為0.5奈米以下。
阻擋絕緣膜32例如包含氧化矽，且與障壁層31之內周面對向。電荷蓄積膜33例如包含氮化矽(SiN)，且與阻擋絕緣膜32之內周面對向。穿隧絕緣膜34例如包含氮氧化矽(SiON)，且與電荷蓄積膜33之內周面對向。通道膜35例如包含多晶矽，且與穿隧絕緣膜34之內周面對向。通道膜35連接於設置於記憶膜30上之位元線(未圖示)。芯絕緣膜36例如包含氧化矽，且與通道膜35之內周面對向。
以下，使用圖3～圖6對上述半導體記憶裝置1之製造步驟中之一部分進行說明。
首先，如圖3所示，於半導體基板10上形成積層體20a。積層體20a係藉由將絕緣層22與絕緣層23沿Z方向交替地積層而形成。絕緣層22及絕緣層23例如可藉由CVD(Chemical Vapor Deposition，化學氣相沈積)或ALD(Atomic Layer Deposition，原子層沈積)而形成。絕緣層23例如為氮化矽層。
繼而，如圖4所示，形成沿Z方向貫通積層體20a之孔40。孔40例如係藉由RIE(Reactive Ion Etching，反應性離子蝕刻)設置於記憶膜30之形成部位。再者，於本實施形態中，於與Z方向正交之X方向及Y方向上分別形成有複數個孔40。
繼而，如圖5所示，於孔40之內側面形成障壁層31。障壁層31例如可藉由交替地供給六氯乙矽烷、二氯甲矽烷等含有矽之氣體與包含三甲胺、二乙胺、三乙胺、乙二胺所代表之烷基胺之氣體之ALD來形成。為了控制障壁層31之氮濃度，亦可使用氨。又，為了控制障壁層31之氧濃度，亦可使用氧、臭氧、或一氧化二氮等。藉由調整含有矽之氣體、烷基胺、氨、氧化氣體之供給比，可形成具有所需之膜組成之障壁層31。
繼而，如圖6所示，藉由依序成膜阻擋絕緣膜32、電荷蓄積膜33、穿隧絕緣膜34、通道膜35、及芯絕緣膜36而完成記憶膜30。阻擋絕緣膜32～芯絕緣膜36可採用ALD等通常使用之成膜方法，因此此處省略說明。
繼而，利用使用磷酸溶液等之濕式蝕刻將絕緣層23去除。接下來，於絕緣層23之去除部位形成阻擋絕緣膜213(氧化鋁)與電極層21。當以如上方式將絕緣層23替換成電極層21時，形成圖2所示之積層體20。
根據以上所說明之本實施形態，於電極層21之阻擋絕緣膜213與阻擋絕緣膜32之界面形成以碳作為主成分之障壁層31。藉此，可抑制於後續製造步驟中之熱處理等中鋁自阻擋絕緣膜213向阻擋絕緣膜32(例如矽氧化膜)擴散而導致阻擋絕緣膜32之絕緣性劣化，結果可抑制蓄積於電荷蓄積膜33中之電子向電極層21側漏出。藉此，可提高針對非揮發性半導體記憶裝置之資料保持性能之可靠性。
(變化例1) 圖7係表示變化例1之半導體記憶裝置之主要部分之構造之剖視圖。對與上述第1實施形態相同之構成要素標註相同符號，並省略詳細之說明。
於上述第1實施形態之半導體記憶裝置1中，障壁層31設置於記憶膜30內。另一方面，於本變化例之半導體記憶裝置1a中，障壁層31設置於積層體20內。具體來說，障壁層31係以覆蓋電極層21之阻擋絕緣膜213之方式設置。該障壁層31係於將第1實施形態中所說明之絕緣層23去除後且於形成電極層21之前形成。
於本變化例中，與第1實施形態同樣地，於阻擋絕緣膜32與阻擋絕緣膜213之界面亦隔著障壁層31。因此，可抑制鋁向阻擋絕緣膜32擴散，結果，可確保充分之資料保持特性。又，於本變化例中，由於在上下相鄰之電極層21之間亦隔著障壁層31，故而絕緣層22之絕緣性提高，結果亦可改善相鄰字元線之間之電應力耐受性。
(第2實施形態) 圖8係表示第2實施形態之半導體記憶裝置之主要部分之構造之剖視圖。對與上述第1實施形態相同之構成要素標註相同符號，並省略詳細之說明。
於上述第1實施形態之半導體記憶裝置1中，障壁層31設置於記憶膜30之最外側。另一方面，於本實施形態之半導體記憶裝置2中，如圖8所示，阻擋絕緣膜32設置於記憶膜30之最外側，障壁層31設置於阻擋絕緣膜32與電荷蓄積膜33之界面。
於本實施形態中，障壁層31可於阻擋絕緣膜32之成膜後、電荷蓄積膜33之成膜前，與第1實施形態同樣地藉由ALD來形成。此處，障壁層31為了於阻擋絕緣膜32與電荷蓄積膜33之界面作為電荷蓄積層之一部分發揮功能，期待障壁層31中所含有之碳濃度為10.0～70.0 atomic%之範圍內。又，亦期待氧濃度為1.0 atomic%以下之低濃度。因此，期待障壁層31係藉由例如交替地供給六氯乙矽烷、二氯甲矽烷等含有矽之氣體與包含三甲胺、二乙胺、三乙胺、乙二胺所代表之烷基胺之氣體之ALD來形成。又，期待障壁層31之厚度為0.3奈米以上、1奈米以下。
根據本實施形態，可藉由障壁層31抑制阻擋絕緣膜32與電荷蓄積膜33之界面上之氮與氧之相互擴散。擴散至阻擋絕緣膜32中之氮會使阻擋絕緣膜32之絕緣性劣化，又，當擴散至電荷蓄積膜33中之氧形成能階淺之電荷捕獲點時，記憶單元之資料保持特性可能會劣化。
然而，根據本實施形態，藉由抑制阻擋絕緣膜32與電荷蓄積膜33之界面反應，可提高對非揮發性半導體記憶裝置之資料保持性能之可靠性。進而，藉由使障壁層31含有高濃度之碳而使電荷之捕獲密度提高，因此可緩解寫入動作中對記憶單元之電應力。其結果為，可減輕伴隨重寫動作產生之對穿隧絕緣膜34或阻擋絕緣膜32之電破壞，亦可提高記憶單元之可靠性。
(第3實施形態) 圖9係表示第3實施形態之半導體記憶裝置之主要部分之構造之剖視圖。對與上述第1實施形態相同之構成要素標註相同符號，並省略詳細之說明。
於上述第1實施形態之半導體記憶裝置1中，障壁層31設置於記憶膜30之最外側。另一方面，於本實施形態之半導體記憶裝置3中，障壁層31設置於電荷蓄積膜33與穿隧絕緣膜34之界面。
於本實施形態中，障壁層31可於電荷蓄積膜33之成膜後、穿隧絕緣膜34之成膜前，與第1實施形態同樣地藉由ALD形成。又，為了於電荷蓄積膜33與穿隧絕緣膜34之界面作為絕緣膜發揮功能，期待障壁層31中所含有之碳濃度為1.0～50.0 atomic%之範圍內。因此，期待障壁層31係藉由例如交替地供給六氯乙矽烷、二氯甲矽烷等含有矽之氣體、包含三甲胺、二乙胺、三乙胺、乙二胺所代表之烷基胺之氣體、及氨之ALD來形成。又，期待障壁層31之厚度與第1實施形態同樣地為0.5奈米以下。
根據本實施形態，可藉由障壁層31抑制電荷蓄積膜33與穿隧絕緣膜34之界面上之氮與氧之相互擴散。擴散至穿遂膜中之氮會使穿遂膜之絕緣性劣化，又，擴散至電荷蓄積膜中之氧會形成能階淺之電荷捕獲點，因此均會引起記憶單元之資料保持特性之劣化。根據本實施形態，藉由抑制電荷蓄積膜33與穿隧絕緣膜34之界面反應，可提高對非揮發性半導體記憶裝置之資料保持性能之可靠性。
(第4實施形態) 圖10係表示第4實施形態之半導體記憶裝置之主要部分之構造之剖視圖。對與上述第1實施形態相同之構成要素標註相同符號，並省略詳細之說明。
如圖10所示，於本實施形態之半導體記憶裝置4中，穿隧絕緣膜具有與電荷蓄積膜33對向之第1膜34a、及與通道膜35對向之第2膜34b。障壁層31設置於第1膜34a與第2膜34b之界面。
第1膜34a及第2膜34b均為氮氧化矽膜。其中，第2膜34b之氧濃度高於第1膜34a之氧濃度。另一方面，第2膜34b之氮濃度低於第1膜34a之氮濃度。
於本實施形態中，障壁層31可於第1膜34a之成膜後、第2膜34b之成膜前，與第1實施形態同樣地藉由ALD形成。又，為了確保穿隧絕緣膜34之絕緣性，期待障壁層31中所含有之碳濃度為0.1～10.0 atomic%之範圍內。因此，期待障壁層31係藉由例如交替地供給六氯乙矽烷、二氯甲矽烷等含有矽之氣體、包含三甲胺、二乙胺、三乙胺、乙二胺所代表之烷基胺之氣體、氨、及氧氣或臭氧、一氧化二氮等氧化氣體之ALD形成。又，期待障壁層31之厚度與第1實施形態同樣地為0.5奈米以下。
根據本實施形態，於穿隧絕緣膜內，可藉由障壁層31抑制第1膜34a與第2膜34b之間之氮與氧之相互擴散。擴散至第2膜34b中之氮會使穿遂膜之絕緣性劣化，又，擴散至第1膜34a中之氧會引起寫入刪除動作電壓之增加。於三維積層型半導體記憶裝置之記憶膜中，隨著微細化之進展，有於異種膜之界面部產生材料之相互擴散或變形，引起所捕獲之電子之洩露或重寫動作耐受性之劣化等可靠性惡化之虞。針對此種課題，根據本實施形態，可提高對非揮發性半導體記憶裝置之資料保持性能之可靠性或改善重寫動作等之對電應力之耐受性。
再者，於上述實施形態及變化例中，障壁層31設置於電極層21與記憶膜30之界面或記憶膜30內之界面之任一者，亦可設置於兩界面。又，記憶膜30之積層構成並不限定於上述實施形態及變化例，例如電荷蓄積膜33亦可包含多層，並於其中之界面設置障壁層31。即，障壁層31只要設置於電極層21與記憶膜30之界面、及記憶膜30內之界面之至少一者即可。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為例而提出，並無意圖限定發明之範圍。該等新穎之實施形態可以其他各種方式實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明與其均等之範圍內。
[相關申請案] 本案享有以日本專利申請案2019-50252號(申請日：2019年3月18日)為基礎申請案之優先權。本案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1           半導體記憶裝置 1a          半導體記憶裝置 10          半導體基板 20          積層體 20a        積層體 21          電極層 22          絕緣層 30          記憶膜 31          障壁層 32          阻擋絕緣膜 33          電荷蓄積膜 34          穿隧絕緣膜 34a        第1膜 34b        第2膜 35          通道膜 36          芯絕緣膜 40          孔 211        金屬層 212        障壁金屬層 213        阻擋絕緣膜
圖1係表示第1實施形態之半導體記憶裝置之主要部分之構成之俯視圖。 圖2係沿著圖1所示之剖切線A-A之剖視圖。 圖3係用以說明積層體之形成步驟之剖視圖。 圖4係用以說明孔之形成步驟之剖視圖。 圖5係用以說明障壁層之形成步驟之剖視圖。 圖6係用以說明記憶膜之成膜步驟之剖視圖。 圖7係表示變化例1之半導體記憶裝置之主要部分之構造之剖視圖。 圖8係表示第2實施形態之半導體記憶裝置之主要部分之構造之剖視圖。 圖9係表示第3實施形態之半導體記憶裝置之主要部分之構造之剖視圖。 圖10係表示第4實施形態之半導體記憶裝置之主要部分之構造之剖視圖。
10          半導體基板 20          積層體 21          電極層 22          絕緣層 30          記憶膜 31          障壁層 32          阻擋絕緣膜 33          電荷蓄積膜 34          穿隧絕緣膜 35          通道膜 36          芯絕緣膜 211        金屬層 212        障壁金屬層 213        阻擋絕緣膜

Claims (8)

  1. 一種半導體記憶裝置，其具備：半導體基板；積層體，其於上述半導體基板上將複數個電極層積層而成；記憶膜，其於上述積層體內具有相對於上述電極層沿垂直方向配置之第1阻擋絕緣膜、與上述第1阻擋絕緣膜對向之電荷蓄積膜、與上述電荷蓄積膜對向之穿隧絕緣膜、及與上述穿隧絕緣膜對向之通道膜；及障壁層，其設置於上述複數個電極層與上述記憶膜之界面、及上述記憶膜內之界面之至少一者，並以碳作為主成分；且上述穿隧絕緣膜具有與上述電荷蓄積膜對向之第1膜、及與上述通道膜對向之第2膜，上述第2膜之氧濃度大於上述第1膜之氧濃度；上述障壁層設置於上述第1膜與上述第2膜之界面。
  2. 如請求項1之半導體記憶裝置，其中上述複數個電極層分別具有金屬層、覆蓋上述金屬層之障壁金屬層、及覆蓋上述障壁金屬層之第2阻擋絕緣膜，上述障壁層設置於上述第1阻擋絕緣膜與上述第2阻擋絕緣膜之界面。
  3. 如請求項1之半導體記憶裝置，其中上述障壁層設置於上述第1阻擋絕緣膜與上述電荷蓄積膜之界面。
  4. 如請求項1之半導體記憶裝置，其中上述障壁層設置於上述電荷蓄積膜與上述穿隧絕緣膜之界面。
  5. 一種半導體裝置之製造方法，其於上述半導體基板上形成由複數個電極層積層而成之積層體，於上述積層體內形成記憶膜，上述記憶膜具有相對於上述電極層沿垂直方向配置之第1阻擋絕緣膜、與上述第1阻擋絕緣膜對向之電荷蓄積膜、與上述電荷蓄積膜對向之穿隧絕緣膜、及與上述穿隧絕緣膜對向之通道膜，於上述複數個電極層與上述記憶膜之界面或上述記憶膜內之界面形成以碳作為主成分之障壁層；於上述穿隧絕緣膜形成與上述電荷蓄積膜對向之第1膜、及與上述通道膜對向且氧濃度大於上述第1膜之第2膜；於上述第1膜與上述第2膜之界面形成上述障壁層。
  6. 如請求項5之半導體記憶裝置之製造方法，其中分別於上述複數個電極層形成金屬層、覆蓋上述金屬層之障壁金屬層、及覆蓋上述障壁金屬層之第2阻擋絕緣膜，於上述第1阻擋絕緣膜與上述第2阻擋絕緣膜之界面形成上述障壁層。
  7. 如請求項5之半導體記憶裝置之製造方法，其中於上述第1阻擋絕緣膜與上述電荷蓄積膜之界面形成上述障壁層。
  8. 如請求項5之半導體記憶裝置之製造方法，其中於上述電荷蓄積膜與上述穿隧絕緣膜之界面形成上述障壁層。
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